isa.cc revision 10609
16019Shines@cs.fsu.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010-2014 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 156019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 166019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 176019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 186019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 196019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 206019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 216019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 226019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 236019Shines@cs.fsu.edu * this software without specific prior written permission. 246019Shines@cs.fsu.edu * 256019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 296019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 306019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 326019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366019Shines@cs.fsu.edu * 376019Shines@cs.fsu.edu * Authors: Gabe Black 386019Shines@cs.fsu.edu * Ali Saidi 396019Shines@cs.fsu.edu */ 406019Shines@cs.fsu.edu 416735Sgblack@eecs.umich.edu#include "arch/arm/isa.hh" 426735Sgblack@eecs.umich.edu#include "arch/arm/pmu.hh" 436019Shines@cs.fsu.edu#include "arch/arm/system.hh" 446019Shines@cs.fsu.edu#include "cpu/checker/cpu.hh" 456019Shines@cs.fsu.edu#include "cpu/base.hh" 466019Shines@cs.fsu.edu#include "debug/Arm.hh" 476019Shines@cs.fsu.edu#include "debug/MiscRegs.hh" 486019Shines@cs.fsu.edu#include "params/ArmISA.hh" 496019Shines@cs.fsu.edu#include "sim/faults.hh" 506019Shines@cs.fsu.edu#include "sim/stat_control.hh" 516019Shines@cs.fsu.edu#include "sim/system.hh" 526019Shines@cs.fsu.edu 537362Sgblack@eecs.umich.edunamespace ArmISA 546735Sgblack@eecs.umich.edu{ 556019Shines@cs.fsu.edu 567362Sgblack@eecs.umich.edu 576735Sgblack@eecs.umich.edu/** 586019Shines@cs.fsu.edu * Some registers aliase with others, and therefore need to be translated. 597362Sgblack@eecs.umich.edu * For each entry: 606735Sgblack@eecs.umich.edu * The first value is the misc register that is to be looked up 616019Shines@cs.fsu.edu * the second value is the lower part of the translation 627362Sgblack@eecs.umich.edu * the third the upper part 636735Sgblack@eecs.umich.edu */ 646019Shines@cs.fsu.educonst struct ISA::MiscRegInitializerEntry 657362Sgblack@eecs.umich.edu ISA::MiscRegSwitch[miscRegTranslateMax] = { 666735Sgblack@eecs.umich.edu {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}}, 676019Shines@cs.fsu.edu {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}}, 687362Sgblack@eecs.umich.edu {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 696735Sgblack@eecs.umich.edu {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}}, 706019Shines@cs.fsu.edu {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 717362Sgblack@eecs.umich.edu {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 726735Sgblack@eecs.umich.edu {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 736019Shines@cs.fsu.edu {MISCREG_HCR_EL2, {MISCREG_HCR, 0}}, 747652Sminkyu.jeong@arm.com {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 757652Sminkyu.jeong@arm.com {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 767652Sminkyu.jeong@arm.com {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 776735Sgblack@eecs.umich.edu {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}}, 787362Sgblack@eecs.umich.edu {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}}, 796735Sgblack@eecs.umich.edu {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 806735Sgblack@eecs.umich.edu {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 816019Shines@cs.fsu.edu {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}}, 826735Sgblack@eecs.umich.edu {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 837400SAli.Saidi@ARM.com {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 846735Sgblack@eecs.umich.edu {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}}, 856735Sgblack@eecs.umich.edu {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}}, 866735Sgblack@eecs.umich.edu {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 877400SAli.Saidi@ARM.com {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 886735Sgblack@eecs.umich.edu {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 896735Sgblack@eecs.umich.edu {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}}, 906735Sgblack@eecs.umich.edu {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 916019Shines@cs.fsu.edu {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 926019Shines@cs.fsu.edu {MISCREG_PAR_EL1, {MISCREG_PAR, 0}}, 936019Shines@cs.fsu.edu {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}}, 946735Sgblack@eecs.umich.edu {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 956735Sgblack@eecs.umich.edu {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}}, 966735Sgblack@eecs.umich.edu {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}}, 977678Sgblack@eecs.umich.edu {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 986019Shines@cs.fsu.edu {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}}, 996735Sgblack@eecs.umich.edu {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}}, 1006735Sgblack@eecs.umich.edu {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}}, 1016735Sgblack@eecs.umich.edu {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}}, 1026019Shines@cs.fsu.edu {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 1036735Sgblack@eecs.umich.edu {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}}, 1046735Sgblack@eecs.umich.edu {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 1056735Sgblack@eecs.umich.edu {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, 1066735Sgblack@eecs.umich.edu {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, 1077720Sgblack@eecs.umich.edu {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, 1086735Sgblack@eecs.umich.edu {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 1096735Sgblack@eecs.umich.edu {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 1106735Sgblack@eecs.umich.edu {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}}, 1116735Sgblack@eecs.umich.edu {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}}, 1126735Sgblack@eecs.umich.edu {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}}, 1136735Sgblack@eecs.umich.edu {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 1147093Sgblack@eecs.umich.edu {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 1156735Sgblack@eecs.umich.edu {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, 1166735Sgblack@eecs.umich.edu {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 1176735Sgblack@eecs.umich.edu {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 1187302Sgblack@eecs.umich.edu {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, 1196735Sgblack@eecs.umich.edu {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}}, 1207720Sgblack@eecs.umich.edu {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}}, 1216735Sgblack@eecs.umich.edu {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}}, 1226735Sgblack@eecs.umich.edu {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}} 1236735Sgblack@eecs.umich.edu}; 1246735Sgblack@eecs.umich.edu 1256735Sgblack@eecs.umich.edu 1266735Sgblack@eecs.umich.eduISA::ISA(Params *p) 1276735Sgblack@eecs.umich.edu : SimObject(p), 1286735Sgblack@eecs.umich.edu system(NULL), 1296735Sgblack@eecs.umich.edu pmu(p->pmu), 1306735Sgblack@eecs.umich.edu lookUpMiscReg(NUM_MISCREGS, {0,0}) 1316735Sgblack@eecs.umich.edu{ 1326735Sgblack@eecs.umich.edu SCTLR sctlr; 1336735Sgblack@eecs.umich.edu sctlr = 0; 1346735Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr; 1356735Sgblack@eecs.umich.edu 1366735Sgblack@eecs.umich.edu // Hook up a dummy device if we haven't been configured with a 1376735Sgblack@eecs.umich.edu // real PMU. By using a dummy device, we don't need to check that 1386735Sgblack@eecs.umich.edu // the PMU exist every time we try to access a PMU register. 1396735Sgblack@eecs.umich.edu if (!pmu) 1406735Sgblack@eecs.umich.edu pmu = &dummyDevice; 1417093Sgblack@eecs.umich.edu 1427093Sgblack@eecs.umich.edu // Give all ISA devices a pointer to this ISA 1437720Sgblack@eecs.umich.edu pmu->setISA(this); 1447585SAli.Saidi@arm.com 1457720Sgblack@eecs.umich.edu system = dynamic_cast<ArmSystem *>(p->system); 1467720Sgblack@eecs.umich.edu DPRINTFN("ISA system set to: %p %p\n", system, p->system); 1477720Sgblack@eecs.umich.edu 1487720Sgblack@eecs.umich.edu // Cache system-level properties 1497720Sgblack@eecs.umich.edu if (FullSystem && system) { 1507720Sgblack@eecs.umich.edu haveSecurity = system->haveSecurity(); 1517720Sgblack@eecs.umich.edu haveLPAE = system->haveLPAE(); 1526019Shines@cs.fsu.edu haveVirtualization = system->haveVirtualization(); 1537189Sgblack@eecs.umich.edu haveLargeAsid64 = system->haveLargeAsid64(); 1547400SAli.Saidi@ARM.com physAddrRange64 = system->physAddrRange64(); 1557678Sgblack@eecs.umich.edu } else { 1567400SAli.Saidi@ARM.com haveSecurity = haveLPAE = haveVirtualization = false; 1577400SAli.Saidi@ARM.com haveLargeAsid64 = false; 1587400SAli.Saidi@ARM.com physAddrRange64 = 32; // dummy value 1597400SAli.Saidi@ARM.com } 1607400SAli.Saidi@ARM.com 1617400SAli.Saidi@ARM.com /** Fill in the miscReg translation table */ 1627189Sgblack@eecs.umich.edu for (uint32_t i = 0; i < miscRegTranslateMax; i++) { 1637189Sgblack@eecs.umich.edu struct MiscRegLUTEntry new_entry; 1647189Sgblack@eecs.umich.edu 1657678Sgblack@eecs.umich.edu uint32_t select = MiscRegSwitch[i].index; 1667189Sgblack@eecs.umich.edu new_entry = MiscRegSwitch[i].entry; 1677640Sgblack@eecs.umich.edu 1687189Sgblack@eecs.umich.edu lookUpMiscReg[select] = new_entry; 1697640Sgblack@eecs.umich.edu } 1707640Sgblack@eecs.umich.edu 1717640Sgblack@eecs.umich.edu preUnflattenMiscReg(); 1727640Sgblack@eecs.umich.edu 1737426Sgblack@eecs.umich.edu clear(); 1747426Sgblack@eecs.umich.edu} 1757189Sgblack@eecs.umich.edu 1767426Sgblack@eecs.umich.educonst ArmISAParams * 1777426Sgblack@eecs.umich.eduISA::params() const 1787189Sgblack@eecs.umich.edu{ 1797189Sgblack@eecs.umich.edu return dynamic_cast<const Params *>(_params); 1807189Sgblack@eecs.umich.edu} 1817197Sgblack@eecs.umich.edu 1827678Sgblack@eecs.umich.eduvoid 1837197Sgblack@eecs.umich.eduISA::clear() 1847197Sgblack@eecs.umich.edu{ 1857197Sgblack@eecs.umich.edu const Params *p(params()); 1867197Sgblack@eecs.umich.edu 1877197Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 1887197Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 1897197Sgblack@eecs.umich.edu 1907197Sgblack@eecs.umich.edu // Initialize configurable default values 1917197Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR] = p->midr; 1927197Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR_EL1] = p->midr; 1937197Sgblack@eecs.umich.edu miscRegs[MISCREG_VPIDR] = p->midr; 1947197Sgblack@eecs.umich.edu 1957197Sgblack@eecs.umich.edu if (FullSystem && system->highestELIs64()) { 1967197Sgblack@eecs.umich.edu // Initialize AArch64 state 1977197Sgblack@eecs.umich.edu clear64(p); 1987720Sgblack@eecs.umich.edu return; 1997720Sgblack@eecs.umich.edu } 2007720Sgblack@eecs.umich.edu 2017720Sgblack@eecs.umich.edu // Initialize AArch32 state... 2027197Sgblack@eecs.umich.edu 2037197Sgblack@eecs.umich.edu CPSR cpsr = 0; 2046019Shines@cs.fsu.edu cpsr.mode = MODE_USER; 2056019Shines@cs.fsu.edu miscRegs[MISCREG_CPSR] = cpsr; 2067362Sgblack@eecs.umich.edu updateRegMap(cpsr); 2077362Sgblack@eecs.umich.edu 2087678Sgblack@eecs.umich.edu SCTLR sctlr = 0; 2097362Sgblack@eecs.umich.edu sctlr.te = (bool) sctlr_rst.te; 2107362Sgblack@eecs.umich.edu sctlr.nmfi = (bool) sctlr_rst.nmfi; 2117362Sgblack@eecs.umich.edu sctlr.v = (bool) sctlr_rst.v; 2127362Sgblack@eecs.umich.edu sctlr.u = 1; 2137362Sgblack@eecs.umich.edu sctlr.xp = 1; 2147362Sgblack@eecs.umich.edu sctlr.rao2 = 1; 2157362Sgblack@eecs.umich.edu sctlr.rao3 = 1; 2167362Sgblack@eecs.umich.edu sctlr.rao4 = 0xf; // SCTLR[6:3] 2177362Sgblack@eecs.umich.edu sctlr.uci = 1; 2187362Sgblack@eecs.umich.edu sctlr.dze = 1; 2197362Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_NS] = sctlr; 2207362Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 2217652Sminkyu.jeong@arm.com miscRegs[MISCREG_HCPTR] = 0; 2227678Sgblack@eecs.umich.edu 2237652Sminkyu.jeong@arm.com // Start with an event in the mailbox 2247652Sminkyu.jeong@arm.com miscRegs[MISCREG_SEV_MAILBOX] = 1; 2257652Sminkyu.jeong@arm.com 2267652Sminkyu.jeong@arm.com // Separate Instruction and Data TLBs 2277652Sminkyu.jeong@arm.com miscRegs[MISCREG_TLBTR] = 1; 2287720Sgblack@eecs.umich.edu 2297720Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 2307720Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 2317720Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 2327652Sminkyu.jeong@arm.com mvfr0.doublePrecision = 2; 2337652Sminkyu.jeong@arm.com mvfr0.vfpExceptionTrapping = 0; 2347678Sgblack@eecs.umich.edu mvfr0.divide = 1; 2357678Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 2367678Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 2377678Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 2387362Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 2396735Sgblack@eecs.umich.edu 2406019Shines@cs.fsu.edu MVFR1 mvfr1 = 0; 2416019Shines@cs.fsu.edu mvfr1.flushToZero = 1; 242 mvfr1.defaultNaN = 1; 243 mvfr1.advSimdLoadStore = 1; 244 mvfr1.advSimdInteger = 1; 245 mvfr1.advSimdSinglePrecision = 1; 246 mvfr1.advSimdHalfPrecision = 1; 247 mvfr1.vfpHalfPrecision = 1; 248 miscRegs[MISCREG_MVFR1] = mvfr1; 249 250 // Reset values of PRRR and NMRR are implementation dependent 251 252 // @todo: PRRR and NMRR in secure state? 253 miscRegs[MISCREG_PRRR_NS] = 254 (1 << 19) | // 19 255 (0 << 18) | // 18 256 (0 << 17) | // 17 257 (1 << 16) | // 16 258 (2 << 14) | // 15:14 259 (0 << 12) | // 13:12 260 (2 << 10) | // 11:10 261 (2 << 8) | // 9:8 262 (2 << 6) | // 7:6 263 (2 << 4) | // 5:4 264 (1 << 2) | // 3:2 265 0; // 1:0 266 miscRegs[MISCREG_NMRR_NS] = 267 (1 << 30) | // 31:30 268 (0 << 26) | // 27:26 269 (0 << 24) | // 25:24 270 (3 << 22) | // 23:22 271 (2 << 20) | // 21:20 272 (0 << 18) | // 19:18 273 (0 << 16) | // 17:16 274 (1 << 14) | // 15:14 275 (0 << 12) | // 13:12 276 (2 << 10) | // 11:10 277 (0 << 8) | // 9:8 278 (3 << 6) | // 7:6 279 (2 << 4) | // 5:4 280 (0 << 2) | // 3:2 281 0; // 1:0 282 283 miscRegs[MISCREG_CPACR] = 0; 284 285 286 miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 287 miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 288 289 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 290 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 291 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 292 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 293 294 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 295 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 296 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 297 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 298 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 299 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 300 301 miscRegs[MISCREG_FPSID] = p->fpsid; 302 303 if (haveLPAE) { 304 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 305 ttbcr.eae = 0; 306 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 307 // Enforce consistency with system-level settings 308 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 309 } 310 311 if (haveSecurity) { 312 miscRegs[MISCREG_SCTLR_S] = sctlr; 313 miscRegs[MISCREG_SCR] = 0; 314 miscRegs[MISCREG_VBAR_S] = 0; 315 } else { 316 // we're always non-secure 317 miscRegs[MISCREG_SCR] = 1; 318 } 319 320 //XXX We need to initialize the rest of the state. 321} 322 323void 324ISA::clear64(const ArmISAParams *p) 325{ 326 CPSR cpsr = 0; 327 Addr rvbar = system->resetAddr64(); 328 switch (system->highestEL()) { 329 // Set initial EL to highest implemented EL using associated stack 330 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 331 // value 332 case EL3: 333 cpsr.mode = MODE_EL3H; 334 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 335 break; 336 case EL2: 337 cpsr.mode = MODE_EL2H; 338 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 339 break; 340 case EL1: 341 cpsr.mode = MODE_EL1H; 342 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 343 break; 344 default: 345 panic("Invalid highest implemented exception level"); 346 break; 347 } 348 349 // Initialize rest of CPSR 350 cpsr.daif = 0xf; // Mask all interrupts 351 cpsr.ss = 0; 352 cpsr.il = 0; 353 miscRegs[MISCREG_CPSR] = cpsr; 354 updateRegMap(cpsr); 355 356 // Initialize other control registers 357 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 358 if (haveSecurity) { 359 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870; 360 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 361 // @todo: uncomment this to enable Virtualization 362 // } else if (haveVirtualization) { 363 // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870; 364 } else { 365 miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870; 366 // Always non-secure 367 miscRegs[MISCREG_SCR_EL3] = 1; 368 } 369 370 // Initialize configurable id registers 371 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 372 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 373 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 374 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 375 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 376 377 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 378 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 379 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 380 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 381 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 382 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 383 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; 384 385 miscRegs[MISCREG_ID_DFR0_EL1] = 386 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 387 388 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 389 390 // Enforce consistency with system-level settings... 391 392 // EL3 393 // (no AArch32/64 interprocessing support for now) 394 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 395 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 396 haveSecurity ? 0x1 : 0x0); 397 // EL2 398 // (no AArch32/64 interprocessing support for now) 399 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 400 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 401 haveVirtualization ? 0x1 : 0x0); 402 // Large ASID support 403 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 404 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 405 haveLargeAsid64 ? 0x2 : 0x0); 406 // Physical address size 407 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 408 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 409 encodePhysAddrRange64(physAddrRange64)); 410} 411 412MiscReg 413ISA::readMiscRegNoEffect(int misc_reg) const 414{ 415 assert(misc_reg < NumMiscRegs); 416 417 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 418 // registers are left unchanged 419 MiscReg val; 420 421 if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR 422 || flat_idx == MISCREG_SCTLR_EL1) { 423 if (flat_idx == MISCREG_SPSR) 424 flat_idx = flattenMiscIndex(MISCREG_SPSR); 425 if (flat_idx == MISCREG_SCTLR_EL1) 426 flat_idx = flattenMiscIndex(MISCREG_SCTLR); 427 val = miscRegs[flat_idx]; 428 } else 429 if (lookUpMiscReg[flat_idx].upper > 0) 430 val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32)) 431 | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32)); 432 else 433 val = miscRegs[lookUpMiscReg[flat_idx].lower]; 434 435 return val; 436} 437 438 439MiscReg 440ISA::readMiscReg(int misc_reg, ThreadContext *tc) 441{ 442 CPSR cpsr = 0; 443 PCState pc = 0; 444 SCR scr = 0; 445 446 if (misc_reg == MISCREG_CPSR) { 447 cpsr = miscRegs[misc_reg]; 448 pc = tc->pcState(); 449 cpsr.j = pc.jazelle() ? 1 : 0; 450 cpsr.t = pc.thumb() ? 1 : 0; 451 return cpsr; 452 } 453 454#ifndef NDEBUG 455 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 456 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 457 warn("Unimplemented system register %s read.\n", 458 miscRegName[misc_reg]); 459 else 460 panic("Unimplemented system register %s read.\n", 461 miscRegName[misc_reg]); 462 } 463#endif 464 465 switch (unflattenMiscReg(misc_reg)) { 466 case MISCREG_HCR: 467 { 468 if (!haveVirtualization) 469 return 0; 470 else 471 return readMiscRegNoEffect(MISCREG_HCR); 472 } 473 case MISCREG_CPACR: 474 { 475 const uint32_t ones = (uint32_t)(-1); 476 CPACR cpacrMask = 0; 477 // Only cp10, cp11, and ase are implemented, nothing else should 478 // be readable? (straight copy from the write code) 479 cpacrMask.cp10 = ones; 480 cpacrMask.cp11 = ones; 481 cpacrMask.asedis = ones; 482 483 // Security Extensions may limit the readability of CPACR 484 if (haveSecurity) { 485 scr = readMiscRegNoEffect(MISCREG_SCR); 486 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 487 if (scr.ns && (cpsr.mode != MODE_MON)) { 488 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 489 // NB: Skipping the full loop, here 490 if (!nsacr.cp10) cpacrMask.cp10 = 0; 491 if (!nsacr.cp11) cpacrMask.cp11 = 0; 492 } 493 } 494 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 495 val &= cpacrMask; 496 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 497 miscRegName[misc_reg], val); 498 return val; 499 } 500 case MISCREG_MPIDR: 501 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 502 scr = readMiscRegNoEffect(MISCREG_SCR); 503 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 504 return getMPIDR(system, tc); 505 } else { 506 return readMiscReg(MISCREG_VMPIDR, tc); 507 } 508 break; 509 case MISCREG_MPIDR_EL1: 510 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 511 return getMPIDR(system, tc) & 0xffffffff; 512 case MISCREG_VMPIDR: 513 // top bit defined as RES1 514 return readMiscRegNoEffect(misc_reg) | 0x80000000; 515 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 516 case MISCREG_REVIDR: // not implemented, so alias MIDR 517 case MISCREG_MIDR: 518 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 519 scr = readMiscRegNoEffect(MISCREG_SCR); 520 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 521 return readMiscRegNoEffect(misc_reg); 522 } else { 523 return readMiscRegNoEffect(MISCREG_VPIDR); 524 } 525 break; 526 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 527 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 528 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 529 case MISCREG_AIDR: // AUX ID set to 0 530 case MISCREG_TCMTR: // No TCM's 531 return 0; 532 533 case MISCREG_CLIDR: 534 warn_once("The clidr register always reports 0 caches.\n"); 535 warn_once("clidr LoUIS field of 0b001 to match current " 536 "ARM implementations.\n"); 537 return 0x00200000; 538 case MISCREG_CCSIDR: 539 warn_once("The ccsidr register isn't implemented and " 540 "always reads as 0.\n"); 541 break; 542 case MISCREG_CTR: 543 { 544 //all caches have the same line size in gem5 545 //4 byte words in ARM 546 unsigned lineSizeWords = 547 tc->getSystemPtr()->cacheLineSize() / 4; 548 unsigned log2LineSizeWords = 0; 549 550 while (lineSizeWords >>= 1) { 551 ++log2LineSizeWords; 552 } 553 554 CTR ctr = 0; 555 //log2 of minimun i-cache line size (words) 556 ctr.iCacheLineSize = log2LineSizeWords; 557 //b11 - gem5 uses pipt 558 ctr.l1IndexPolicy = 0x3; 559 //log2 of minimum d-cache line size (words) 560 ctr.dCacheLineSize = log2LineSizeWords; 561 //log2 of max reservation size (words) 562 ctr.erg = log2LineSizeWords; 563 //log2 of max writeback size (words) 564 ctr.cwg = log2LineSizeWords; 565 //b100 - gem5 format is ARMv7 566 ctr.format = 0x4; 567 568 return ctr; 569 } 570 case MISCREG_ACTLR: 571 warn("Not doing anything for miscreg ACTLR\n"); 572 break; 573 574 case MISCREG_PMXEVTYPER_PMCCFILTR: 575 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 576 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 577 case MISCREG_PMCR ... MISCREG_PMOVSSET: 578 return pmu->readMiscReg(misc_reg); 579 580 case MISCREG_CPSR_Q: 581 panic("shouldn't be reading this register seperately\n"); 582 case MISCREG_FPSCR_QC: 583 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 584 case MISCREG_FPSCR_EXC: 585 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 586 case MISCREG_FPSR: 587 { 588 const uint32_t ones = (uint32_t)(-1); 589 FPSCR fpscrMask = 0; 590 fpscrMask.ioc = ones; 591 fpscrMask.dzc = ones; 592 fpscrMask.ofc = ones; 593 fpscrMask.ufc = ones; 594 fpscrMask.ixc = ones; 595 fpscrMask.idc = ones; 596 fpscrMask.qc = ones; 597 fpscrMask.v = ones; 598 fpscrMask.c = ones; 599 fpscrMask.z = ones; 600 fpscrMask.n = ones; 601 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 602 } 603 case MISCREG_FPCR: 604 { 605 const uint32_t ones = (uint32_t)(-1); 606 FPSCR fpscrMask = 0; 607 fpscrMask.ioe = ones; 608 fpscrMask.dze = ones; 609 fpscrMask.ofe = ones; 610 fpscrMask.ufe = ones; 611 fpscrMask.ixe = ones; 612 fpscrMask.ide = ones; 613 fpscrMask.len = ones; 614 fpscrMask.stride = ones; 615 fpscrMask.rMode = ones; 616 fpscrMask.fz = ones; 617 fpscrMask.dn = ones; 618 fpscrMask.ahp = ones; 619 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 620 } 621 case MISCREG_NZCV: 622 { 623 CPSR cpsr = 0; 624 cpsr.nz = tc->readCCReg(CCREG_NZ); 625 cpsr.c = tc->readCCReg(CCREG_C); 626 cpsr.v = tc->readCCReg(CCREG_V); 627 return cpsr; 628 } 629 case MISCREG_DAIF: 630 { 631 CPSR cpsr = 0; 632 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 633 return cpsr; 634 } 635 case MISCREG_SP_EL0: 636 { 637 return tc->readIntReg(INTREG_SP0); 638 } 639 case MISCREG_SP_EL1: 640 { 641 return tc->readIntReg(INTREG_SP1); 642 } 643 case MISCREG_SP_EL2: 644 { 645 return tc->readIntReg(INTREG_SP2); 646 } 647 case MISCREG_SPSEL: 648 { 649 return miscRegs[MISCREG_CPSR] & 0x1; 650 } 651 case MISCREG_CURRENTEL: 652 { 653 return miscRegs[MISCREG_CPSR] & 0xc; 654 } 655 case MISCREG_L2CTLR: 656 { 657 // mostly unimplemented, just set NumCPUs field from sim and return 658 L2CTLR l2ctlr = 0; 659 // b00:1CPU to b11:4CPUs 660 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 661 return l2ctlr; 662 } 663 case MISCREG_DBGDIDR: 664 /* For now just implement the version number. 665 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 666 */ 667 return 0x5 << 16; 668 case MISCREG_DBGDSCRint: 669 return 0; 670 case MISCREG_ISR: 671 return tc->getCpuPtr()->getInterruptController()->getISR( 672 readMiscRegNoEffect(MISCREG_HCR), 673 readMiscRegNoEffect(MISCREG_CPSR), 674 readMiscRegNoEffect(MISCREG_SCR)); 675 case MISCREG_ISR_EL1: 676 return tc->getCpuPtr()->getInterruptController()->getISR( 677 readMiscRegNoEffect(MISCREG_HCR_EL2), 678 readMiscRegNoEffect(MISCREG_CPSR), 679 readMiscRegNoEffect(MISCREG_SCR_EL3)); 680 case MISCREG_DCZID_EL0: 681 return 0x04; // DC ZVA clear 64-byte chunks 682 case MISCREG_HCPTR: 683 { 684 MiscReg val = readMiscRegNoEffect(misc_reg); 685 // The trap bit associated with CP14 is defined as RAZ 686 val &= ~(1 << 14); 687 // If a CP bit in NSACR is 0 then the corresponding bit in 688 // HCPTR is RAO/WI 689 bool secure_lookup = haveSecurity && 690 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 691 readMiscRegNoEffect(MISCREG_CPSR)); 692 if (!secure_lookup) { 693 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 694 val |= (mask ^ 0x7FFF) & 0xBFFF; 695 } 696 // Set the bits for unimplemented coprocessors to RAO/WI 697 val |= 0x33FF; 698 return (val); 699 } 700 case MISCREG_HDFAR: // alias for secure DFAR 701 return readMiscRegNoEffect(MISCREG_DFAR_S); 702 case MISCREG_HIFAR: // alias for secure IFAR 703 return readMiscRegNoEffect(MISCREG_IFAR_S); 704 case MISCREG_HVBAR: // bottom bits reserved 705 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 706 case MISCREG_SCTLR: // Some bits hardwired 707 // The FI field (bit 21) is common between S/NS versions of the register 708 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 709 (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR 710 case MISCREG_SCTLR_EL1: 711 // The FI field (bit 21) is common between S/NS versions of the register 712 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 713 (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1 714 case MISCREG_SCTLR_EL3: 715 // The FI field (bit 21) is common between S/NS versions of the register 716 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 717 (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3 718 case MISCREG_HSCTLR: // FI comes from SCTLR 719 { 720 uint32_t mask = 1 << 27; 721 return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) | 722 (readMiscRegNoEffect(MISCREG_SCTLR) & mask); 723 } 724 case MISCREG_SCR: 725 { 726 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 727 if (cpsr.width) { 728 return readMiscRegNoEffect(MISCREG_SCR); 729 } else { 730 return readMiscRegNoEffect(MISCREG_SCR_EL3); 731 } 732 } 733 // Generic Timer registers 734 case MISCREG_CNTFRQ: 735 case MISCREG_CNTFRQ_EL0: 736 inform_once("Read CNTFREQ_EL0 frequency\n"); 737 return getSystemCounter(tc)->freq(); 738 case MISCREG_CNTPCT: 739 case MISCREG_CNTPCT_EL0: 740 return getSystemCounter(tc)->value(); 741 case MISCREG_CNTVCT: 742 return getSystemCounter(tc)->value(); 743 case MISCREG_CNTVCT_EL0: 744 return getSystemCounter(tc)->value(); 745 case MISCREG_CNTP_CVAL: 746 case MISCREG_CNTP_CVAL_EL0: 747 return getArchTimer(tc, tc->cpuId())->compareValue(); 748 case MISCREG_CNTP_TVAL: 749 case MISCREG_CNTP_TVAL_EL0: 750 return getArchTimer(tc, tc->cpuId())->timerValue(); 751 case MISCREG_CNTP_CTL: 752 case MISCREG_CNTP_CTL_EL0: 753 return getArchTimer(tc, tc->cpuId())->control(); 754 // PL1 phys. timer, secure 755 // AArch64 756 // case MISCREG_CNTPS_CVAL_EL1: 757 // case MISCREG_CNTPS_TVAL_EL1: 758 // case MISCREG_CNTPS_CTL_EL1: 759 // PL2 phys. timer, non-secure 760 // AArch32 761 // case MISCREG_CNTHCTL: 762 // case MISCREG_CNTHP_CVAL: 763 // case MISCREG_CNTHP_TVAL: 764 // case MISCREG_CNTHP_CTL: 765 // AArch64 766 // case MISCREG_CNTHCTL_EL2: 767 // case MISCREG_CNTHP_CVAL_EL2: 768 // case MISCREG_CNTHP_TVAL_EL2: 769 // case MISCREG_CNTHP_CTL_EL2: 770 // Virtual timer 771 // AArch32 772 // case MISCREG_CNTV_CVAL: 773 // case MISCREG_CNTV_TVAL: 774 // case MISCREG_CNTV_CTL: 775 // AArch64 776 // case MISCREG_CNTV_CVAL_EL2: 777 // case MISCREG_CNTV_TVAL_EL2: 778 // case MISCREG_CNTV_CTL_EL2: 779 default: 780 break; 781 782 } 783 return readMiscRegNoEffect(misc_reg); 784} 785 786void 787ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 788{ 789 assert(misc_reg < NumMiscRegs); 790 791 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 792 // registers are left unchanged 793 794 int flat_idx2 = lookUpMiscReg[flat_idx].upper; 795 796 if (flat_idx2 > 0) { 797 miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0); 798 miscRegs[flat_idx2] = bits(val, 63, 32); 799 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 800 misc_reg, flat_idx, flat_idx2, val); 801 } else { 802 if (flat_idx == MISCREG_SPSR) 803 flat_idx = flattenMiscIndex(MISCREG_SPSR); 804 else if (flat_idx == MISCREG_SCTLR_EL1) 805 flat_idx = flattenMiscIndex(MISCREG_SCTLR); 806 else 807 flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ? 808 lookUpMiscReg[flat_idx].lower : flat_idx; 809 miscRegs[flat_idx] = val; 810 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 811 misc_reg, flat_idx, val); 812 } 813} 814 815void 816ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 817{ 818 819 MiscReg newVal = val; 820 int x; 821 bool secure_lookup; 822 bool hyp; 823 System *sys; 824 ThreadContext *oc; 825 uint8_t target_el; 826 uint16_t asid; 827 SCR scr; 828 829 if (misc_reg == MISCREG_CPSR) { 830 updateRegMap(val); 831 832 833 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 834 int old_mode = old_cpsr.mode; 835 CPSR cpsr = val; 836 if (old_mode != cpsr.mode) { 837 tc->getITBPtr()->invalidateMiscReg(); 838 tc->getDTBPtr()->invalidateMiscReg(); 839 } 840 841 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 842 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 843 PCState pc = tc->pcState(); 844 pc.nextThumb(cpsr.t); 845 pc.nextJazelle(cpsr.j); 846 847 // Follow slightly different semantics if a CheckerCPU object 848 // is connected 849 CheckerCPU *checker = tc->getCheckerCpuPtr(); 850 if (checker) { 851 tc->pcStateNoRecord(pc); 852 } else { 853 tc->pcState(pc); 854 } 855 } else { 856#ifndef NDEBUG 857 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 858 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 859 warn("Unimplemented system register %s write with %#x.\n", 860 miscRegName[misc_reg], val); 861 else 862 panic("Unimplemented system register %s write with %#x.\n", 863 miscRegName[misc_reg], val); 864 } 865#endif 866 switch (unflattenMiscReg(misc_reg)) { 867 case MISCREG_CPACR: 868 { 869 870 const uint32_t ones = (uint32_t)(-1); 871 CPACR cpacrMask = 0; 872 // Only cp10, cp11, and ase are implemented, nothing else should 873 // be writable 874 cpacrMask.cp10 = ones; 875 cpacrMask.cp11 = ones; 876 cpacrMask.asedis = ones; 877 878 // Security Extensions may limit the writability of CPACR 879 if (haveSecurity) { 880 scr = readMiscRegNoEffect(MISCREG_SCR); 881 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 882 if (scr.ns && (cpsr.mode != MODE_MON)) { 883 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 884 // NB: Skipping the full loop, here 885 if (!nsacr.cp10) cpacrMask.cp10 = 0; 886 if (!nsacr.cp11) cpacrMask.cp11 = 0; 887 } 888 } 889 890 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 891 newVal &= cpacrMask; 892 newVal |= old_val & ~cpacrMask; 893 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 894 miscRegName[misc_reg], newVal); 895 } 896 break; 897 case MISCREG_CPACR_EL1: 898 { 899 const uint32_t ones = (uint32_t)(-1); 900 CPACR cpacrMask = 0; 901 cpacrMask.tta = ones; 902 cpacrMask.fpen = ones; 903 newVal &= cpacrMask; 904 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 905 miscRegName[misc_reg], newVal); 906 } 907 break; 908 case MISCREG_CPTR_EL2: 909 { 910 const uint32_t ones = (uint32_t)(-1); 911 CPTR cptrMask = 0; 912 cptrMask.tcpac = ones; 913 cptrMask.tta = ones; 914 cptrMask.tfp = ones; 915 newVal &= cptrMask; 916 cptrMask = 0; 917 cptrMask.res1_13_12_el2 = ones; 918 cptrMask.res1_9_0_el2 = ones; 919 newVal |= cptrMask; 920 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 921 miscRegName[misc_reg], newVal); 922 } 923 break; 924 case MISCREG_CPTR_EL3: 925 { 926 const uint32_t ones = (uint32_t)(-1); 927 CPTR cptrMask = 0; 928 cptrMask.tcpac = ones; 929 cptrMask.tta = ones; 930 cptrMask.tfp = ones; 931 newVal &= cptrMask; 932 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 933 miscRegName[misc_reg], newVal); 934 } 935 break; 936 case MISCREG_CSSELR: 937 warn_once("The csselr register isn't implemented.\n"); 938 return; 939 940 case MISCREG_DC_ZVA_Xt: 941 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 942 return; 943 944 case MISCREG_FPSCR: 945 { 946 const uint32_t ones = (uint32_t)(-1); 947 FPSCR fpscrMask = 0; 948 fpscrMask.ioc = ones; 949 fpscrMask.dzc = ones; 950 fpscrMask.ofc = ones; 951 fpscrMask.ufc = ones; 952 fpscrMask.ixc = ones; 953 fpscrMask.idc = ones; 954 fpscrMask.ioe = ones; 955 fpscrMask.dze = ones; 956 fpscrMask.ofe = ones; 957 fpscrMask.ufe = ones; 958 fpscrMask.ixe = ones; 959 fpscrMask.ide = ones; 960 fpscrMask.len = ones; 961 fpscrMask.stride = ones; 962 fpscrMask.rMode = ones; 963 fpscrMask.fz = ones; 964 fpscrMask.dn = ones; 965 fpscrMask.ahp = ones; 966 fpscrMask.qc = ones; 967 fpscrMask.v = ones; 968 fpscrMask.c = ones; 969 fpscrMask.z = ones; 970 fpscrMask.n = ones; 971 newVal = (newVal & (uint32_t)fpscrMask) | 972 (readMiscRegNoEffect(MISCREG_FPSCR) & 973 ~(uint32_t)fpscrMask); 974 tc->getDecoderPtr()->setContext(newVal); 975 } 976 break; 977 case MISCREG_FPSR: 978 { 979 const uint32_t ones = (uint32_t)(-1); 980 FPSCR fpscrMask = 0; 981 fpscrMask.ioc = ones; 982 fpscrMask.dzc = ones; 983 fpscrMask.ofc = ones; 984 fpscrMask.ufc = ones; 985 fpscrMask.ixc = ones; 986 fpscrMask.idc = ones; 987 fpscrMask.qc = ones; 988 fpscrMask.v = ones; 989 fpscrMask.c = ones; 990 fpscrMask.z = ones; 991 fpscrMask.n = ones; 992 newVal = (newVal & (uint32_t)fpscrMask) | 993 (readMiscRegNoEffect(MISCREG_FPSCR) & 994 ~(uint32_t)fpscrMask); 995 misc_reg = MISCREG_FPSCR; 996 } 997 break; 998 case MISCREG_FPCR: 999 { 1000 const uint32_t ones = (uint32_t)(-1); 1001 FPSCR fpscrMask = 0; 1002 fpscrMask.ioe = ones; 1003 fpscrMask.dze = ones; 1004 fpscrMask.ofe = ones; 1005 fpscrMask.ufe = ones; 1006 fpscrMask.ixe = ones; 1007 fpscrMask.ide = ones; 1008 fpscrMask.len = ones; 1009 fpscrMask.stride = ones; 1010 fpscrMask.rMode = ones; 1011 fpscrMask.fz = ones; 1012 fpscrMask.dn = ones; 1013 fpscrMask.ahp = ones; 1014 newVal = (newVal & (uint32_t)fpscrMask) | 1015 (readMiscRegNoEffect(MISCREG_FPSCR) & 1016 ~(uint32_t)fpscrMask); 1017 misc_reg = MISCREG_FPSCR; 1018 } 1019 break; 1020 case MISCREG_CPSR_Q: 1021 { 1022 assert(!(newVal & ~CpsrMaskQ)); 1023 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 1024 misc_reg = MISCREG_CPSR; 1025 } 1026 break; 1027 case MISCREG_FPSCR_QC: 1028 { 1029 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1030 (newVal & FpscrQcMask); 1031 misc_reg = MISCREG_FPSCR; 1032 } 1033 break; 1034 case MISCREG_FPSCR_EXC: 1035 { 1036 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1037 (newVal & FpscrExcMask); 1038 misc_reg = MISCREG_FPSCR; 1039 } 1040 break; 1041 case MISCREG_FPEXC: 1042 { 1043 // vfpv3 architecture, section B.6.1 of DDI04068 1044 // bit 29 - valid only if fpexc[31] is 0 1045 const uint32_t fpexcMask = 0x60000000; 1046 newVal = (newVal & fpexcMask) | 1047 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1048 } 1049 break; 1050 case MISCREG_HCR: 1051 { 1052 if (!haveVirtualization) 1053 return; 1054 } 1055 break; 1056 case MISCREG_IFSR: 1057 { 1058 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1059 const uint32_t ifsrMask = 1060 mask(31, 13) | mask(11, 11) | mask(8, 6); 1061 newVal = newVal & ~ifsrMask; 1062 } 1063 break; 1064 case MISCREG_DFSR: 1065 { 1066 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1067 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1068 newVal = newVal & ~dfsrMask; 1069 } 1070 break; 1071 case MISCREG_AMAIR0: 1072 case MISCREG_AMAIR1: 1073 { 1074 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1075 // Valid only with LPAE 1076 if (!haveLPAE) 1077 return; 1078 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1079 } 1080 break; 1081 case MISCREG_SCR: 1082 tc->getITBPtr()->invalidateMiscReg(); 1083 tc->getDTBPtr()->invalidateMiscReg(); 1084 break; 1085 case MISCREG_SCTLR: 1086 { 1087 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1088 MiscRegIndex sctlr_idx; 1089 scr = readMiscRegNoEffect(MISCREG_SCR); 1090 if (haveSecurity && !scr.ns) { 1091 sctlr_idx = MISCREG_SCTLR_S; 1092 } else { 1093 sctlr_idx = MISCREG_SCTLR_NS; 1094 // The FI field (bit 21) is common between S/NS versions 1095 // of the register, we store this in the secure copy of 1096 // the reg 1097 miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21); 1098 miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21); 1099 } 1100 SCTLR sctlr = miscRegs[sctlr_idx]; 1101 SCTLR new_sctlr = newVal; 1102 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1103 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1104 tc->getITBPtr()->invalidateMiscReg(); 1105 tc->getDTBPtr()->invalidateMiscReg(); 1106 1107 if (new_sctlr.c) 1108 updateBootUncacheable(sctlr_idx, tc); 1109 return; 1110 } 1111 case MISCREG_MIDR: 1112 case MISCREG_ID_PFR0: 1113 case MISCREG_ID_PFR1: 1114 case MISCREG_ID_DFR0: 1115 case MISCREG_ID_MMFR0: 1116 case MISCREG_ID_MMFR1: 1117 case MISCREG_ID_MMFR2: 1118 case MISCREG_ID_MMFR3: 1119 case MISCREG_ID_ISAR0: 1120 case MISCREG_ID_ISAR1: 1121 case MISCREG_ID_ISAR2: 1122 case MISCREG_ID_ISAR3: 1123 case MISCREG_ID_ISAR4: 1124 case MISCREG_ID_ISAR5: 1125 1126 case MISCREG_MPIDR: 1127 case MISCREG_FPSID: 1128 case MISCREG_TLBTR: 1129 case MISCREG_MVFR0: 1130 case MISCREG_MVFR1: 1131 1132 case MISCREG_ID_AA64AFR0_EL1: 1133 case MISCREG_ID_AA64AFR1_EL1: 1134 case MISCREG_ID_AA64DFR0_EL1: 1135 case MISCREG_ID_AA64DFR1_EL1: 1136 case MISCREG_ID_AA64ISAR0_EL1: 1137 case MISCREG_ID_AA64ISAR1_EL1: 1138 case MISCREG_ID_AA64MMFR0_EL1: 1139 case MISCREG_ID_AA64MMFR1_EL1: 1140 case MISCREG_ID_AA64PFR0_EL1: 1141 case MISCREG_ID_AA64PFR1_EL1: 1142 // ID registers are constants. 1143 return; 1144 1145 // TLBI all entries, EL0&1 inner sharable (ignored) 1146 case MISCREG_TLBIALLIS: 1147 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1148 assert32(tc); 1149 target_el = 1; // el 0 and 1 are handled together 1150 scr = readMiscReg(MISCREG_SCR, tc); 1151 secure_lookup = haveSecurity && !scr.ns; 1152 sys = tc->getSystemPtr(); 1153 for (x = 0; x < sys->numContexts(); x++) { 1154 oc = sys->getThreadContext(x); 1155 assert(oc->getITBPtr() && oc->getDTBPtr()); 1156 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1157 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1158 1159 // If CheckerCPU is connected, need to notify it of a flush 1160 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1161 if (checker) { 1162 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1163 target_el); 1164 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1165 target_el); 1166 } 1167 } 1168 return; 1169 // TLBI all entries, EL0&1, instruction side 1170 case MISCREG_ITLBIALL: 1171 assert32(tc); 1172 target_el = 1; // el 0 and 1 are handled together 1173 scr = readMiscReg(MISCREG_SCR, tc); 1174 secure_lookup = haveSecurity && !scr.ns; 1175 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1176 return; 1177 // TLBI all entries, EL0&1, data side 1178 case MISCREG_DTLBIALL: 1179 assert32(tc); 1180 target_el = 1; // el 0 and 1 are handled together 1181 scr = readMiscReg(MISCREG_SCR, tc); 1182 secure_lookup = haveSecurity && !scr.ns; 1183 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1184 return; 1185 // TLBI based on VA, EL0&1 inner sharable (ignored) 1186 case MISCREG_TLBIMVAIS: 1187 case MISCREG_TLBIMVA: 1188 assert32(tc); 1189 target_el = 1; // el 0 and 1 are handled together 1190 scr = readMiscReg(MISCREG_SCR, tc); 1191 secure_lookup = haveSecurity && !scr.ns; 1192 sys = tc->getSystemPtr(); 1193 for (x = 0; x < sys->numContexts(); x++) { 1194 oc = sys->getThreadContext(x); 1195 assert(oc->getITBPtr() && oc->getDTBPtr()); 1196 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1197 bits(newVal, 7,0), 1198 secure_lookup, target_el); 1199 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1200 bits(newVal, 7,0), 1201 secure_lookup, target_el); 1202 1203 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1204 if (checker) { 1205 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1206 bits(newVal, 7,0), secure_lookup, target_el); 1207 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1208 bits(newVal, 7,0), secure_lookup, target_el); 1209 } 1210 } 1211 return; 1212 // TLBI by ASID, EL0&1, inner sharable 1213 case MISCREG_TLBIASIDIS: 1214 case MISCREG_TLBIASID: 1215 assert32(tc); 1216 target_el = 1; // el 0 and 1 are handled together 1217 scr = readMiscReg(MISCREG_SCR, tc); 1218 secure_lookup = haveSecurity && !scr.ns; 1219 sys = tc->getSystemPtr(); 1220 for (x = 0; x < sys->numContexts(); x++) { 1221 oc = sys->getThreadContext(x); 1222 assert(oc->getITBPtr() && oc->getDTBPtr()); 1223 oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 1224 secure_lookup, target_el); 1225 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1226 secure_lookup, target_el); 1227 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1228 if (checker) { 1229 checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 1230 secure_lookup, target_el); 1231 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1232 secure_lookup, target_el); 1233 } 1234 } 1235 return; 1236 // TLBI by address, EL0&1, inner sharable (ignored) 1237 case MISCREG_TLBIMVAAIS: 1238 case MISCREG_TLBIMVAA: 1239 assert32(tc); 1240 target_el = 1; // el 0 and 1 are handled together 1241 scr = readMiscReg(MISCREG_SCR, tc); 1242 secure_lookup = haveSecurity && !scr.ns; 1243 hyp = 0; 1244 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1245 return; 1246 // TLBI by address, EL2, hypervisor mode 1247 case MISCREG_TLBIMVAH: 1248 case MISCREG_TLBIMVAHIS: 1249 assert32(tc); 1250 target_el = 1; // aarch32, use hyp bit 1251 scr = readMiscReg(MISCREG_SCR, tc); 1252 secure_lookup = haveSecurity && !scr.ns; 1253 hyp = 1; 1254 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1255 return; 1256 // TLBI by address and asid, EL0&1, instruction side only 1257 case MISCREG_ITLBIMVA: 1258 assert32(tc); 1259 target_el = 1; // el 0 and 1 are handled together 1260 scr = readMiscReg(MISCREG_SCR, tc); 1261 secure_lookup = haveSecurity && !scr.ns; 1262 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1263 bits(newVal, 7,0), secure_lookup, target_el); 1264 return; 1265 // TLBI by address and asid, EL0&1, data side only 1266 case MISCREG_DTLBIMVA: 1267 assert32(tc); 1268 target_el = 1; // el 0 and 1 are handled together 1269 scr = readMiscReg(MISCREG_SCR, tc); 1270 secure_lookup = haveSecurity && !scr.ns; 1271 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1272 bits(newVal, 7,0), secure_lookup, target_el); 1273 return; 1274 // TLBI by ASID, EL0&1, instrution side only 1275 case MISCREG_ITLBIASID: 1276 assert32(tc); 1277 target_el = 1; // el 0 and 1 are handled together 1278 scr = readMiscReg(MISCREG_SCR, tc); 1279 secure_lookup = haveSecurity && !scr.ns; 1280 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1281 target_el); 1282 return; 1283 // TLBI by ASID EL0&1 data size only 1284 case MISCREG_DTLBIASID: 1285 assert32(tc); 1286 target_el = 1; // el 0 and 1 are handled together 1287 scr = readMiscReg(MISCREG_SCR, tc); 1288 secure_lookup = haveSecurity && !scr.ns; 1289 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1290 target_el); 1291 return; 1292 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1293 case MISCREG_TLBIALLNSNH: 1294 case MISCREG_TLBIALLNSNHIS: 1295 assert32(tc); 1296 target_el = 1; // el 0 and 1 are handled together 1297 hyp = 0; 1298 tlbiALLN(tc, hyp, target_el); 1299 return; 1300 // TLBI all entries, EL2, hyp, 1301 case MISCREG_TLBIALLH: 1302 case MISCREG_TLBIALLHIS: 1303 assert32(tc); 1304 target_el = 1; // aarch32, use hyp bit 1305 hyp = 1; 1306 tlbiALLN(tc, hyp, target_el); 1307 return; 1308 // AArch64 TLBI: invalidate all entries EL3 1309 case MISCREG_TLBI_ALLE3IS: 1310 case MISCREG_TLBI_ALLE3: 1311 assert64(tc); 1312 target_el = 3; 1313 secure_lookup = true; 1314 tlbiALL(tc, secure_lookup, target_el); 1315 return; 1316 // @todo: uncomment this to enable Virtualization 1317 // case MISCREG_TLBI_ALLE2IS: 1318 // case MISCREG_TLBI_ALLE2: 1319 // TLBI all entries, EL0&1 1320 case MISCREG_TLBI_ALLE1IS: 1321 case MISCREG_TLBI_ALLE1: 1322 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1323 case MISCREG_TLBI_VMALLE1IS: 1324 case MISCREG_TLBI_VMALLE1: 1325 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1326 case MISCREG_TLBI_VMALLS12E1IS: 1327 case MISCREG_TLBI_VMALLS12E1: 1328 // @todo: handle VMID and stage 2 to enable Virtualization 1329 assert64(tc); 1330 target_el = 1; // el 0 and 1 are handled together 1331 scr = readMiscReg(MISCREG_SCR, tc); 1332 secure_lookup = haveSecurity && !scr.ns; 1333 tlbiALL(tc, secure_lookup, target_el); 1334 return; 1335 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1336 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1337 // from the last level of translation table walks 1338 // @todo: handle VMID to enable Virtualization 1339 // TLBI all entries, EL0&1 1340 case MISCREG_TLBI_VAE3IS_Xt: 1341 case MISCREG_TLBI_VAE3_Xt: 1342 // TLBI by VA, EL3 regime stage 1, last level walk 1343 case MISCREG_TLBI_VALE3IS_Xt: 1344 case MISCREG_TLBI_VALE3_Xt: 1345 assert64(tc); 1346 target_el = 3; 1347 asid = 0xbeef; // does not matter, tlbi is global 1348 secure_lookup = true; 1349 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1350 return; 1351 // TLBI by VA, EL2 1352 case MISCREG_TLBI_VAE2IS_Xt: 1353 case MISCREG_TLBI_VAE2_Xt: 1354 // TLBI by VA, EL2, stage1 last level walk 1355 case MISCREG_TLBI_VALE2IS_Xt: 1356 case MISCREG_TLBI_VALE2_Xt: 1357 assert64(tc); 1358 target_el = 2; 1359 asid = 0xbeef; // does not matter, tlbi is global 1360 scr = readMiscReg(MISCREG_SCR, tc); 1361 secure_lookup = haveSecurity && !scr.ns; 1362 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1363 return; 1364 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1365 case MISCREG_TLBI_VAE1IS_Xt: 1366 case MISCREG_TLBI_VAE1_Xt: 1367 case MISCREG_TLBI_VALE1IS_Xt: 1368 case MISCREG_TLBI_VALE1_Xt: 1369 assert64(tc); 1370 asid = bits(newVal, 63, 48); 1371 target_el = 1; // el 0 and 1 are handled together 1372 scr = readMiscReg(MISCREG_SCR, tc); 1373 secure_lookup = haveSecurity && !scr.ns; 1374 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1375 return; 1376 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1377 // @todo: handle VMID to enable Virtualization 1378 case MISCREG_TLBI_ASIDE1IS_Xt: 1379 case MISCREG_TLBI_ASIDE1_Xt: 1380 assert64(tc); 1381 target_el = 1; // el 0 and 1 are handled together 1382 scr = readMiscReg(MISCREG_SCR, tc); 1383 secure_lookup = haveSecurity && !scr.ns; 1384 sys = tc->getSystemPtr(); 1385 for (x = 0; x < sys->numContexts(); x++) { 1386 oc = sys->getThreadContext(x); 1387 assert(oc->getITBPtr() && oc->getDTBPtr()); 1388 asid = bits(newVal, 63, 48); 1389 if (haveLargeAsid64) 1390 asid &= mask(8); 1391 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1392 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1393 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1394 if (checker) { 1395 checker->getITBPtr()->flushAsid(asid, 1396 secure_lookup, target_el); 1397 checker->getDTBPtr()->flushAsid(asid, 1398 secure_lookup, target_el); 1399 } 1400 } 1401 return; 1402 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1403 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1404 // entries from the last level of translation table walks 1405 // @todo: handle VMID to enable Virtualization 1406 case MISCREG_TLBI_VAAE1IS_Xt: 1407 case MISCREG_TLBI_VAAE1_Xt: 1408 case MISCREG_TLBI_VAALE1IS_Xt: 1409 case MISCREG_TLBI_VAALE1_Xt: 1410 assert64(tc); 1411 target_el = 1; // el 0 and 1 are handled together 1412 scr = readMiscReg(MISCREG_SCR, tc); 1413 secure_lookup = haveSecurity && !scr.ns; 1414 sys = tc->getSystemPtr(); 1415 for (x = 0; x < sys->numContexts(); x++) { 1416 // @todo: extra controls on TLBI broadcast? 1417 oc = sys->getThreadContext(x); 1418 assert(oc->getITBPtr() && oc->getDTBPtr()); 1419 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1420 oc->getITBPtr()->flushMva(va, 1421 secure_lookup, false, target_el); 1422 oc->getDTBPtr()->flushMva(va, 1423 secure_lookup, false, target_el); 1424 1425 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1426 if (checker) { 1427 checker->getITBPtr()->flushMva(va, 1428 secure_lookup, false, target_el); 1429 checker->getDTBPtr()->flushMva(va, 1430 secure_lookup, false, target_el); 1431 } 1432 } 1433 return; 1434 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1435 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1436 case MISCREG_TLBI_IPAS2LE1_Xt: 1437 case MISCREG_TLBI_IPAS2E1IS_Xt: 1438 case MISCREG_TLBI_IPAS2E1_Xt: 1439 assert64(tc); 1440 // @todo: implement these as part of Virtualization 1441 warn("Not doing anything for write of miscreg ITLB_IPAS2\n"); 1442 return; 1443 case MISCREG_ACTLR: 1444 warn("Not doing anything for write of miscreg ACTLR\n"); 1445 break; 1446 1447 case MISCREG_PMXEVTYPER_PMCCFILTR: 1448 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1449 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1450 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1451 pmu->setMiscReg(misc_reg, newVal); 1452 break; 1453 1454 1455 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1456 { 1457 HSTR hstrMask = 0; 1458 hstrMask.tjdbx = 1; 1459 newVal &= ~((uint32_t) hstrMask); 1460 break; 1461 } 1462 case MISCREG_HCPTR: 1463 { 1464 // If a CP bit in NSACR is 0 then the corresponding bit in 1465 // HCPTR is RAO/WI. Same applies to NSASEDIS 1466 secure_lookup = haveSecurity && 1467 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1468 readMiscRegNoEffect(MISCREG_CPSR)); 1469 if (!secure_lookup) { 1470 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1471 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1472 newVal = (newVal & ~mask) | (oldValue & mask); 1473 } 1474 break; 1475 } 1476 case MISCREG_HDFAR: // alias for secure DFAR 1477 misc_reg = MISCREG_DFAR_S; 1478 break; 1479 case MISCREG_HIFAR: // alias for secure IFAR 1480 misc_reg = MISCREG_IFAR_S; 1481 break; 1482 case MISCREG_ATS1CPR: 1483 case MISCREG_ATS1CPW: 1484 case MISCREG_ATS1CUR: 1485 case MISCREG_ATS1CUW: 1486 case MISCREG_ATS12NSOPR: 1487 case MISCREG_ATS12NSOPW: 1488 case MISCREG_ATS12NSOUR: 1489 case MISCREG_ATS12NSOUW: 1490 case MISCREG_ATS1HR: 1491 case MISCREG_ATS1HW: 1492 { 1493 RequestPtr req = new Request; 1494 unsigned flags = 0; 1495 BaseTLB::Mode mode = BaseTLB::Read; 1496 TLB::ArmTranslationType tranType = TLB::NormalTran; 1497 Fault fault; 1498 switch(misc_reg) { 1499 case MISCREG_ATS1CPR: 1500 flags = TLB::MustBeOne; 1501 tranType = TLB::S1CTran; 1502 mode = BaseTLB::Read; 1503 break; 1504 case MISCREG_ATS1CPW: 1505 flags = TLB::MustBeOne; 1506 tranType = TLB::S1CTran; 1507 mode = BaseTLB::Write; 1508 break; 1509 case MISCREG_ATS1CUR: 1510 flags = TLB::MustBeOne | TLB::UserMode; 1511 tranType = TLB::S1CTran; 1512 mode = BaseTLB::Read; 1513 break; 1514 case MISCREG_ATS1CUW: 1515 flags = TLB::MustBeOne | TLB::UserMode; 1516 tranType = TLB::S1CTran; 1517 mode = BaseTLB::Write; 1518 break; 1519 case MISCREG_ATS12NSOPR: 1520 if (!haveSecurity) 1521 panic("Security Extensions required for ATS12NSOPR"); 1522 flags = TLB::MustBeOne; 1523 tranType = TLB::S1S2NsTran; 1524 mode = BaseTLB::Read; 1525 break; 1526 case MISCREG_ATS12NSOPW: 1527 if (!haveSecurity) 1528 panic("Security Extensions required for ATS12NSOPW"); 1529 flags = TLB::MustBeOne; 1530 tranType = TLB::S1S2NsTran; 1531 mode = BaseTLB::Write; 1532 break; 1533 case MISCREG_ATS12NSOUR: 1534 if (!haveSecurity) 1535 panic("Security Extensions required for ATS12NSOUR"); 1536 flags = TLB::MustBeOne | TLB::UserMode; 1537 tranType = TLB::S1S2NsTran; 1538 mode = BaseTLB::Read; 1539 break; 1540 case MISCREG_ATS12NSOUW: 1541 if (!haveSecurity) 1542 panic("Security Extensions required for ATS12NSOUW"); 1543 flags = TLB::MustBeOne | TLB::UserMode; 1544 tranType = TLB::S1S2NsTran; 1545 mode = BaseTLB::Write; 1546 break; 1547 case MISCREG_ATS1HR: // only really useful from secure mode. 1548 flags = TLB::MustBeOne; 1549 tranType = TLB::HypMode; 1550 mode = BaseTLB::Read; 1551 break; 1552 case MISCREG_ATS1HW: 1553 flags = TLB::MustBeOne; 1554 tranType = TLB::HypMode; 1555 mode = BaseTLB::Write; 1556 break; 1557 } 1558 // If we're in timing mode then doing the translation in 1559 // functional mode then we're slightly distorting performance 1560 // results obtained from simulations. The translation should be 1561 // done in the same mode the core is running in. NOTE: This 1562 // can't be an atomic translation because that causes problems 1563 // with unexpected atomic snoop requests. 1564 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1565 req->setVirt(0, val, 1, flags, Request::funcMasterId, 1566 tc->pcState().pc()); 1567 req->setThreadContext(tc->contextId(), tc->threadId()); 1568 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, tranType); 1569 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1570 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1571 1572 MiscReg newVal; 1573 if (fault == NoFault) { 1574 Addr paddr = req->getPaddr(); 1575 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1576 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1577 newVal = (paddr & mask(39, 12)) | 1578 (tc->getDTBPtr()->getAttr()); 1579 } else { 1580 newVal = (paddr & 0xfffff000) | 1581 (tc->getDTBPtr()->getAttr()); 1582 } 1583 DPRINTF(MiscRegs, 1584 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1585 val, newVal); 1586 } else { 1587 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1588 // Set fault bit and FSR 1589 FSR fsr = armFault->getFsr(tc); 1590 1591 newVal = ((fsr >> 9) & 1) << 11; 1592 if (newVal) { 1593 // LPAE - rearange fault status 1594 newVal |= ((fsr >> 0) & 0x3f) << 1; 1595 } else { 1596 // VMSA - rearange fault status 1597 newVal |= ((fsr >> 0) & 0xf) << 1; 1598 newVal |= ((fsr >> 10) & 0x1) << 5; 1599 newVal |= ((fsr >> 12) & 0x1) << 6; 1600 } 1601 newVal |= 0x1; // F bit 1602 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1603 newVal |= armFault->isStage2() ? 0x200 : 0; 1604 DPRINTF(MiscRegs, 1605 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1606 val, fsr, newVal); 1607 } 1608 delete req; 1609 setMiscRegNoEffect(MISCREG_PAR, newVal); 1610 return; 1611 } 1612 case MISCREG_TTBCR: 1613 { 1614 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1615 const uint32_t ones = (uint32_t)(-1); 1616 TTBCR ttbcrMask = 0; 1617 TTBCR ttbcrNew = newVal; 1618 1619 // ARM DDI 0406C.b, ARMv7-32 1620 ttbcrMask.n = ones; // T0SZ 1621 if (haveSecurity) { 1622 ttbcrMask.pd0 = ones; 1623 ttbcrMask.pd1 = ones; 1624 } 1625 ttbcrMask.epd0 = ones; 1626 ttbcrMask.irgn0 = ones; 1627 ttbcrMask.orgn0 = ones; 1628 ttbcrMask.sh0 = ones; 1629 ttbcrMask.ps = ones; // T1SZ 1630 ttbcrMask.a1 = ones; 1631 ttbcrMask.epd1 = ones; 1632 ttbcrMask.irgn1 = ones; 1633 ttbcrMask.orgn1 = ones; 1634 ttbcrMask.sh1 = ones; 1635 if (haveLPAE) 1636 ttbcrMask.eae = ones; 1637 1638 if (haveLPAE && ttbcrNew.eae) { 1639 newVal = newVal & ttbcrMask; 1640 } else { 1641 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1642 } 1643 } 1644 case MISCREG_TTBR0: 1645 case MISCREG_TTBR1: 1646 { 1647 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1648 if (haveLPAE) { 1649 if (ttbcr.eae) { 1650 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1651 // ARMv8 AArch32 bit 63-56 only 1652 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1653 newVal = (newVal & (~ttbrMask)); 1654 } 1655 } 1656 } 1657 case MISCREG_SCTLR_EL1: 1658 { 1659 tc->getITBPtr()->invalidateMiscReg(); 1660 tc->getDTBPtr()->invalidateMiscReg(); 1661 SCTLR new_sctlr = newVal; 1662 setMiscRegNoEffect(misc_reg, newVal); 1663 if (new_sctlr.c) 1664 updateBootUncacheable(misc_reg, tc); 1665 return; 1666 } 1667 case MISCREG_CONTEXTIDR: 1668 case MISCREG_PRRR: 1669 case MISCREG_NMRR: 1670 case MISCREG_MAIR0: 1671 case MISCREG_MAIR1: 1672 case MISCREG_DACR: 1673 case MISCREG_VTTBR: 1674 case MISCREG_SCR_EL3: 1675 case MISCREG_TCR_EL1: 1676 case MISCREG_TCR_EL2: 1677 case MISCREG_TCR_EL3: 1678 case MISCREG_SCTLR_EL2: 1679 case MISCREG_SCTLR_EL3: 1680 case MISCREG_TTBR0_EL1: 1681 case MISCREG_TTBR1_EL1: 1682 case MISCREG_TTBR0_EL2: 1683 case MISCREG_TTBR0_EL3: 1684 tc->getITBPtr()->invalidateMiscReg(); 1685 tc->getDTBPtr()->invalidateMiscReg(); 1686 break; 1687 case MISCREG_NZCV: 1688 { 1689 CPSR cpsr = val; 1690 1691 tc->setCCReg(CCREG_NZ, cpsr.nz); 1692 tc->setCCReg(CCREG_C, cpsr.c); 1693 tc->setCCReg(CCREG_V, cpsr.v); 1694 } 1695 break; 1696 case MISCREG_DAIF: 1697 { 1698 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1699 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1700 newVal = cpsr; 1701 misc_reg = MISCREG_CPSR; 1702 } 1703 break; 1704 case MISCREG_SP_EL0: 1705 tc->setIntReg(INTREG_SP0, newVal); 1706 break; 1707 case MISCREG_SP_EL1: 1708 tc->setIntReg(INTREG_SP1, newVal); 1709 break; 1710 case MISCREG_SP_EL2: 1711 tc->setIntReg(INTREG_SP2, newVal); 1712 break; 1713 case MISCREG_SPSEL: 1714 { 1715 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1716 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1717 newVal = cpsr; 1718 misc_reg = MISCREG_CPSR; 1719 } 1720 break; 1721 case MISCREG_CURRENTEL: 1722 { 1723 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1724 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1725 newVal = cpsr; 1726 misc_reg = MISCREG_CPSR; 1727 } 1728 break; 1729 case MISCREG_AT_S1E1R_Xt: 1730 case MISCREG_AT_S1E1W_Xt: 1731 case MISCREG_AT_S1E0R_Xt: 1732 case MISCREG_AT_S1E0W_Xt: 1733 case MISCREG_AT_S1E2R_Xt: 1734 case MISCREG_AT_S1E2W_Xt: 1735 case MISCREG_AT_S12E1R_Xt: 1736 case MISCREG_AT_S12E1W_Xt: 1737 case MISCREG_AT_S12E0R_Xt: 1738 case MISCREG_AT_S12E0W_Xt: 1739 case MISCREG_AT_S1E3R_Xt: 1740 case MISCREG_AT_S1E3W_Xt: 1741 { 1742 RequestPtr req = new Request; 1743 unsigned flags = 0; 1744 BaseTLB::Mode mode = BaseTLB::Read; 1745 TLB::ArmTranslationType tranType = TLB::NormalTran; 1746 Fault fault; 1747 switch(misc_reg) { 1748 case MISCREG_AT_S1E1R_Xt: 1749 flags = TLB::MustBeOne; 1750 tranType = TLB::S1CTran; 1751 mode = BaseTLB::Read; 1752 break; 1753 case MISCREG_AT_S1E1W_Xt: 1754 flags = TLB::MustBeOne; 1755 tranType = TLB::S1CTran; 1756 mode = BaseTLB::Write; 1757 break; 1758 case MISCREG_AT_S1E0R_Xt: 1759 flags = TLB::MustBeOne | TLB::UserMode; 1760 tranType = TLB::S1CTran; 1761 mode = BaseTLB::Read; 1762 break; 1763 case MISCREG_AT_S1E0W_Xt: 1764 flags = TLB::MustBeOne | TLB::UserMode; 1765 tranType = TLB::S1CTran; 1766 mode = BaseTLB::Write; 1767 break; 1768 case MISCREG_AT_S1E2R_Xt: 1769 flags = TLB::MustBeOne; 1770 tranType = TLB::HypMode; 1771 mode = BaseTLB::Read; 1772 break; 1773 case MISCREG_AT_S1E2W_Xt: 1774 flags = TLB::MustBeOne; 1775 tranType = TLB::HypMode; 1776 mode = BaseTLB::Write; 1777 break; 1778 case MISCREG_AT_S12E0R_Xt: 1779 flags = TLB::MustBeOne | TLB::UserMode; 1780 tranType = TLB::S1S2NsTran; 1781 mode = BaseTLB::Read; 1782 break; 1783 case MISCREG_AT_S12E0W_Xt: 1784 flags = TLB::MustBeOne | TLB::UserMode; 1785 tranType = TLB::S1S2NsTran; 1786 mode = BaseTLB::Write; 1787 break; 1788 case MISCREG_AT_S12E1R_Xt: 1789 flags = TLB::MustBeOne; 1790 tranType = TLB::S1S2NsTran; 1791 mode = BaseTLB::Read; 1792 break; 1793 case MISCREG_AT_S12E1W_Xt: 1794 flags = TLB::MustBeOne; 1795 tranType = TLB::S1S2NsTran; 1796 mode = BaseTLB::Write; 1797 break; 1798 case MISCREG_AT_S1E3R_Xt: 1799 flags = TLB::MustBeOne; 1800 tranType = TLB::HypMode; // There is no TZ mode defined. 1801 mode = BaseTLB::Read; 1802 break; 1803 case MISCREG_AT_S1E3W_Xt: 1804 flags = TLB::MustBeOne; 1805 tranType = TLB::HypMode; // There is no TZ mode defined. 1806 mode = BaseTLB::Write; 1807 break; 1808 } 1809 // If we're in timing mode then doing the translation in 1810 // functional mode then we're slightly distorting performance 1811 // results obtained from simulations. The translation should be 1812 // done in the same mode the core is running in. NOTE: This 1813 // can't be an atomic translation because that causes problems 1814 // with unexpected atomic snoop requests. 1815 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1816 req->setVirt(0, val, 1, flags, Request::funcMasterId, 1817 tc->pcState().pc()); 1818 req->setThreadContext(tc->contextId(), tc->threadId()); 1819 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1820 tranType); 1821 1822 MiscReg newVal; 1823 if (fault == NoFault) { 1824 Addr paddr = req->getPaddr(); 1825 uint64_t attr = tc->getDTBPtr()->getAttr(); 1826 uint64_t attr1 = attr >> 56; 1827 if (!attr1 || attr1 ==0x44) { 1828 attr |= 0x100; 1829 attr &= ~ uint64_t(0x80); 1830 } 1831 newVal = (paddr & mask(47, 12)) | attr; 1832 DPRINTF(MiscRegs, 1833 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1834 val, newVal); 1835 } else { 1836 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1837 // Set fault bit and FSR 1838 FSR fsr = armFault->getFsr(tc); 1839 1840 newVal = ((fsr >> 9) & 1) << 11; 1841 // rearange fault status 1842 newVal |= ((fsr >> 0) & 0x3f) << 1; 1843 newVal |= 0x1; // F bit 1844 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1845 newVal |= armFault->isStage2() ? 0x200 : 0; 1846 DPRINTF(MiscRegs, 1847 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1848 val, fsr, newVal); 1849 } 1850 delete req; 1851 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1852 return; 1853 } 1854 case MISCREG_SPSR_EL3: 1855 case MISCREG_SPSR_EL2: 1856 case MISCREG_SPSR_EL1: 1857 // Force bits 23:21 to 0 1858 newVal = val & ~(0x7 << 21); 1859 break; 1860 case MISCREG_L2CTLR: 1861 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1862 miscRegName[misc_reg], uint32_t(val)); 1863 break; 1864 1865 // Generic Timer registers 1866 case MISCREG_CNTFRQ: 1867 case MISCREG_CNTFRQ_EL0: 1868 getSystemCounter(tc)->setFreq(val); 1869 break; 1870 case MISCREG_CNTP_CVAL: 1871 case MISCREG_CNTP_CVAL_EL0: 1872 getArchTimer(tc, tc->cpuId())->setCompareValue(val); 1873 break; 1874 case MISCREG_CNTP_TVAL: 1875 case MISCREG_CNTP_TVAL_EL0: 1876 getArchTimer(tc, tc->cpuId())->setTimerValue(val); 1877 break; 1878 case MISCREG_CNTP_CTL: 1879 case MISCREG_CNTP_CTL_EL0: 1880 getArchTimer(tc, tc->cpuId())->setControl(val); 1881 break; 1882 // PL1 phys. timer, secure 1883 // AArch64 1884 case MISCREG_CNTPS_CVAL_EL1: 1885 case MISCREG_CNTPS_TVAL_EL1: 1886 case MISCREG_CNTPS_CTL_EL1: 1887 // PL2 phys. timer, non-secure 1888 // AArch32 1889 case MISCREG_CNTHCTL: 1890 case MISCREG_CNTHP_CVAL: 1891 case MISCREG_CNTHP_TVAL: 1892 case MISCREG_CNTHP_CTL: 1893 // AArch64 1894 case MISCREG_CNTHCTL_EL2: 1895 case MISCREG_CNTHP_CVAL_EL2: 1896 case MISCREG_CNTHP_TVAL_EL2: 1897 case MISCREG_CNTHP_CTL_EL2: 1898 // Virtual timer 1899 // AArch32 1900 case MISCREG_CNTV_CVAL: 1901 case MISCREG_CNTV_TVAL: 1902 case MISCREG_CNTV_CTL: 1903 // AArch64 1904 // case MISCREG_CNTV_CVAL_EL2: 1905 // case MISCREG_CNTV_TVAL_EL2: 1906 // case MISCREG_CNTV_CTL_EL2: 1907 break; 1908 } 1909 } 1910 setMiscRegNoEffect(misc_reg, newVal); 1911} 1912 1913void 1914ISA::updateBootUncacheable(int sctlr_idx, ThreadContext *tc) 1915{ 1916 System *sys; 1917 ThreadContext *oc; 1918 1919 // Check if all CPUs are booted with caches enabled 1920 // so we can stop enforcing coherency of some kernel 1921 // structures manually. 1922 sys = tc->getSystemPtr(); 1923 for (int x = 0; x < sys->numContexts(); x++) { 1924 oc = sys->getThreadContext(x); 1925 // @todo: double check this for security 1926 SCTLR other_sctlr = oc->readMiscRegNoEffect(sctlr_idx); 1927 if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 1928 return; 1929 } 1930 1931 for (int x = 0; x < sys->numContexts(); x++) { 1932 oc = sys->getThreadContext(x); 1933 oc->getDTBPtr()->allCpusCaching(); 1934 oc->getITBPtr()->allCpusCaching(); 1935 1936 // If CheckerCPU is connected, need to notify it. 1937 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1938 if (checker) { 1939 checker->getDTBPtr()->allCpusCaching(); 1940 checker->getITBPtr()->allCpusCaching(); 1941 } 1942 } 1943} 1944 1945void 1946ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid, bool secure_lookup, 1947 uint8_t target_el) 1948{ 1949 if (haveLargeAsid64) 1950 asid &= mask(8); 1951 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1952 System *sys = tc->getSystemPtr(); 1953 for (int x = 0; x < sys->numContexts(); x++) { 1954 ThreadContext *oc = sys->getThreadContext(x); 1955 assert(oc->getITBPtr() && oc->getDTBPtr()); 1956 oc->getITBPtr()->flushMvaAsid(va, asid, 1957 secure_lookup, target_el); 1958 oc->getDTBPtr()->flushMvaAsid(va, asid, 1959 secure_lookup, target_el); 1960 1961 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1962 if (checker) { 1963 checker->getITBPtr()->flushMvaAsid( 1964 va, asid, secure_lookup, target_el); 1965 checker->getDTBPtr()->flushMvaAsid( 1966 va, asid, secure_lookup, target_el); 1967 } 1968 } 1969} 1970 1971void 1972ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1973{ 1974 System *sys = tc->getSystemPtr(); 1975 for (int x = 0; x < sys->numContexts(); x++) { 1976 ThreadContext *oc = sys->getThreadContext(x); 1977 assert(oc->getITBPtr() && oc->getDTBPtr()); 1978 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1979 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1980 1981 // If CheckerCPU is connected, need to notify it of a flush 1982 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1983 if (checker) { 1984 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1985 target_el); 1986 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1987 target_el); 1988 } 1989 } 1990} 1991 1992void 1993ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1994{ 1995 System *sys = tc->getSystemPtr(); 1996 for (int x = 0; x < sys->numContexts(); x++) { 1997 ThreadContext *oc = sys->getThreadContext(x); 1998 assert(oc->getITBPtr() && oc->getDTBPtr()); 1999 oc->getITBPtr()->flushAllNs(hyp, target_el); 2000 oc->getDTBPtr()->flushAllNs(hyp, target_el); 2001 2002 CheckerCPU *checker = oc->getCheckerCpuPtr(); 2003 if (checker) { 2004 checker->getITBPtr()->flushAllNs(hyp, target_el); 2005 checker->getDTBPtr()->flushAllNs(hyp, target_el); 2006 } 2007 } 2008} 2009 2010void 2011ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 2012 uint8_t target_el) 2013{ 2014 System *sys = tc->getSystemPtr(); 2015 for (int x = 0; x < sys->numContexts(); x++) { 2016 ThreadContext *oc = sys->getThreadContext(x); 2017 assert(oc->getITBPtr() && oc->getDTBPtr()); 2018 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 2019 secure_lookup, hyp, target_el); 2020 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 2021 secure_lookup, hyp, target_el); 2022 2023 CheckerCPU *checker = oc->getCheckerCpuPtr(); 2024 if (checker) { 2025 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 2026 secure_lookup, hyp, target_el); 2027 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 2028 secure_lookup, hyp, target_el); 2029 } 2030 } 2031} 2032 2033::GenericTimer::SystemCounter * 2034ISA::getSystemCounter(ThreadContext *tc) 2035{ 2036 ::GenericTimer::SystemCounter *cnt = ((ArmSystem *) tc->getSystemPtr())-> 2037 getSystemCounter(); 2038 if (cnt == NULL) { 2039 panic("System counter not available\n"); 2040 } 2041 return cnt; 2042} 2043 2044::GenericTimer::ArchTimer * 2045ISA::getArchTimer(ThreadContext *tc, int cpu_id) 2046{ 2047 ::GenericTimer::ArchTimer *timer = ((ArmSystem *) tc->getSystemPtr())-> 2048 getArchTimer(cpu_id); 2049 if (timer == NULL) { 2050 panic("Architected timer not available\n"); 2051 } 2052 return timer; 2053} 2054 2055} 2056 2057ArmISA::ISA * 2058ArmISAParams::create() 2059{ 2060 return new ArmISA::ISA(this); 2061} 2062