isa.cc revision 9377
12221SN/A/* 22221SN/A * Copyright (c) 2010-2012 ARM Limited 32221SN/A * All rights reserved 42221SN/A * 52221SN/A * The license below extends only to copyright in the software and shall 62221SN/A * not be construed as granting a license to any other intellectual 72221SN/A * property including but not limited to intellectual property relating 82221SN/A * to a hardware implementation of the functionality of the software 92221SN/A * licensed hereunder. You may use the software subject to the license 102221SN/A * terms below provided that you ensure that this notice is replicated 112221SN/A * unmodified and in its entirety in all distributions of the software, 122221SN/A * modified or unmodified, in source code or in binary form. 132221SN/A * 142221SN/A * Redistribution and use in source and binary forms, with or without 152221SN/A * modification, are permitted provided that the following conditions are 162221SN/A * met: redistributions of source code must retain the above copyright 172221SN/A * notice, this list of conditions and the following disclaimer; 182221SN/A * redistributions in binary form must reproduce the above copyright 192221SN/A * notice, this list of conditions and the following disclaimer in the 202221SN/A * documentation and/or other materials provided with the distribution; 212221SN/A * neither the name of the copyright holders nor the names of its 222221SN/A * contributors may be used to endorse or promote products derived from 232221SN/A * this software without specific prior written permission. 242221SN/A * 252221SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262221SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302221SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312221SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 323415Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 333415Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342223SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 353415Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 363578Sgblack@eecs.umich.edu * 373415Sgblack@eecs.umich.edu * Authors: Gabe Black 383415Sgblack@eecs.umich.edu * Ali Saidi 393523Sgblack@eecs.umich.edu */ 403415Sgblack@eecs.umich.edu 412680Sktlim@umich.edu#include "arch/arm/isa.hh" 422800Ssaidi@eecs.umich.edu#include "arch/arm/system.hh" 433523Sgblack@eecs.umich.edu#include "cpu/checker/cpu.hh" 443415Sgblack@eecs.umich.edu#include "debug/Arm.hh" 452800Ssaidi@eecs.umich.edu#include "debug/MiscRegs.hh" 462800Ssaidi@eecs.umich.edu#include "sim/faults.hh" 472221SN/A#include "sim/stat_control.hh" 483415Sgblack@eecs.umich.edu#include "sim/system.hh" 493415Sgblack@eecs.umich.edu 502223SN/Anamespace ArmISA 512221SN/A{ 522221SN/A 533573Sgblack@eecs.umich.eduvoid 543576Sgblack@eecs.umich.eduISA::clear() 553576Sgblack@eecs.umich.edu{ 562221SN/A SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 573573Sgblack@eecs.umich.edu uint32_t midr = miscRegs[MISCREG_MIDR]; 583576Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 593576Sgblack@eecs.umich.edu CPSR cpsr = 0; 602221SN/A cpsr.mode = MODE_USER; 613573Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 623576Sgblack@eecs.umich.edu updateRegMap(cpsr); 633576Sgblack@eecs.umich.edu 642221SN/A SCTLR sctlr = 0; 653573Sgblack@eecs.umich.edu sctlr.te = (bool)sctlr_rst.te; 663576Sgblack@eecs.umich.edu sctlr.nmfi = (bool)sctlr_rst.nmfi; 673576Sgblack@eecs.umich.edu sctlr.v = (bool)sctlr_rst.v; 682221SN/A sctlr.u = 1; 693573Sgblack@eecs.umich.edu sctlr.xp = 1; 703576Sgblack@eecs.umich.edu sctlr.rao2 = 1; 713576Sgblack@eecs.umich.edu sctlr.rao3 = 1; 722221SN/A sctlr.rao4 = 1; 733573Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 743576Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 753576Sgblack@eecs.umich.edu 762221SN/A // Preserve MIDR across reset 773573Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR] = midr; 783576Sgblack@eecs.umich.edu 793576Sgblack@eecs.umich.edu /* Start with an event in the mailbox */ 803576Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 813576Sgblack@eecs.umich.edu 823576Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs. 833576Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 843576Sgblack@eecs.umich.edu 852221SN/A MVFR0 mvfr0 = 0; 863573Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 873576Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 883576Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 892221SN/A mvfr0.vfpExceptionTrapping = 0; 903573Sgblack@eecs.umich.edu mvfr0.divide = 1; 913576Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 923576Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 932221SN/A mvfr0.roundingModes = 1; 943573Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 953576Sgblack@eecs.umich.edu 963576Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 973576Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 983576Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 993576Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1003576Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1013576Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1023576Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1033576Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1043576Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1053576Sgblack@eecs.umich.edu 1063576Sgblack@eecs.umich.edu // Reset values of PRRR and NMRR are implementation dependent 1072221SN/A 1083573Sgblack@eecs.umich.edu miscRegs[MISCREG_PRRR] = 1093576Sgblack@eecs.umich.edu (1 << 19) | // 19 1103576Sgblack@eecs.umich.edu (0 << 18) | // 18 1112221SN/A (0 << 17) | // 17 1123573Sgblack@eecs.umich.edu (1 << 16) | // 16 1133576Sgblack@eecs.umich.edu (2 << 14) | // 15:14 1143576Sgblack@eecs.umich.edu (0 << 12) | // 13:12 1152221SN/A (2 << 10) | // 11:10 1163573Sgblack@eecs.umich.edu (2 << 8) | // 9:8 1173576Sgblack@eecs.umich.edu (2 << 6) | // 7:6 1183576Sgblack@eecs.umich.edu (2 << 4) | // 5:4 1192221SN/A (1 << 2) | // 3:2 1203573Sgblack@eecs.umich.edu 0; // 1:0 1213576Sgblack@eecs.umich.edu miscRegs[MISCREG_NMRR] = 1223576Sgblack@eecs.umich.edu (1 << 30) | // 31:30 1232221SN/A (0 << 26) | // 27:26 1243573Sgblack@eecs.umich.edu (0 << 24) | // 25:24 1253576Sgblack@eecs.umich.edu (3 << 22) | // 23:22 1263576Sgblack@eecs.umich.edu (2 << 20) | // 21:20 1272221SN/A (0 << 18) | // 19:18 1283573Sgblack@eecs.umich.edu (0 << 16) | // 17:16 1293576Sgblack@eecs.umich.edu (1 << 14) | // 15:14 1303576Sgblack@eecs.umich.edu (0 << 12) | // 13:12 1312223SN/A (2 << 10) | // 11:10 1323573Sgblack@eecs.umich.edu (0 << 8) | // 9:8 1333576Sgblack@eecs.umich.edu (3 << 6) | // 7:6 1343576Sgblack@eecs.umich.edu (2 << 4) | // 5:4 1352223SN/A (0 << 2) | // 3:2 1363573Sgblack@eecs.umich.edu 0; // 1:0 1373576Sgblack@eecs.umich.edu 1383576Sgblack@eecs.umich.edu miscRegs[MISCREG_CPACR] = 0; 1392223SN/A miscRegs[MISCREG_FPSID] = 0x410430A0; 1403573Sgblack@eecs.umich.edu 1413576Sgblack@eecs.umich.edu // See section B4.1.84 of ARM ARM 1423576Sgblack@eecs.umich.edu // All values are latest for ARMv7-A profile 1432223SN/A miscRegs[MISCREG_ID_ISAR0] = 0x02101111; 1443573Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 1453576Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 1463576Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 1473576Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 1483576Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 1493576Sgblack@eecs.umich.edu 1503576Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1513576Sgblack@eecs.umich.edu} 1522223SN/A 1533573Sgblack@eecs.umich.eduMiscReg 1543576Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int misc_reg) 1553576Sgblack@eecs.umich.edu{ 1562223SN/A assert(misc_reg < NumMiscRegs); 1573573Sgblack@eecs.umich.edu 1583576Sgblack@eecs.umich.edu int flat_idx; 1593576Sgblack@eecs.umich.edu if (misc_reg == MISCREG_SPSR) 1602223SN/A flat_idx = flattenMiscIndex(misc_reg); 1613573Sgblack@eecs.umich.edu else 1623576Sgblack@eecs.umich.edu flat_idx = misc_reg; 1633576Sgblack@eecs.umich.edu MiscReg val = miscRegs[flat_idx]; 1642223SN/A 1653573Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1663576Sgblack@eecs.umich.edu misc_reg, flat_idx, val); 1673576Sgblack@eecs.umich.edu return val; 1682223SN/A} 1693573Sgblack@eecs.umich.edu 1703576Sgblack@eecs.umich.edu 1713576Sgblack@eecs.umich.eduMiscReg 1722223SN/AISA::readMiscReg(int misc_reg, ThreadContext *tc) 1733573Sgblack@eecs.umich.edu{ 1743576Sgblack@eecs.umich.edu ArmSystem *arm_sys; 1753576Sgblack@eecs.umich.edu 1762223SN/A if (misc_reg == MISCREG_CPSR) { 1773573Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[misc_reg]; 1783576Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 1793576Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 1802223SN/A cpsr.t = pc.thumb() ? 1 : 0; 1813573Sgblack@eecs.umich.edu return cpsr; 1823576Sgblack@eecs.umich.edu } 1833576Sgblack@eecs.umich.edu if (misc_reg >= MISCREG_CP15_UNIMP_START) 1842223SN/A panic("Unimplemented CP15 register %s read.\n", 1853573Sgblack@eecs.umich.edu miscRegName[misc_reg]); 1863576Sgblack@eecs.umich.edu 1873576Sgblack@eecs.umich.edu switch (misc_reg) { 1882223SN/A case MISCREG_MPIDR: 1893573Sgblack@eecs.umich.edu arm_sys = dynamic_cast<ArmSystem*>(tc->getSystemPtr()); 1903576Sgblack@eecs.umich.edu assert(arm_sys); 1913576Sgblack@eecs.umich.edu 1922223SN/A if (arm_sys->multiProc) { 1933576Sgblack@eecs.umich.edu return 0x80000000 | // multiprocessor extensions available 1943576Sgblack@eecs.umich.edu tc->cpuId(); 1953576Sgblack@eecs.umich.edu } else { 1963576Sgblack@eecs.umich.edu return 0x80000000 | // multiprocessor extensions available 1972527SN/A 0x40000000 | // in up system 1983573Sgblack@eecs.umich.edu tc->cpuId(); 1993576Sgblack@eecs.umich.edu } 2003576Sgblack@eecs.umich.edu break; 2012223SN/A case MISCREG_ID_MMFR0: 2023573Sgblack@eecs.umich.edu return 0x03; // VMSAv7 support 2033576Sgblack@eecs.umich.edu case MISCREG_ID_MMFR2: 2043576Sgblack@eecs.umich.edu return 0x01230000; // no HW access | WFI stalling | ISB and DSB 2052223SN/A // | all TLB maintenance | no Harvard 2063573Sgblack@eecs.umich.edu case MISCREG_ID_MMFR3: 2073576Sgblack@eecs.umich.edu return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 2083576Sgblack@eecs.umich.edu // BP Maint | Cache Maint Set/way | Cache Maint MVA 2092223SN/A case MISCREG_CLIDR: 2103573Sgblack@eecs.umich.edu warn_once("The clidr register always reports 0 caches.\n"); 2113576Sgblack@eecs.umich.edu warn_once("clidr LoUIS field of 0b001 to match current " 2123576Sgblack@eecs.umich.edu "ARM implementations.\n"); 2132223SN/A return 0x00200000; 2143573Sgblack@eecs.umich.edu case MISCREG_CCSIDR: 2153576Sgblack@eecs.umich.edu warn_once("The ccsidr register isn't implemented and " 2163576Sgblack@eecs.umich.edu "always reads as 0.\n"); 2172223SN/A break; 2183573Sgblack@eecs.umich.edu case MISCREG_ID_PFR0: 2193576Sgblack@eecs.umich.edu warn("Returning thumbEE disabled for now since we don't support CP14" 2203576Sgblack@eecs.umich.edu "config registers and jumping to ThumbEE vectors\n"); 2213576Sgblack@eecs.umich.edu return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 2223576Sgblack@eecs.umich.edu case MISCREG_ID_PFR1: 2233576Sgblack@eecs.umich.edu return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4 2243576Sgblack@eecs.umich.edu case MISCREG_CTR: 2253576Sgblack@eecs.umich.edu { 2263576Sgblack@eecs.umich.edu //all caches have the same line size in gem5 2273576Sgblack@eecs.umich.edu //4 byte words in ARM 2283576Sgblack@eecs.umich.edu unsigned lineSizeWords = 2293576Sgblack@eecs.umich.edu tc->getCpuPtr()->getInstPort().peerBlockSize() / 4; 2303576Sgblack@eecs.umich.edu unsigned log2LineSizeWords = 0; 2313576Sgblack@eecs.umich.edu 2323576Sgblack@eecs.umich.edu while (lineSizeWords >>= 1) { 2333576Sgblack@eecs.umich.edu ++log2LineSizeWords; 2343576Sgblack@eecs.umich.edu } 2353576Sgblack@eecs.umich.edu 2363576Sgblack@eecs.umich.edu CTR ctr = 0; 2373576Sgblack@eecs.umich.edu //log2 of minimun i-cache line size (words) 2383576Sgblack@eecs.umich.edu ctr.iCacheLineSize = log2LineSizeWords; 2393576Sgblack@eecs.umich.edu //b11 - gem5 uses pipt 2403576Sgblack@eecs.umich.edu ctr.l1IndexPolicy = 0x3; 2413576Sgblack@eecs.umich.edu //log2 of minimum d-cache line size (words) 2423576Sgblack@eecs.umich.edu ctr.dCacheLineSize = log2LineSizeWords; 2433576Sgblack@eecs.umich.edu //log2 of max reservation size (words) 2443576Sgblack@eecs.umich.edu ctr.erg = log2LineSizeWords; 2453576Sgblack@eecs.umich.edu //log2 of max writeback size (words) 2463576Sgblack@eecs.umich.edu ctr.cwg = log2LineSizeWords; 2473576Sgblack@eecs.umich.edu //b100 - gem5 format is ARMv7 2483576Sgblack@eecs.umich.edu ctr.format = 0x4; 2493576Sgblack@eecs.umich.edu 2503576Sgblack@eecs.umich.edu return ctr; 2513576Sgblack@eecs.umich.edu } 2523576Sgblack@eecs.umich.edu case MISCREG_ACTLR: 2533576Sgblack@eecs.umich.edu warn("Not doing anything for miscreg ACTLR\n"); 2543576Sgblack@eecs.umich.edu break; 2553576Sgblack@eecs.umich.edu case MISCREG_PMCR: 2563576Sgblack@eecs.umich.edu case MISCREG_PMCCNTR: 2573576Sgblack@eecs.umich.edu case MISCREG_PMSELR: 2583576Sgblack@eecs.umich.edu warn("Not doing anything for read to miscreg %s\n", 2593576Sgblack@eecs.umich.edu miscRegName[misc_reg]); 2603576Sgblack@eecs.umich.edu break; 2613576Sgblack@eecs.umich.edu case MISCREG_CPSR_Q: 2623576Sgblack@eecs.umich.edu panic("shouldn't be reading this register seperately\n"); 2633576Sgblack@eecs.umich.edu case MISCREG_FPSCR_QC: 2643576Sgblack@eecs.umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 2652223SN/A case MISCREG_FPSCR_EXC: 2662800Ssaidi@eecs.umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 2673573Sgblack@eecs.umich.edu case MISCREG_L2CTLR: 2683576Sgblack@eecs.umich.edu { 2693576Sgblack@eecs.umich.edu // mostly unimplemented, just set NumCPUs field from sim and return 2702800Ssaidi@eecs.umich.edu L2CTLR l2ctlr = 0; 2712800Ssaidi@eecs.umich.edu // b00:1CPU to b11:4CPUs 2723415Sgblack@eecs.umich.edu l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 2733578Sgblack@eecs.umich.edu return l2ctlr; 2743578Sgblack@eecs.umich.edu } 2753415Sgblack@eecs.umich.edu case MISCREG_DBGDIDR: 2763415Sgblack@eecs.umich.edu /* For now just implement the version number. 2773578Sgblack@eecs.umich.edu * Return 0 as we don't support debug architecture yet. 2783415Sgblack@eecs.umich.edu */ 2793578Sgblack@eecs.umich.edu return 0; 2803578Sgblack@eecs.umich.edu case MISCREG_DBGDSCR_INT: 2813578Sgblack@eecs.umich.edu return 0; 2823578Sgblack@eecs.umich.edu } 2833578Sgblack@eecs.umich.edu return readMiscRegNoEffect(misc_reg); 2843578Sgblack@eecs.umich.edu} 2853578Sgblack@eecs.umich.edu 2863595Sgblack@eecs.umich.eduvoid 2873746Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2883746Sgblack@eecs.umich.edu{ 2893746Sgblack@eecs.umich.edu assert(misc_reg < NumMiscRegs); 2903746Sgblack@eecs.umich.edu 2913746Sgblack@eecs.umich.edu int flat_idx; 2923578Sgblack@eecs.umich.edu if (misc_reg == MISCREG_SPSR) 2933578Sgblack@eecs.umich.edu flat_idx = flattenMiscIndex(misc_reg); 2943578Sgblack@eecs.umich.edu else 2953578Sgblack@eecs.umich.edu flat_idx = misc_reg; 2963578Sgblack@eecs.umich.edu miscRegs[flat_idx] = val; 2973578Sgblack@eecs.umich.edu 2983578Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 2993578Sgblack@eecs.umich.edu flat_idx, val); 3003578Sgblack@eecs.umich.edu} 3013578Sgblack@eecs.umich.edu 3023578Sgblack@eecs.umich.eduvoid 3033578Sgblack@eecs.umich.eduISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 3043578Sgblack@eecs.umich.edu{ 3053578Sgblack@eecs.umich.edu 3063578Sgblack@eecs.umich.edu MiscReg newVal = val; 3073578Sgblack@eecs.umich.edu int x; 3083578Sgblack@eecs.umich.edu System *sys; 3093578Sgblack@eecs.umich.edu ThreadContext *oc; 3103578Sgblack@eecs.umich.edu 3113578Sgblack@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 3123578Sgblack@eecs.umich.edu updateRegMap(val); 3133578Sgblack@eecs.umich.edu 3143578Sgblack@eecs.umich.edu 3153578Sgblack@eecs.umich.edu CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 3163578Sgblack@eecs.umich.edu int old_mode = old_cpsr.mode; 3173578Sgblack@eecs.umich.edu CPSR cpsr = val; 3183578Sgblack@eecs.umich.edu if (old_mode != cpsr.mode) { 3193578Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateMiscReg(); 3203578Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateMiscReg(); 3213578Sgblack@eecs.umich.edu } 3223578Sgblack@eecs.umich.edu 3233578Sgblack@eecs.umich.edu DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 3243578Sgblack@eecs.umich.edu miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 3253578Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 3263578Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 3273578Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 3283578Sgblack@eecs.umich.edu 3293578Sgblack@eecs.umich.edu // Follow slightly different semantics if a CheckerCPU object 3303578Sgblack@eecs.umich.edu // is connected 3313578Sgblack@eecs.umich.edu CheckerCPU *checker = tc->getCheckerCpuPtr(); 3323578Sgblack@eecs.umich.edu if (checker) { 3333578Sgblack@eecs.umich.edu tc->pcStateNoRecord(pc); 3343578Sgblack@eecs.umich.edu } else { 3353578Sgblack@eecs.umich.edu tc->pcState(pc); 3363578Sgblack@eecs.umich.edu } 3373578Sgblack@eecs.umich.edu } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 3383578Sgblack@eecs.umich.edu misc_reg < MISCREG_CP15_END) { 3393578Sgblack@eecs.umich.edu panic("Unimplemented CP15 register %s wrote with %#x.\n", 3403578Sgblack@eecs.umich.edu miscRegName[misc_reg], val); 3413578Sgblack@eecs.umich.edu } else { 3423578Sgblack@eecs.umich.edu switch (misc_reg) { 3433578Sgblack@eecs.umich.edu case MISCREG_CPACR: 3443578Sgblack@eecs.umich.edu { 3453578Sgblack@eecs.umich.edu 3463578Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 3473578Sgblack@eecs.umich.edu CPACR cpacrMask = 0; 3483746Sgblack@eecs.umich.edu // Only cp10, cp11, and ase are implemented, nothing else should 3493746Sgblack@eecs.umich.edu // be writable 3503578Sgblack@eecs.umich.edu cpacrMask.cp10 = ones; 3513746Sgblack@eecs.umich.edu cpacrMask.cp11 = ones; 3523746Sgblack@eecs.umich.edu cpacrMask.asedis = ones; 3533746Sgblack@eecs.umich.edu newVal &= cpacrMask; 3543578Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 3553578Sgblack@eecs.umich.edu miscRegName[misc_reg], newVal); 3563578Sgblack@eecs.umich.edu } 3573578Sgblack@eecs.umich.edu break; 3583578Sgblack@eecs.umich.edu case MISCREG_CSSELR: 3593578Sgblack@eecs.umich.edu warn_once("The csselr register isn't implemented.\n"); 3603578Sgblack@eecs.umich.edu return; 3613578Sgblack@eecs.umich.edu case MISCREG_FPSCR: 3623578Sgblack@eecs.umich.edu { 3633578Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 3643578Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 3653578Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 3663578Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 3673578Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 3683578Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 3693578Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 3703578Sgblack@eecs.umich.edu fpscrMask.idc = ones; 3713578Sgblack@eecs.umich.edu fpscrMask.len = ones; 3723578Sgblack@eecs.umich.edu fpscrMask.stride = ones; 3733578Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 3743578Sgblack@eecs.umich.edu fpscrMask.fz = ones; 3753578Sgblack@eecs.umich.edu fpscrMask.dn = ones; 3763578Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 3773578Sgblack@eecs.umich.edu fpscrMask.qc = ones; 3783578Sgblack@eecs.umich.edu fpscrMask.v = ones; 3793578Sgblack@eecs.umich.edu fpscrMask.c = ones; 3803578Sgblack@eecs.umich.edu fpscrMask.z = ones; 3813578Sgblack@eecs.umich.edu fpscrMask.n = ones; 3823578Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3833578Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3843578Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(newVal); 3853578Sgblack@eecs.umich.edu } 3863578Sgblack@eecs.umich.edu break; 3873578Sgblack@eecs.umich.edu case MISCREG_CPSR_Q: 3883578Sgblack@eecs.umich.edu { 3893578Sgblack@eecs.umich.edu assert(!(newVal & ~CpsrMaskQ)); 3903578Sgblack@eecs.umich.edu newVal = miscRegs[MISCREG_CPSR] | newVal; 3913578Sgblack@eecs.umich.edu misc_reg = MISCREG_CPSR; 3923578Sgblack@eecs.umich.edu } 3933578Sgblack@eecs.umich.edu break; 3943578Sgblack@eecs.umich.edu case MISCREG_FPSCR_QC: 3953578Sgblack@eecs.umich.edu { 3963578Sgblack@eecs.umich.edu newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 3973578Sgblack@eecs.umich.edu misc_reg = MISCREG_FPSCR; 3983578Sgblack@eecs.umich.edu } 3993578Sgblack@eecs.umich.edu break; 4003578Sgblack@eecs.umich.edu case MISCREG_FPSCR_EXC: 4013578Sgblack@eecs.umich.edu { 4023578Sgblack@eecs.umich.edu newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 4033578Sgblack@eecs.umich.edu misc_reg = MISCREG_FPSCR; 4043578Sgblack@eecs.umich.edu } 4053578Sgblack@eecs.umich.edu break; 4063415Sgblack@eecs.umich.edu case MISCREG_FPEXC: 4073415Sgblack@eecs.umich.edu { 4083415Sgblack@eecs.umich.edu // vfpv3 architecture, section B.6.1 of DDI04068 4093415Sgblack@eecs.umich.edu // bit 29 - valid only if fpexc[31] is 0 4103415Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 4113415Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 4123415Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 4133415Sgblack@eecs.umich.edu } 4143415Sgblack@eecs.umich.edu break; 4153415Sgblack@eecs.umich.edu case MISCREG_SCTLR: 4163415Sgblack@eecs.umich.edu { 4173415Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 4183415Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 4193415Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 4203415Sgblack@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 4213415Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 4223415Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateMiscReg(); 4233415Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateMiscReg(); 4243415Sgblack@eecs.umich.edu 4253415Sgblack@eecs.umich.edu // Check if all CPUs are booted with caches enabled 4263415Sgblack@eecs.umich.edu // so we can stop enforcing coherency of some kernel 4273415Sgblack@eecs.umich.edu // structures manually. 4283415Sgblack@eecs.umich.edu sys = tc->getSystemPtr(); 4293415Sgblack@eecs.umich.edu for (x = 0; x < sys->numContexts(); x++) { 4303415Sgblack@eecs.umich.edu oc = sys->getThreadContext(x); 4313415Sgblack@eecs.umich.edu SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 4323415Sgblack@eecs.umich.edu if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 4333415Sgblack@eecs.umich.edu return; 4343415Sgblack@eecs.umich.edu } 4353415Sgblack@eecs.umich.edu 4363415Sgblack@eecs.umich.edu for (x = 0; x < sys->numContexts(); x++) { 4373415Sgblack@eecs.umich.edu oc = sys->getThreadContext(x); 4383415Sgblack@eecs.umich.edu oc->getDTBPtr()->allCpusCaching(); 4393578Sgblack@eecs.umich.edu oc->getITBPtr()->allCpusCaching(); 4403578Sgblack@eecs.umich.edu 4413415Sgblack@eecs.umich.edu // If CheckerCPU is connected, need to notify it. 4423578Sgblack@eecs.umich.edu CheckerCPU *checker = oc->getCheckerCpuPtr(); 4433415Sgblack@eecs.umich.edu if (checker) { 4443415Sgblack@eecs.umich.edu checker->getDTBPtr()->allCpusCaching(); 4453415Sgblack@eecs.umich.edu checker->getITBPtr()->allCpusCaching(); 4463415Sgblack@eecs.umich.edu } 4473415Sgblack@eecs.umich.edu } 4483415Sgblack@eecs.umich.edu return; 4493415Sgblack@eecs.umich.edu } 4503415Sgblack@eecs.umich.edu case MISCREG_TLBTR: 4513578Sgblack@eecs.umich.edu case MISCREG_MVFR0: 4523415Sgblack@eecs.umich.edu case MISCREG_MVFR1: 4533415Sgblack@eecs.umich.edu case MISCREG_MPIDR: 4543415Sgblack@eecs.umich.edu case MISCREG_FPSID: 4553415Sgblack@eecs.umich.edu return; 4563415Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 4573415Sgblack@eecs.umich.edu case MISCREG_TLBIALL: 4583415Sgblack@eecs.umich.edu sys = tc->getSystemPtr(); 4593415Sgblack@eecs.umich.edu for (x = 0; x < sys->numContexts(); x++) { 4603415Sgblack@eecs.umich.edu oc = sys->getThreadContext(x); 4613746Sgblack@eecs.umich.edu assert(oc->getITBPtr() && oc->getDTBPtr()); 4623746Sgblack@eecs.umich.edu oc->getITBPtr()->flushAll(); 4633746Sgblack@eecs.umich.edu oc->getDTBPtr()->flushAll(); 4643415Sgblack@eecs.umich.edu 4653415Sgblack@eecs.umich.edu // If CheckerCPU is connected, need to notify it of a flush 4663415Sgblack@eecs.umich.edu CheckerCPU *checker = oc->getCheckerCpuPtr(); 4673415Sgblack@eecs.umich.edu if (checker) { 4683415Sgblack@eecs.umich.edu checker->getITBPtr()->flushAll(); 4693415Sgblack@eecs.umich.edu checker->getDTBPtr()->flushAll(); 4703415Sgblack@eecs.umich.edu } 4713415Sgblack@eecs.umich.edu } 4723415Sgblack@eecs.umich.edu return; 4733415Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 4743578Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 4753415Sgblack@eecs.umich.edu return; 4763415Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 4773415Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 4783415Sgblack@eecs.umich.edu return; 4793415Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 4803415Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 4813415Sgblack@eecs.umich.edu sys = tc->getSystemPtr(); 4823415Sgblack@eecs.umich.edu for (x = 0; x < sys->numContexts(); x++) { 4833415Sgblack@eecs.umich.edu oc = sys->getThreadContext(x); 4843415Sgblack@eecs.umich.edu assert(oc->getITBPtr() && oc->getDTBPtr()); 4853415Sgblack@eecs.umich.edu oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4863415Sgblack@eecs.umich.edu bits(newVal, 7,0)); 4873415Sgblack@eecs.umich.edu oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4883415Sgblack@eecs.umich.edu bits(newVal, 7,0)); 4893415Sgblack@eecs.umich.edu 4903415Sgblack@eecs.umich.edu CheckerCPU *checker = oc->getCheckerCpuPtr(); 4913415Sgblack@eecs.umich.edu if (checker) { 4923415Sgblack@eecs.umich.edu checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4933415Sgblack@eecs.umich.edu bits(newVal, 7,0)); 4943415Sgblack@eecs.umich.edu checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4953420Sgblack@eecs.umich.edu bits(newVal, 7,0)); 4963415Sgblack@eecs.umich.edu } 4973415Sgblack@eecs.umich.edu } 4983415Sgblack@eecs.umich.edu return; 4993415Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 5003415Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 5013415Sgblack@eecs.umich.edu sys = tc->getSystemPtr(); 5023415Sgblack@eecs.umich.edu for (x = 0; x < sys->numContexts(); x++) { 5033595Sgblack@eecs.umich.edu oc = sys->getThreadContext(x); 5043578Sgblack@eecs.umich.edu assert(oc->getITBPtr() && oc->getDTBPtr()); 5053585Sgblack@eecs.umich.edu oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 5063603Ssaidi@eecs.umich.edu oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 5073595Sgblack@eecs.umich.edu CheckerCPU *checker = oc->getCheckerCpuPtr(); 5083578Sgblack@eecs.umich.edu if (checker) { 5093578Sgblack@eecs.umich.edu checker->getITBPtr()->flushAsid(bits(newVal, 7,0)); 5103578Sgblack@eecs.umich.edu checker->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 5113585Sgblack@eecs.umich.edu } 5123578Sgblack@eecs.umich.edu } 5133585Sgblack@eecs.umich.edu return; 5143578Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 5153578Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 5163578Sgblack@eecs.umich.edu sys = tc->getSystemPtr(); 5173578Sgblack@eecs.umich.edu for (x = 0; x < sys->numContexts(); x++) { 5183585Sgblack@eecs.umich.edu oc = sys->getThreadContext(x); 5193578Sgblack@eecs.umich.edu assert(oc->getITBPtr() && oc->getDTBPtr()); 5203585Sgblack@eecs.umich.edu oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 5213578Sgblack@eecs.umich.edu oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 5223578Sgblack@eecs.umich.edu 5233578Sgblack@eecs.umich.edu CheckerCPU *checker = oc->getCheckerCpuPtr(); 5243578Sgblack@eecs.umich.edu if (checker) { 5253578Sgblack@eecs.umich.edu checker->getITBPtr()->flushMva(mbits(newVal, 31,12)); 5263578Sgblack@eecs.umich.edu checker->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 5272221SN/A } 5282221SN/A } 5293573Sgblack@eecs.umich.edu return; 5302221SN/A case MISCREG_ITLBIMVA: 5313825Ssaidi@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5322680Sktlim@umich.edu bits(newVal, 7,0)); 5332223SN/A return; 5342221SN/A case MISCREG_DTLBIMVA: 5353578Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5363578Sgblack@eecs.umich.edu bits(newVal, 7,0)); 5373578Sgblack@eecs.umich.edu return; 5383578Sgblack@eecs.umich.edu case MISCREG_ITLBIASID: 5393578Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 5403578Sgblack@eecs.umich.edu return; 5413578Sgblack@eecs.umich.edu case MISCREG_DTLBIASID: 5423578Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 5433578Sgblack@eecs.umich.edu return; 5443578Sgblack@eecs.umich.edu case MISCREG_ACTLR: 5453746Sgblack@eecs.umich.edu warn("Not doing anything for write of miscreg ACTLR\n"); 5463746Sgblack@eecs.umich.edu break; 5473746Sgblack@eecs.umich.edu case MISCREG_PMCR: 5483578Sgblack@eecs.umich.edu { 5493578Sgblack@eecs.umich.edu // Performance counters not implemented. Instead, interpret 5503746Sgblack@eecs.umich.edu // a reset command to this register to reset the simulator 5513578Sgblack@eecs.umich.edu // statistics. 5523578Sgblack@eecs.umich.edu // PMCR_E | PMCR_P | PMCR_C 5533578Sgblack@eecs.umich.edu const int ResetAndEnableCounters = 0x7; 5543578Sgblack@eecs.umich.edu if (newVal == ResetAndEnableCounters) { 5553578Sgblack@eecs.umich.edu inform("Resetting all simobject stats\n"); 5563595Sgblack@eecs.umich.edu Stats::schedStatEvent(false, true); 5573746Sgblack@eecs.umich.edu break; 5583746Sgblack@eecs.umich.edu } 5593746Sgblack@eecs.umich.edu } 5603578Sgblack@eecs.umich.edu case MISCREG_PMCCNTR: 5613578Sgblack@eecs.umich.edu case MISCREG_PMSELR: 5623578Sgblack@eecs.umich.edu warn("Not doing anything for write to miscreg %s\n", 5633578Sgblack@eecs.umich.edu miscRegName[misc_reg]); 5643825Ssaidi@eecs.umich.edu break; 5653578Sgblack@eecs.umich.edu case MISCREG_V2PCWPR: 5663578Sgblack@eecs.umich.edu case MISCREG_V2PCWPW: 5673578Sgblack@eecs.umich.edu case MISCREG_V2PCWUR: 5683578Sgblack@eecs.umich.edu case MISCREG_V2PCWUW: 5693578Sgblack@eecs.umich.edu case MISCREG_V2POWPR: 5703578Sgblack@eecs.umich.edu case MISCREG_V2POWPW: 5713578Sgblack@eecs.umich.edu case MISCREG_V2POWUR: 5723578Sgblack@eecs.umich.edu case MISCREG_V2POWUW: 5733585Sgblack@eecs.umich.edu { 5743578Sgblack@eecs.umich.edu RequestPtr req = new Request; 5753578Sgblack@eecs.umich.edu unsigned flags; 5763578Sgblack@eecs.umich.edu BaseTLB::Mode mode; 5773578Sgblack@eecs.umich.edu Fault fault; 5783585Sgblack@eecs.umich.edu switch(misc_reg) { 5793578Sgblack@eecs.umich.edu case MISCREG_V2PCWPR: 5803578Sgblack@eecs.umich.edu flags = TLB::MustBeOne; 5813578Sgblack@eecs.umich.edu mode = BaseTLB::Read; 5823578Sgblack@eecs.umich.edu break; 5833585Sgblack@eecs.umich.edu case MISCREG_V2PCWPW: 5843578Sgblack@eecs.umich.edu flags = TLB::MustBeOne; 5853578Sgblack@eecs.umich.edu mode = BaseTLB::Write; 5863578Sgblack@eecs.umich.edu break; 5873578Sgblack@eecs.umich.edu case MISCREG_V2PCWUR: 5883578Sgblack@eecs.umich.edu flags = TLB::MustBeOne | TLB::UserMode; 5893420Sgblack@eecs.umich.edu mode = BaseTLB::Read; 5902221SN/A break; 5913523Sgblack@eecs.umich.edu case MISCREG_V2PCWUW: 5923523Sgblack@eecs.umich.edu flags = TLB::MustBeOne | TLB::UserMode; 5933523Sgblack@eecs.umich.edu mode = BaseTLB::Write; 5943523Sgblack@eecs.umich.edu break; 5953523Sgblack@eecs.umich.edu default: 5963595Sgblack@eecs.umich.edu panic("Security Extensions not implemented!"); 5973595Sgblack@eecs.umich.edu } 5983595Sgblack@eecs.umich.edu warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 5993595Sgblack@eecs.umich.edu req->setVirt(0, val, 1, flags, tc->pcState().pc(), 6003595Sgblack@eecs.umich.edu Request::funcMasterId); 6013746Sgblack@eecs.umich.edu fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 6023746Sgblack@eecs.umich.edu if (fault == NoFault) { 6033595Sgblack@eecs.umich.edu miscRegs[MISCREG_PAR] = 6043595Sgblack@eecs.umich.edu (req->getPaddr() & 0xfffff000) | 6053628Sgblack@eecs.umich.edu (tc->getDTBPtr()->getAttr() ); 6063628Sgblack@eecs.umich.edu DPRINTF(MiscRegs, 6073628Sgblack@eecs.umich.edu "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 6083628Sgblack@eecs.umich.edu val, miscRegs[MISCREG_PAR]); 6093628Sgblack@eecs.umich.edu } 6103628Sgblack@eecs.umich.edu else { 6113628Sgblack@eecs.umich.edu // Set fault bit and FSR 6123628Sgblack@eecs.umich.edu FSR fsr = miscRegs[MISCREG_DFSR]; 6133628Sgblack@eecs.umich.edu miscRegs[MISCREG_PAR] = 6143628Sgblack@eecs.umich.edu (fsr.ext << 6) | 6153595Sgblack@eecs.umich.edu (fsr.fsHigh << 5) | 6163595Sgblack@eecs.umich.edu (fsr.fsLow << 1) | 6173595Sgblack@eecs.umich.edu 0x1; // F bit 6183595Sgblack@eecs.umich.edu } 6193746Sgblack@eecs.umich.edu return; 6203746Sgblack@eecs.umich.edu } 6213746Sgblack@eecs.umich.edu case MISCREG_CONTEXTIDR: 6223746Sgblack@eecs.umich.edu case MISCREG_PRRR: 6233595Sgblack@eecs.umich.edu case MISCREG_NMRR: 6243595Sgblack@eecs.umich.edu case MISCREG_DACR: 6253595Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateMiscReg(); 6263595Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateMiscReg(); 6273595Sgblack@eecs.umich.edu break; 6283595Sgblack@eecs.umich.edu case MISCREG_CPSR_MODE: 6293595Sgblack@eecs.umich.edu // This miscreg is used by copy*Regs to set the CPSR mode 6303595Sgblack@eecs.umich.edu // without updating other CPSR variables. It's used to 6313523Sgblack@eecs.umich.edu // make sure the register map is in such a state that we can 6323595Sgblack@eecs.umich.edu // see all of the registers for the copy. 6333595Sgblack@eecs.umich.edu updateRegMap(val); 6343595Sgblack@eecs.umich.edu return; 6353595Sgblack@eecs.umich.edu case MISCREG_L2CTLR: 6363595Sgblack@eecs.umich.edu warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 6373523Sgblack@eecs.umich.edu miscRegName[misc_reg], uint32_t(val)); 6383523Sgblack@eecs.umich.edu } 6393523Sgblack@eecs.umich.edu } 6403523Sgblack@eecs.umich.edu setMiscRegNoEffect(misc_reg, newVal); 6413523Sgblack@eecs.umich.edu} 6423523Sgblack@eecs.umich.edu 6433523Sgblack@eecs.umich.edu} 6443523Sgblack@eecs.umich.edu