isa.cc revision 8059
12221SN/A/* 22221SN/A * Copyright (c) 2010 ARM Limited 32221SN/A * All rights reserved 42221SN/A * 52221SN/A * The license below extends only to copyright in the software and shall 62221SN/A * not be construed as granting a license to any other intellectual 72221SN/A * property including but not limited to intellectual property relating 82221SN/A * to a hardware implementation of the functionality of the software 92221SN/A * licensed hereunder. You may use the software subject to the license 102221SN/A * terms below provided that you ensure that this notice is replicated 112221SN/A * unmodified and in its entirety in all distributions of the software, 122221SN/A * modified or unmodified, in source code or in binary form. 132221SN/A * 142221SN/A * Redistribution and use in source and binary forms, with or without 152221SN/A * modification, are permitted provided that the following conditions are 162221SN/A * met: redistributions of source code must retain the above copyright 172221SN/A * notice, this list of conditions and the following disclaimer; 182221SN/A * redistributions in binary form must reproduce the above copyright 192221SN/A * notice, this list of conditions and the following disclaimer in the 202221SN/A * documentation and/or other materials provided with the distribution; 212221SN/A * neither the name of the copyright holders nor the names of its 222221SN/A * contributors may be used to endorse or promote products derived from 232221SN/A * this software without specific prior written permission. 242221SN/A * 252221SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262221SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302221SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312221SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 323415Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 333415Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342223SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 353415Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 363578Sgblack@eecs.umich.edu * 373415Sgblack@eecs.umich.edu * Authors: Gabe Black 383415Sgblack@eecs.umich.edu * Ali Saidi 393523Sgblack@eecs.umich.edu */ 403415Sgblack@eecs.umich.edu 412680Sktlim@umich.edu#include "arch/arm/isa.hh" 422800Ssaidi@eecs.umich.edu#include "sim/faults.hh" 433523Sgblack@eecs.umich.edu#include "sim/stat_control.hh" 443415Sgblack@eecs.umich.edu 452800Ssaidi@eecs.umich.edunamespace ArmISA 462800Ssaidi@eecs.umich.edu{ 472221SN/A 483415Sgblack@eecs.umich.eduvoid 493415Sgblack@eecs.umich.eduISA::clear() 502223SN/A{ 512221SN/A SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 522221SN/A 533573Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 543576Sgblack@eecs.umich.edu CPSR cpsr = 0; 553576Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 562221SN/A miscRegs[MISCREG_CPSR] = cpsr; 573573Sgblack@eecs.umich.edu updateRegMap(cpsr); 583576Sgblack@eecs.umich.edu 593576Sgblack@eecs.umich.edu SCTLR sctlr = 0; 602221SN/A sctlr.te = (bool)sctlr_rst.te; 613573Sgblack@eecs.umich.edu sctlr.nmfi = (bool)sctlr_rst.nmfi; 623576Sgblack@eecs.umich.edu sctlr.v = (bool)sctlr_rst.v; 633576Sgblack@eecs.umich.edu sctlr.u = 1; 642221SN/A sctlr.xp = 1; 653573Sgblack@eecs.umich.edu sctlr.rao2 = 1; 663576Sgblack@eecs.umich.edu sctlr.rao3 = 1; 673576Sgblack@eecs.umich.edu sctlr.rao4 = 1; 682221SN/A miscRegs[MISCREG_SCTLR] = sctlr; 693573Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 703576Sgblack@eecs.umich.edu 713576Sgblack@eecs.umich.edu /* Start with an event in the mailbox */ 722221SN/A miscRegs[MISCREG_SEV_MAILBOX] = 1; 733573Sgblack@eecs.umich.edu 743576Sgblack@eecs.umich.edu /* 753576Sgblack@eecs.umich.edu * Implemented = '5' from "M5", 762221SN/A * Variant = 0, 773573Sgblack@eecs.umich.edu */ 783576Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR] = 793576Sgblack@eecs.umich.edu (0x35 << 24) | // Implementor is '5' from "M5" 803576Sgblack@eecs.umich.edu (0 << 20) | // Variant 813576Sgblack@eecs.umich.edu (0xf << 16) | // Architecture from CPUID scheme 823576Sgblack@eecs.umich.edu (0xf00 << 4) | // Primary part number 833576Sgblack@eecs.umich.edu (0 << 0) | // Revision 843576Sgblack@eecs.umich.edu 0; 852221SN/A 863573Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs. 873576Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 883576Sgblack@eecs.umich.edu 892221SN/A MVFR0 mvfr0 = 0; 903573Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 913576Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 923576Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 932221SN/A mvfr0.vfpExceptionTrapping = 0; 943573Sgblack@eecs.umich.edu mvfr0.divide = 1; 953576Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 963576Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 973576Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 983576Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 993576Sgblack@eecs.umich.edu 1003576Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1013576Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1023576Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1033576Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1043576Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1053576Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1063576Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1072221SN/A mvfr1.vfpHalfPrecision = 1; 1083573Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1093576Sgblack@eecs.umich.edu 1103576Sgblack@eecs.umich.edu miscRegs[MISCREG_MPIDR] = 0; 1112221SN/A 1123573Sgblack@eecs.umich.edu // Reset values of PRRR and NMRR are implementation dependent 1133576Sgblack@eecs.umich.edu 1143576Sgblack@eecs.umich.edu miscRegs[MISCREG_PRRR] = 1152221SN/A (1 << 19) | // 19 1163573Sgblack@eecs.umich.edu (0 << 18) | // 18 1173576Sgblack@eecs.umich.edu (0 << 17) | // 17 1183576Sgblack@eecs.umich.edu (1 << 16) | // 16 1192221SN/A (2 << 14) | // 15:14 1203573Sgblack@eecs.umich.edu (0 << 12) | // 13:12 1213576Sgblack@eecs.umich.edu (2 << 10) | // 11:10 1223576Sgblack@eecs.umich.edu (2 << 8) | // 9:8 1232221SN/A (2 << 6) | // 7:6 1243573Sgblack@eecs.umich.edu (2 << 4) | // 5:4 1253576Sgblack@eecs.umich.edu (1 << 2) | // 3:2 1263576Sgblack@eecs.umich.edu 0; // 1:0 1272221SN/A miscRegs[MISCREG_NMRR] = 1283573Sgblack@eecs.umich.edu (1 << 30) | // 31:30 1293576Sgblack@eecs.umich.edu (0 << 26) | // 27:26 1303576Sgblack@eecs.umich.edu (0 << 24) | // 25:24 1312223SN/A (3 << 22) | // 23:22 1323573Sgblack@eecs.umich.edu (2 << 20) | // 21:20 1333576Sgblack@eecs.umich.edu (0 << 18) | // 19:18 1343576Sgblack@eecs.umich.edu (0 << 16) | // 17:16 1352223SN/A (1 << 14) | // 15:14 1363573Sgblack@eecs.umich.edu (0 << 12) | // 13:12 1373576Sgblack@eecs.umich.edu (2 << 10) | // 11:10 1383576Sgblack@eecs.umich.edu (0 << 8) | // 9:8 1392223SN/A (3 << 6) | // 7:6 1403573Sgblack@eecs.umich.edu (2 << 4) | // 5:4 1413576Sgblack@eecs.umich.edu (0 << 2) | // 3:2 1423576Sgblack@eecs.umich.edu 0; // 1:0 1432223SN/A 1443573Sgblack@eecs.umich.edu miscRegs[MISCREG_CPACR] = 0; 1453576Sgblack@eecs.umich.edu miscRegs[MISCREG_FPSID] = 0x410430A0; 1463576Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1473576Sgblack@eecs.umich.edu} 1483576Sgblack@eecs.umich.edu 1493576Sgblack@eecs.umich.eduMiscReg 1503576Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int misc_reg) 1513576Sgblack@eecs.umich.edu{ 1522223SN/A assert(misc_reg < NumMiscRegs); 1533573Sgblack@eecs.umich.edu 1543576Sgblack@eecs.umich.edu int flat_idx; 1553576Sgblack@eecs.umich.edu if (misc_reg == MISCREG_SPSR) 1562223SN/A flat_idx = flattenMiscIndex(misc_reg); 1573573Sgblack@eecs.umich.edu else 1583576Sgblack@eecs.umich.edu flat_idx = misc_reg; 1593576Sgblack@eecs.umich.edu MiscReg val = miscRegs[flat_idx]; 1602223SN/A 1613573Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1623576Sgblack@eecs.umich.edu misc_reg, flat_idx, val); 1633576Sgblack@eecs.umich.edu return val; 1642223SN/A} 1653573Sgblack@eecs.umich.edu 1663576Sgblack@eecs.umich.edu 1673576Sgblack@eecs.umich.eduMiscReg 1682223SN/AISA::readMiscReg(int misc_reg, ThreadContext *tc) 1693573Sgblack@eecs.umich.edu{ 1703576Sgblack@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 1713576Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[misc_reg]; 1722223SN/A PCState pc = tc->pcState(); 1733573Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 1743576Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 1753576Sgblack@eecs.umich.edu return cpsr; 1762223SN/A } 1773573Sgblack@eecs.umich.edu if (misc_reg >= MISCREG_CP15_UNIMP_START) 1783576Sgblack@eecs.umich.edu panic("Unimplemented CP15 register %s read.\n", 1793576Sgblack@eecs.umich.edu miscRegName[misc_reg]); 1802223SN/A 1813573Sgblack@eecs.umich.edu switch (misc_reg) { 1823576Sgblack@eecs.umich.edu case MISCREG_CLIDR: 1833576Sgblack@eecs.umich.edu warn_once("The clidr register always reports 0 caches.\n"); 1842223SN/A break; 1853573Sgblack@eecs.umich.edu case MISCREG_CCSIDR: 1863576Sgblack@eecs.umich.edu warn_once("The ccsidr register isn't implemented and " 1873576Sgblack@eecs.umich.edu "always reads as 0.\n"); 1882223SN/A break; 1893573Sgblack@eecs.umich.edu case MISCREG_ID_PFR0: 1903576Sgblack@eecs.umich.edu warn("Returning thumbEE disabled for now since we don't support CP14" 1913576Sgblack@eecs.umich.edu "config registers and jumping to ThumbEE vectors\n"); 1922223SN/A return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 1933576Sgblack@eecs.umich.edu case MISCREG_ID_MMFR0: 1943576Sgblack@eecs.umich.edu return 0x03; //VMSAz7 1953576Sgblack@eecs.umich.edu case MISCREG_CTR: 1963576Sgblack@eecs.umich.edu return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 1972527SN/A case MISCREG_ACTLR: 1983573Sgblack@eecs.umich.edu warn("Not doing anything for miscreg ACTLR\n"); 1993576Sgblack@eecs.umich.edu break; 2003576Sgblack@eecs.umich.edu case MISCREG_PMCR: 2012223SN/A case MISCREG_PMCCNTR: 2023573Sgblack@eecs.umich.edu case MISCREG_PMSELR: 2033576Sgblack@eecs.umich.edu warn("Not doing anyhting for read to miscreg %s\n", 2043576Sgblack@eecs.umich.edu miscRegName[misc_reg]); 2052223SN/A break; 2063573Sgblack@eecs.umich.edu case MISCREG_FPSCR_QC: 2073576Sgblack@eecs.umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 2083576Sgblack@eecs.umich.edu case MISCREG_FPSCR_EXC: 2092223SN/A return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 2103573Sgblack@eecs.umich.edu } 2113576Sgblack@eecs.umich.edu return readMiscRegNoEffect(misc_reg); 2123576Sgblack@eecs.umich.edu} 2132223SN/A 2143573Sgblack@eecs.umich.eduvoid 2153576Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2163576Sgblack@eecs.umich.edu{ 2172223SN/A assert(misc_reg < NumMiscRegs); 2183573Sgblack@eecs.umich.edu 2193576Sgblack@eecs.umich.edu int flat_idx; 2203576Sgblack@eecs.umich.edu if (misc_reg == MISCREG_SPSR) 2213576Sgblack@eecs.umich.edu flat_idx = flattenMiscIndex(misc_reg); 2223576Sgblack@eecs.umich.edu else 2233576Sgblack@eecs.umich.edu flat_idx = misc_reg; 2243576Sgblack@eecs.umich.edu miscRegs[flat_idx] = val; 2253576Sgblack@eecs.umich.edu 2263576Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 2273576Sgblack@eecs.umich.edu flat_idx, val); 2283576Sgblack@eecs.umich.edu} 2293576Sgblack@eecs.umich.edu 2303576Sgblack@eecs.umich.eduvoid 2313576Sgblack@eecs.umich.eduISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2323576Sgblack@eecs.umich.edu{ 2333576Sgblack@eecs.umich.edu 2343576Sgblack@eecs.umich.edu MiscReg newVal = val; 2353576Sgblack@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 2363576Sgblack@eecs.umich.edu updateRegMap(val); 2373576Sgblack@eecs.umich.edu 2383576Sgblack@eecs.umich.edu 2393576Sgblack@eecs.umich.edu CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 2403576Sgblack@eecs.umich.edu int old_mode = old_cpsr.mode; 2413576Sgblack@eecs.umich.edu CPSR cpsr = val; 2423576Sgblack@eecs.umich.edu if (old_mode != cpsr.mode) { 2433576Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateMiscReg(); 2443576Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateMiscReg(); 2453576Sgblack@eecs.umich.edu } 2463576Sgblack@eecs.umich.edu 2473576Sgblack@eecs.umich.edu DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 2483576Sgblack@eecs.umich.edu miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 2493576Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 2503576Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 2513576Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 2523576Sgblack@eecs.umich.edu tc->pcState(pc); 2533576Sgblack@eecs.umich.edu } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 2543576Sgblack@eecs.umich.edu misc_reg < MISCREG_CP15_END) { 2553576Sgblack@eecs.umich.edu panic("Unimplemented CP15 register %s wrote with %#x.\n", 2563576Sgblack@eecs.umich.edu miscRegName[misc_reg], val); 2573576Sgblack@eecs.umich.edu } else { 2583576Sgblack@eecs.umich.edu switch (misc_reg) { 2593576Sgblack@eecs.umich.edu case MISCREG_ITSTATE: 2603576Sgblack@eecs.umich.edu { 2613576Sgblack@eecs.umich.edu ITSTATE itstate = newVal; 2623576Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 2633576Sgblack@eecs.umich.edu cpsr.it1 = itstate.bottom2; 2643576Sgblack@eecs.umich.edu cpsr.it2 = itstate.top6; 2652223SN/A miscRegs[MISCREG_CPSR] = cpsr; 2662800Ssaidi@eecs.umich.edu DPRINTF(MiscRegs, 2673573Sgblack@eecs.umich.edu "Updating ITSTATE -> %#x in CPSR -> %#x.\n", 2683576Sgblack@eecs.umich.edu (uint8_t)itstate, (uint32_t)cpsr); 2693576Sgblack@eecs.umich.edu } 2702800Ssaidi@eecs.umich.edu break; 2712800Ssaidi@eecs.umich.edu case MISCREG_CPACR: 2723415Sgblack@eecs.umich.edu { 2733578Sgblack@eecs.umich.edu CPACR newCpacr = 0; 2743578Sgblack@eecs.umich.edu CPACR valCpacr = val; 2753415Sgblack@eecs.umich.edu newCpacr.cp10 = valCpacr.cp10; 2763415Sgblack@eecs.umich.edu newCpacr.cp11 = valCpacr.cp11; 2773578Sgblack@eecs.umich.edu //XXX d32dis isn't implemented. The manual says whether or not 2783415Sgblack@eecs.umich.edu //it works is implementation defined. 2793578Sgblack@eecs.umich.edu newCpacr.asedis = valCpacr.asedis; 2803578Sgblack@eecs.umich.edu newVal = newCpacr; 2813578Sgblack@eecs.umich.edu } 2823578Sgblack@eecs.umich.edu break; 2833578Sgblack@eecs.umich.edu case MISCREG_CSSELR: 2843578Sgblack@eecs.umich.edu warn_once("The csselr register isn't implemented.\n"); 2853578Sgblack@eecs.umich.edu break; 2863595Sgblack@eecs.umich.edu case MISCREG_FPSCR: 2873746Sgblack@eecs.umich.edu { 2883746Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 2893746Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 2903746Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 2913746Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 2923578Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 2933578Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 2943578Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 2953578Sgblack@eecs.umich.edu fpscrMask.idc = ones; 2963578Sgblack@eecs.umich.edu fpscrMask.len = ones; 2973578Sgblack@eecs.umich.edu fpscrMask.stride = ones; 2983578Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 2993578Sgblack@eecs.umich.edu fpscrMask.fz = ones; 3003578Sgblack@eecs.umich.edu fpscrMask.dn = ones; 3013578Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 3023578Sgblack@eecs.umich.edu fpscrMask.qc = ones; 3033578Sgblack@eecs.umich.edu fpscrMask.v = ones; 3043578Sgblack@eecs.umich.edu fpscrMask.c = ones; 3053578Sgblack@eecs.umich.edu fpscrMask.z = ones; 3063578Sgblack@eecs.umich.edu fpscrMask.n = ones; 3073578Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3083578Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3093578Sgblack@eecs.umich.edu } 3103578Sgblack@eecs.umich.edu break; 3113578Sgblack@eecs.umich.edu case MISCREG_FPSCR_QC: 3123578Sgblack@eecs.umich.edu { 3133578Sgblack@eecs.umich.edu newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 3143578Sgblack@eecs.umich.edu misc_reg = MISCREG_FPSCR; 3153578Sgblack@eecs.umich.edu } 3163578Sgblack@eecs.umich.edu break; 3173578Sgblack@eecs.umich.edu case MISCREG_FPSCR_EXC: 3183578Sgblack@eecs.umich.edu { 3193578Sgblack@eecs.umich.edu newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 3203578Sgblack@eecs.umich.edu misc_reg = MISCREG_FPSCR; 3213578Sgblack@eecs.umich.edu } 3223578Sgblack@eecs.umich.edu break; 3233578Sgblack@eecs.umich.edu case MISCREG_FPEXC: 3243578Sgblack@eecs.umich.edu { 3253578Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 3263578Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 3273578Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 3283578Sgblack@eecs.umich.edu } 3293578Sgblack@eecs.umich.edu break; 3303578Sgblack@eecs.umich.edu case MISCREG_SCTLR: 3313578Sgblack@eecs.umich.edu { 3323578Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 3333578Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 3343578Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 3353578Sgblack@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 3363578Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 3373578Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateMiscReg(); 3383578Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateMiscReg(); 3393578Sgblack@eecs.umich.edu return; 3403578Sgblack@eecs.umich.edu } 3413578Sgblack@eecs.umich.edu case MISCREG_TLBTR: 3423578Sgblack@eecs.umich.edu case MISCREG_MVFR0: 3433578Sgblack@eecs.umich.edu case MISCREG_MVFR1: 3443578Sgblack@eecs.umich.edu case MISCREG_MPIDR: 3453578Sgblack@eecs.umich.edu case MISCREG_FPSID: 3463578Sgblack@eecs.umich.edu return; 3473578Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 3483746Sgblack@eecs.umich.edu case MISCREG_TLBIALL: 3493746Sgblack@eecs.umich.edu warn_once("Need to flush all TLBs in MP\n"); 3503578Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 3513746Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 3523746Sgblack@eecs.umich.edu return; 3533746Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 3543578Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 3553578Sgblack@eecs.umich.edu return; 3563578Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 3573578Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 3583578Sgblack@eecs.umich.edu return; 3593578Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 3603578Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 3613578Sgblack@eecs.umich.edu warn_once("Need to flush all TLBs in MP\n"); 3623578Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3633578Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3643578Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3653578Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3663578Sgblack@eecs.umich.edu return; 3673578Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 3683578Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 3693578Sgblack@eecs.umich.edu warn_once("Need to flush all TLBs in MP\n"); 3703578Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 3713578Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 3723578Sgblack@eecs.umich.edu return; 3733578Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 3743578Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 3753578Sgblack@eecs.umich.edu warn_once("Need to flush all TLBs in MP\n"); 3763578Sgblack@eecs.umich.edu tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 3773578Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 3783578Sgblack@eecs.umich.edu return; 3793578Sgblack@eecs.umich.edu case MISCREG_ITLBIMVA: 3803578Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3813578Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3823578Sgblack@eecs.umich.edu return; 3833578Sgblack@eecs.umich.edu case MISCREG_DTLBIMVA: 3843578Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3853578Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3863578Sgblack@eecs.umich.edu return; 3873578Sgblack@eecs.umich.edu case MISCREG_ITLBIASID: 3883578Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 3893578Sgblack@eecs.umich.edu return; 3903578Sgblack@eecs.umich.edu case MISCREG_DTLBIASID: 3913578Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 3923578Sgblack@eecs.umich.edu return; 3933578Sgblack@eecs.umich.edu case MISCREG_ACTLR: 3943578Sgblack@eecs.umich.edu warn("Not doing anything for write of miscreg ACTLR\n"); 3953578Sgblack@eecs.umich.edu break; 3963578Sgblack@eecs.umich.edu case MISCREG_PMCR: 3973578Sgblack@eecs.umich.edu { 3983578Sgblack@eecs.umich.edu // Performance counters not implemented. Instead, interpret 3993578Sgblack@eecs.umich.edu // a reset command to this register to reset the simulator 4003578Sgblack@eecs.umich.edu // statistics. 4013578Sgblack@eecs.umich.edu // PMCR_E | PMCR_P | PMCR_C 4023578Sgblack@eecs.umich.edu const int ResetAndEnableCounters = 0x7; 4033578Sgblack@eecs.umich.edu if (newVal == ResetAndEnableCounters) { 4043578Sgblack@eecs.umich.edu inform("Resetting all simobject stats\n"); 4053578Sgblack@eecs.umich.edu Stats::schedStatEvent(false, true); 4063415Sgblack@eecs.umich.edu break; 4073415Sgblack@eecs.umich.edu } 4083415Sgblack@eecs.umich.edu } 4093415Sgblack@eecs.umich.edu case MISCREG_PMCCNTR: 4103415Sgblack@eecs.umich.edu case MISCREG_PMSELR: 4113415Sgblack@eecs.umich.edu warn("Not doing anything for write to miscreg %s\n", 4123415Sgblack@eecs.umich.edu miscRegName[misc_reg]); 4133415Sgblack@eecs.umich.edu break; 4143415Sgblack@eecs.umich.edu case MISCREG_V2PCWPR: 4153415Sgblack@eecs.umich.edu case MISCREG_V2PCWPW: 4163415Sgblack@eecs.umich.edu case MISCREG_V2PCWUR: 4173415Sgblack@eecs.umich.edu case MISCREG_V2PCWUW: 4183415Sgblack@eecs.umich.edu case MISCREG_V2POWPR: 4193415Sgblack@eecs.umich.edu case MISCREG_V2POWPW: 4203415Sgblack@eecs.umich.edu case MISCREG_V2POWUR: 4213415Sgblack@eecs.umich.edu case MISCREG_V2POWUW: 4223415Sgblack@eecs.umich.edu { 4233415Sgblack@eecs.umich.edu RequestPtr req = new Request; 4243415Sgblack@eecs.umich.edu unsigned flags; 4253415Sgblack@eecs.umich.edu BaseTLB::Mode mode; 4263415Sgblack@eecs.umich.edu Fault fault; 4273415Sgblack@eecs.umich.edu switch(misc_reg) { 4283415Sgblack@eecs.umich.edu case MISCREG_V2PCWPR: 4293415Sgblack@eecs.umich.edu flags = TLB::MustBeOne; 4303415Sgblack@eecs.umich.edu mode = BaseTLB::Read; 4313415Sgblack@eecs.umich.edu break; 4323415Sgblack@eecs.umich.edu case MISCREG_V2PCWPW: 4333415Sgblack@eecs.umich.edu flags = TLB::MustBeOne; 4343415Sgblack@eecs.umich.edu mode = BaseTLB::Write; 4353415Sgblack@eecs.umich.edu break; 4363415Sgblack@eecs.umich.edu case MISCREG_V2PCWUR: 4373415Sgblack@eecs.umich.edu flags = TLB::MustBeOne | TLB::UserMode; 4383415Sgblack@eecs.umich.edu mode = BaseTLB::Read; 4393578Sgblack@eecs.umich.edu break; 4403578Sgblack@eecs.umich.edu case MISCREG_V2PCWUW: 4413415Sgblack@eecs.umich.edu flags = TLB::MustBeOne | TLB::UserMode; 4423578Sgblack@eecs.umich.edu mode = BaseTLB::Write; 4433415Sgblack@eecs.umich.edu break; 4443415Sgblack@eecs.umich.edu default: 4453415Sgblack@eecs.umich.edu panic("Security Extensions not implemented!"); 4463415Sgblack@eecs.umich.edu } 4473415Sgblack@eecs.umich.edu req->setVirt(0, val, 1, flags, tc->pcState().pc()); 4483415Sgblack@eecs.umich.edu fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 4493415Sgblack@eecs.umich.edu if (fault == NoFault) { 4503415Sgblack@eecs.umich.edu miscRegs[MISCREG_PAR] = 4513578Sgblack@eecs.umich.edu (req->getPaddr() & 0xfffff000) | 4523415Sgblack@eecs.umich.edu (tc->getDTBPtr()->getAttr() ); 4533415Sgblack@eecs.umich.edu DPRINTF(MiscRegs, 4543415Sgblack@eecs.umich.edu "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 4553415Sgblack@eecs.umich.edu val, miscRegs[MISCREG_PAR]); 4563415Sgblack@eecs.umich.edu } 4573415Sgblack@eecs.umich.edu else { 4583415Sgblack@eecs.umich.edu // Set fault bit and FSR 4593415Sgblack@eecs.umich.edu FSR fsr = miscRegs[MISCREG_DFSR]; 4603415Sgblack@eecs.umich.edu miscRegs[MISCREG_PAR] = 4613746Sgblack@eecs.umich.edu (fsr.ext << 6) | 4623746Sgblack@eecs.umich.edu (fsr.fsHigh << 5) | 4633746Sgblack@eecs.umich.edu (fsr.fsLow << 1) | 4643415Sgblack@eecs.umich.edu 0x1; // F bit 4653415Sgblack@eecs.umich.edu } 4663415Sgblack@eecs.umich.edu return; 4673415Sgblack@eecs.umich.edu } 4683415Sgblack@eecs.umich.edu case MISCREG_CONTEXTIDR: 4693415Sgblack@eecs.umich.edu case MISCREG_PRRR: 4703415Sgblack@eecs.umich.edu case MISCREG_NMRR: 4713415Sgblack@eecs.umich.edu case MISCREG_DACR: 4723415Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateMiscReg(); 4733415Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateMiscReg(); 4743578Sgblack@eecs.umich.edu break; 4753415Sgblack@eecs.umich.edu 4763415Sgblack@eecs.umich.edu } 4773415Sgblack@eecs.umich.edu } 4783415Sgblack@eecs.umich.edu setMiscRegNoEffect(misc_reg, newVal); 4793415Sgblack@eecs.umich.edu} 4803415Sgblack@eecs.umich.edu 4813415Sgblack@eecs.umich.edu} 4823415Sgblack@eecs.umich.edu