isa.cc revision 7588
17405SAli.Saidi@ARM.com/* 27405SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 427405SAli.Saidi@ARM.com 437405SAli.Saidi@ARM.comnamespace ArmISA 447405SAli.Saidi@ARM.com{ 457405SAli.Saidi@ARM.com 467427Sgblack@eecs.umich.eduvoid 477427Sgblack@eecs.umich.eduISA::clear() 487427Sgblack@eecs.umich.edu{ 497427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 507427Sgblack@eecs.umich.edu 517427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 527427Sgblack@eecs.umich.edu CPSR cpsr = 0; 537427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 547427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 557427Sgblack@eecs.umich.edu updateRegMap(cpsr); 567427Sgblack@eecs.umich.edu 577427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 587427Sgblack@eecs.umich.edu sctlr.nmfi = (bool)sctlr_rst.nmfi; 597427Sgblack@eecs.umich.edu sctlr.v = (bool)sctlr_rst.v; 607427Sgblack@eecs.umich.edu sctlr.u = 1; 617427Sgblack@eecs.umich.edu sctlr.xp = 1; 627427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 637427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 647427Sgblack@eecs.umich.edu sctlr.rao4 = 1; 657427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 667427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 677427Sgblack@eecs.umich.edu 687427Sgblack@eecs.umich.edu 697427Sgblack@eecs.umich.edu /* 707427Sgblack@eecs.umich.edu * Technically this should be 0, but we don't support those 717427Sgblack@eecs.umich.edu * settings. 727427Sgblack@eecs.umich.edu */ 737427Sgblack@eecs.umich.edu CPACR cpacr = 0; 747427Sgblack@eecs.umich.edu // Enable CP 10, 11 757427Sgblack@eecs.umich.edu cpacr.cp10 = 0x3; 767427Sgblack@eecs.umich.edu cpacr.cp11 = 0x3; 777427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPACR] = cpacr; 787427Sgblack@eecs.umich.edu 797427Sgblack@eecs.umich.edu /* Start with an event in the mailbox */ 807427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 817427Sgblack@eecs.umich.edu 827427Sgblack@eecs.umich.edu /* 837427Sgblack@eecs.umich.edu * Implemented = '5' from "M5", 847427Sgblack@eecs.umich.edu * Variant = 0, 857427Sgblack@eecs.umich.edu */ 867427Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR] = 877427Sgblack@eecs.umich.edu (0x35 << 24) | //Implementor is '5' from "M5" 887427Sgblack@eecs.umich.edu (0 << 20) | //Variant 897427Sgblack@eecs.umich.edu (0xf << 16) | //Architecture from CPUID scheme 907427Sgblack@eecs.umich.edu (0 << 4) | //Primary part number 917427Sgblack@eecs.umich.edu (0 << 0) | //Revision 927427Sgblack@eecs.umich.edu 0; 937427Sgblack@eecs.umich.edu 947427Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs. 957427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 967427Sgblack@eecs.umich.edu 977427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 987427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 997427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 1007427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 1017427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 1027427Sgblack@eecs.umich.edu mvfr0.divide = 1; 1037427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 1047427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 1057427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 1067427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 1077427Sgblack@eecs.umich.edu 1087427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1097427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1107427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1117427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1127427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1137427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1147427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1157427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1167427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1177427Sgblack@eecs.umich.edu 1187427Sgblack@eecs.umich.edu miscRegs[MISCREG_MPIDR] = 0; 1197427Sgblack@eecs.umich.edu 1207436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1217436Sdam.sunwoo@arm.com 1227436Sdam.sunwoo@arm.com miscRegs[MISCREG_PRRR] = 1237436Sdam.sunwoo@arm.com (1 << 19) | // 19 1247436Sdam.sunwoo@arm.com (0 << 18) | // 18 1257436Sdam.sunwoo@arm.com (0 << 17) | // 17 1267436Sdam.sunwoo@arm.com (1 << 16) | // 16 1277436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1287436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1297436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1307436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1317436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1327436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1337436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1347436Sdam.sunwoo@arm.com 0; // 1:0 1357436Sdam.sunwoo@arm.com miscRegs[MISCREG_NMRR] = 1367436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1377436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1387436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1397436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1407436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1417436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1427436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 1437436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 1447436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1457436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1467436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 1477436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 1487436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1497436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 1507436Sdam.sunwoo@arm.com 0; // 1:0 1517436Sdam.sunwoo@arm.com 1527427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1537427Sgblack@eecs.umich.edu} 1547427Sgblack@eecs.umich.edu 1557405SAli.Saidi@ARM.comMiscReg 1567405SAli.Saidi@ARM.comISA::readMiscRegNoEffect(int misc_reg) 1577405SAli.Saidi@ARM.com{ 1587405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 1597405SAli.Saidi@ARM.com if (misc_reg == MISCREG_SPSR) { 1607405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 1617405SAli.Saidi@ARM.com switch (cpsr.mode) { 1627405SAli.Saidi@ARM.com case MODE_USER: 1637405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR]; 1647405SAli.Saidi@ARM.com case MODE_FIQ: 1657405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR_FIQ]; 1667405SAli.Saidi@ARM.com case MODE_IRQ: 1677405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR_IRQ]; 1687405SAli.Saidi@ARM.com case MODE_SVC: 1697405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR_SVC]; 1707405SAli.Saidi@ARM.com case MODE_MON: 1717405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR_MON]; 1727405SAli.Saidi@ARM.com case MODE_ABORT: 1737405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR_ABT]; 1747405SAli.Saidi@ARM.com case MODE_UNDEFINED: 1757405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR_UND]; 1767405SAli.Saidi@ARM.com default: 1777405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR]; 1787405SAli.Saidi@ARM.com } 1797405SAli.Saidi@ARM.com } 1807405SAli.Saidi@ARM.com return miscRegs[misc_reg]; 1817405SAli.Saidi@ARM.com} 1827405SAli.Saidi@ARM.com 1837405SAli.Saidi@ARM.com 1847405SAli.Saidi@ARM.comMiscReg 1857405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 1867405SAli.Saidi@ARM.com{ 1877405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 1887405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[misc_reg]; 1897405SAli.Saidi@ARM.com Addr pc = tc->readPC(); 1907405SAli.Saidi@ARM.com if (pc & (ULL(1) << PcJBitShift)) 1917405SAli.Saidi@ARM.com cpsr.j = 1; 1927405SAli.Saidi@ARM.com else 1937405SAli.Saidi@ARM.com cpsr.j = 0; 1947405SAli.Saidi@ARM.com if (pc & (ULL(1) << PcTBitShift)) 1957405SAli.Saidi@ARM.com cpsr.t = 1; 1967405SAli.Saidi@ARM.com else 1977405SAli.Saidi@ARM.com cpsr.t = 0; 1987405SAli.Saidi@ARM.com return cpsr; 1997405SAli.Saidi@ARM.com } 2007405SAli.Saidi@ARM.com if (misc_reg >= MISCREG_CP15_UNIMP_START && 2017405SAli.Saidi@ARM.com misc_reg < MISCREG_CP15_END) { 2027405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s read.\n", 2037405SAli.Saidi@ARM.com miscRegName[misc_reg]); 2047405SAli.Saidi@ARM.com } 2057405SAli.Saidi@ARM.com switch (misc_reg) { 2067405SAli.Saidi@ARM.com case MISCREG_CLIDR: 2077405SAli.Saidi@ARM.com warn("The clidr register always reports 0 caches.\n"); 2087405SAli.Saidi@ARM.com break; 2097405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 2107405SAli.Saidi@ARM.com warn("The ccsidr register isn't implemented and " 2117405SAli.Saidi@ARM.com "always reads as 0.\n"); 2127405SAli.Saidi@ARM.com break; 2137405SAli.Saidi@ARM.com case MISCREG_ID_PFR0: 2147588SAli.Saidi@arm.com warn("Returning thumbEE disabled for now since we don't support CP14" 2157588SAli.Saidi@arm.com "config registers and jumping to ThumbEE vectors\n"); 2167588SAli.Saidi@arm.com return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 2177583SAli.Saidi@arm.com case MISCREG_ID_MMFR0: 2187583SAli.Saidi@arm.com return 0x03; //VMSAz7 2197583SAli.Saidi@arm.com case MISCREG_CTR: 2207583SAli.Saidi@arm.com return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 2217583SAli.Saidi@arm.com case MISCREG_ACTLR: 2227583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 2237583SAli.Saidi@arm.com break; 2247583SAli.Saidi@arm.com case MISCREG_PMCR: 2257583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 2267583SAli.Saidi@arm.com case MISCREG_PMSELR: 2277583SAli.Saidi@arm.com warn("Not doing anyhting for read to miscreg %s\n", 2287583SAli.Saidi@arm.com miscRegName[misc_reg]); 2297583SAli.Saidi@arm.com break; 2307583SAli.Saidi@arm.com 2317405SAli.Saidi@ARM.com } 2327405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 2337405SAli.Saidi@ARM.com} 2347405SAli.Saidi@ARM.com 2357405SAli.Saidi@ARM.comvoid 2367405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2377405SAli.Saidi@ARM.com{ 2387405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 2397405SAli.Saidi@ARM.com if (misc_reg == MISCREG_SPSR) { 2407405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 2417405SAli.Saidi@ARM.com switch (cpsr.mode) { 2427405SAli.Saidi@ARM.com case MODE_USER: 2437405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR] = val; 2447405SAli.Saidi@ARM.com return; 2457405SAli.Saidi@ARM.com case MODE_FIQ: 2467405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_FIQ] = val; 2477405SAli.Saidi@ARM.com return; 2487405SAli.Saidi@ARM.com case MODE_IRQ: 2497405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_IRQ] = val; 2507405SAli.Saidi@ARM.com return; 2517405SAli.Saidi@ARM.com case MODE_SVC: 2527405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_SVC] = val; 2537405SAli.Saidi@ARM.com return; 2547405SAli.Saidi@ARM.com case MODE_MON: 2557405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_MON] = val; 2567405SAli.Saidi@ARM.com return; 2577405SAli.Saidi@ARM.com case MODE_ABORT: 2587405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_ABT] = val; 2597405SAli.Saidi@ARM.com return; 2607405SAli.Saidi@ARM.com case MODE_UNDEFINED: 2617405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_UND] = val; 2627405SAli.Saidi@ARM.com return; 2637405SAli.Saidi@ARM.com default: 2647405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR] = val; 2657405SAli.Saidi@ARM.com return; 2667405SAli.Saidi@ARM.com } 2677405SAli.Saidi@ARM.com } 2687405SAli.Saidi@ARM.com miscRegs[misc_reg] = val; 2697405SAli.Saidi@ARM.com} 2707405SAli.Saidi@ARM.com 2717405SAli.Saidi@ARM.comvoid 2727405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2737405SAli.Saidi@ARM.com{ 2747405SAli.Saidi@ARM.com MiscReg newVal = val; 2757405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 2767405SAli.Saidi@ARM.com updateRegMap(val); 2777405SAli.Saidi@ARM.com CPSR cpsr = val; 2787405SAli.Saidi@ARM.com DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n", 2797405SAli.Saidi@ARM.com cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 2807405SAli.Saidi@ARM.com Addr npc = tc->readNextPC() & ~PcModeMask; 2817405SAli.Saidi@ARM.com if (cpsr.j) 2827405SAli.Saidi@ARM.com npc = npc | (ULL(1) << PcJBitShift); 2837405SAli.Saidi@ARM.com if (cpsr.t) 2847405SAli.Saidi@ARM.com npc = npc | (ULL(1) << PcTBitShift); 2857405SAli.Saidi@ARM.com 2867405SAli.Saidi@ARM.com tc->setNextPC(npc); 2877408Sgblack@eecs.umich.edu } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 2887405SAli.Saidi@ARM.com misc_reg < MISCREG_CP15_END) { 2897405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s wrote with %#x.\n", 2907405SAli.Saidi@ARM.com miscRegName[misc_reg], val); 2917408Sgblack@eecs.umich.edu } else { 2927408Sgblack@eecs.umich.edu switch (misc_reg) { 2937408Sgblack@eecs.umich.edu case MISCREG_ITSTATE: 2947408Sgblack@eecs.umich.edu { 2957408Sgblack@eecs.umich.edu ITSTATE itstate = newVal; 2967408Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 2977408Sgblack@eecs.umich.edu cpsr.it1 = itstate.bottom2; 2987408Sgblack@eecs.umich.edu cpsr.it2 = itstate.top6; 2997408Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 3007408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, 3017408Sgblack@eecs.umich.edu "Updating ITSTATE -> %#x in CPSR -> %#x.\n", 3027408Sgblack@eecs.umich.edu (uint8_t)itstate, (uint32_t)cpsr); 3037405SAli.Saidi@ARM.com } 3047408Sgblack@eecs.umich.edu break; 3057408Sgblack@eecs.umich.edu case MISCREG_CPACR: 3067408Sgblack@eecs.umich.edu { 3077408Sgblack@eecs.umich.edu CPACR newCpacr = 0; 3087408Sgblack@eecs.umich.edu CPACR valCpacr = val; 3097408Sgblack@eecs.umich.edu newCpacr.cp10 = valCpacr.cp10; 3107408Sgblack@eecs.umich.edu newCpacr.cp11 = valCpacr.cp11; 3117408Sgblack@eecs.umich.edu if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) { 3127408Sgblack@eecs.umich.edu panic("Disabling coprocessors isn't implemented.\n"); 3137408Sgblack@eecs.umich.edu } 3147408Sgblack@eecs.umich.edu newVal = newCpacr; 3157408Sgblack@eecs.umich.edu } 3167408Sgblack@eecs.umich.edu break; 3177408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 3187408Sgblack@eecs.umich.edu warn("The csselr register isn't implemented.\n"); 3197408Sgblack@eecs.umich.edu break; 3207408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 3217408Sgblack@eecs.umich.edu { 3227408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 3237408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 3247408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 3257408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 3267408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 3277408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 3287408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 3297408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 3307408Sgblack@eecs.umich.edu fpscrMask.len = ones; 3317408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 3327408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 3337408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 3347408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 3357408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 3367408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 3377408Sgblack@eecs.umich.edu fpscrMask.v = ones; 3387408Sgblack@eecs.umich.edu fpscrMask.c = ones; 3397408Sgblack@eecs.umich.edu fpscrMask.z = ones; 3407408Sgblack@eecs.umich.edu fpscrMask.n = ones; 3417408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3427408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3437408Sgblack@eecs.umich.edu } 3447408Sgblack@eecs.umich.edu break; 3457408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 3467408Sgblack@eecs.umich.edu { 3477408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 3487408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 3497408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 3507408Sgblack@eecs.umich.edu } 3517408Sgblack@eecs.umich.edu break; 3527408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 3537408Sgblack@eecs.umich.edu { 3547408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 3557408Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 3567408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 3577408Sgblack@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 3587408Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 3597408Sgblack@eecs.umich.edu return; 3607408Sgblack@eecs.umich.edu } 3617408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 3627408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 3637408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 3647408Sgblack@eecs.umich.edu case MISCREG_MPIDR: 3657408Sgblack@eecs.umich.edu case MISCREG_FPSID: 3667408Sgblack@eecs.umich.edu return; 3677408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 3687408Sgblack@eecs.umich.edu case MISCREG_TLBIALL: 3697408Sgblack@eecs.umich.edu warn("Need to flush all TLBs in MP\n"); 3707408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 3717408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 3727408Sgblack@eecs.umich.edu return; 3737408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 3747408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 3757408Sgblack@eecs.umich.edu return; 3767408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 3777408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 3787408Sgblack@eecs.umich.edu return; 3797408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 3807408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 3817408Sgblack@eecs.umich.edu warn("Need to flush all TLBs in MP\n"); 3827408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3837408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3847408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3857408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3867408Sgblack@eecs.umich.edu return; 3877408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 3887408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 3897408Sgblack@eecs.umich.edu warn("Need to flush all TLBs in MP\n"); 3907408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 3917408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 3927408Sgblack@eecs.umich.edu return; 3937408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 3947408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 3957408Sgblack@eecs.umich.edu warn("Need to flush all TLBs in MP\n"); 3967408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 3977408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 3987408Sgblack@eecs.umich.edu return; 3997408Sgblack@eecs.umich.edu case MISCREG_ITLBIMVA: 4007408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4017408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 4027408Sgblack@eecs.umich.edu return; 4037408Sgblack@eecs.umich.edu case MISCREG_DTLBIMVA: 4047408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4057408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 4067408Sgblack@eecs.umich.edu return; 4077408Sgblack@eecs.umich.edu case MISCREG_ITLBIASID: 4087408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 4097408Sgblack@eecs.umich.edu return; 4107408Sgblack@eecs.umich.edu case MISCREG_DTLBIASID: 4117408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 4127405SAli.Saidi@ARM.com return; 4137583SAli.Saidi@arm.com case MISCREG_ACTLR: 4147583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 4157583SAli.Saidi@arm.com break; 4167583SAli.Saidi@arm.com case MISCREG_PMCR: 4177583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 4187583SAli.Saidi@arm.com case MISCREG_PMSELR: 4197583SAli.Saidi@arm.com warn("Not doing anything for write to miscreg %s\n", 4207583SAli.Saidi@arm.com miscRegName[misc_reg]); 4217583SAli.Saidi@arm.com break; 4227436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 4237436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 4247436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 4257436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 4267436Sdam.sunwoo@arm.com case MISCREG_V2POWPR: 4277436Sdam.sunwoo@arm.com case MISCREG_V2POWPW: 4287436Sdam.sunwoo@arm.com case MISCREG_V2POWUR: 4297436Sdam.sunwoo@arm.com case MISCREG_V2POWUW: 4307436Sdam.sunwoo@arm.com { 4317436Sdam.sunwoo@arm.com RequestPtr req = new Request; 4327436Sdam.sunwoo@arm.com unsigned flags; 4337436Sdam.sunwoo@arm.com BaseTLB::Mode mode; 4347436Sdam.sunwoo@arm.com Fault fault; 4357436Sdam.sunwoo@arm.com switch(misc_reg) { 4367436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 4377436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 4387436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 4397436Sdam.sunwoo@arm.com break; 4407436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 4417436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 4427436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 4437436Sdam.sunwoo@arm.com break; 4447436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 4457436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 4467436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 4477436Sdam.sunwoo@arm.com break; 4487436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 4497436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 4507436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 4517436Sdam.sunwoo@arm.com break; 4527442Ssaidi@eecs.umich.edu default: 4537436Sdam.sunwoo@arm.com panic("Security Extensions not implemented!"); 4547436Sdam.sunwoo@arm.com } 4557436Sdam.sunwoo@arm.com req->setVirt(0, val, 1, flags, tc->readPC()); 4567436Sdam.sunwoo@arm.com fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 4577436Sdam.sunwoo@arm.com if (fault == NoFault) { 4587436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 4597436Sdam.sunwoo@arm.com (req->getPaddr() & 0xfffff000) | 4607436Sdam.sunwoo@arm.com (tc->getDTBPtr()->getAttr() ); 4617436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 4627436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 4637436Sdam.sunwoo@arm.com val, miscRegs[MISCREG_PAR]); 4647436Sdam.sunwoo@arm.com } 4657436Sdam.sunwoo@arm.com else { 4667436Sdam.sunwoo@arm.com // Set fault bit and FSR 4677436Sdam.sunwoo@arm.com FSR fsr = miscRegs[MISCREG_DFSR]; 4687436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 4697436Sdam.sunwoo@arm.com (fsr.ext << 6) | 4707436Sdam.sunwoo@arm.com (fsr.fsHigh << 5) | 4717436Sdam.sunwoo@arm.com (fsr.fsLow << 1) | 4727436Sdam.sunwoo@arm.com 0x1; // F bit 4737436Sdam.sunwoo@arm.com } 4747436Sdam.sunwoo@arm.com return; 4757436Sdam.sunwoo@arm.com } 4767405SAli.Saidi@ARM.com } 4777405SAli.Saidi@ARM.com } 4787405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 4797405SAli.Saidi@ARM.com} 4807405SAli.Saidi@ARM.com 4817405SAli.Saidi@ARM.com} 482