isa.cc revision 7408
110447Snilay@cs.wisc.edu/* 210447Snilay@cs.wisc.edu * Copyright (c) 2010 ARM Limited 310447Snilay@cs.wisc.edu * All rights reserved 410447Snilay@cs.wisc.edu * 510447Snilay@cs.wisc.edu * The license below extends only to copyright in the software and shall 610447Snilay@cs.wisc.edu * not be construed as granting a license to any other intellectual 710447Snilay@cs.wisc.edu * property including but not limited to intellectual property relating 810447Snilay@cs.wisc.edu * to a hardware implementation of the functionality of the software 910447Snilay@cs.wisc.edu * licensed hereunder. You may use the software subject to the license 1010447Snilay@cs.wisc.edu * terms below provided that you ensure that this notice is replicated 1110447Snilay@cs.wisc.edu * unmodified and in its entirety in all distributions of the software, 1210447Snilay@cs.wisc.edu * modified or unmodified, in source code or in binary form. 1310447Snilay@cs.wisc.edu * 1410447Snilay@cs.wisc.edu * Redistribution and use in source and binary forms, with or without 1510447Snilay@cs.wisc.edu * modification, are permitted provided that the following conditions are 1610447Snilay@cs.wisc.edu * met: redistributions of source code must retain the above copyright 1710447Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer; 1810447Snilay@cs.wisc.edu * redistributions in binary form must reproduce the above copyright 1910447Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer in the 2010447Snilay@cs.wisc.edu * documentation and/or other materials provided with the distribution; 2110447Snilay@cs.wisc.edu * neither the name of the copyright holders nor the names of its 2210447Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 2310447Snilay@cs.wisc.edu * this software without specific prior written permission. 2410447Snilay@cs.wisc.edu * 2510447Snilay@cs.wisc.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610447Snilay@cs.wisc.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710447Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810447Snilay@cs.wisc.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910447Snilay@cs.wisc.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010447Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110447Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210447Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310447Snilay@cs.wisc.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410447Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510447Snilay@cs.wisc.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610447Snilay@cs.wisc.edu * 3710447Snilay@cs.wisc.edu * Authors: Gabe Black 3810447Snilay@cs.wisc.edu * Ali Saidi 3910447Snilay@cs.wisc.edu */ 4010447Snilay@cs.wisc.edu 4110447Snilay@cs.wisc.edu#include "arch/arm/isa.hh" 4210447Snilay@cs.wisc.edu 4310447Snilay@cs.wisc.edunamespace ArmISA 4410447Snilay@cs.wisc.edu{ 4510447Snilay@cs.wisc.edu 4610447Snilay@cs.wisc.eduMiscReg 4710447Snilay@cs.wisc.eduISA::readMiscRegNoEffect(int misc_reg) 4810447Snilay@cs.wisc.edu{ 4910447Snilay@cs.wisc.edu assert(misc_reg < NumMiscRegs); 5010447Snilay@cs.wisc.edu if (misc_reg == MISCREG_SPSR) { 5110447Snilay@cs.wisc.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 5210447Snilay@cs.wisc.edu switch (cpsr.mode) { 5310447Snilay@cs.wisc.edu case MODE_USER: 5410447Snilay@cs.wisc.edu return miscRegs[MISCREG_SPSR]; 5510447Snilay@cs.wisc.edu case MODE_FIQ: 5610447Snilay@cs.wisc.edu return miscRegs[MISCREG_SPSR_FIQ]; 5710447Snilay@cs.wisc.edu case MODE_IRQ: 5810447Snilay@cs.wisc.edu return miscRegs[MISCREG_SPSR_IRQ]; 5910447Snilay@cs.wisc.edu case MODE_SVC: 6010447Snilay@cs.wisc.edu return miscRegs[MISCREG_SPSR_SVC]; 6110447Snilay@cs.wisc.edu case MODE_MON: 6210447Snilay@cs.wisc.edu return miscRegs[MISCREG_SPSR_MON]; 6310447Snilay@cs.wisc.edu case MODE_ABORT: 6410447Snilay@cs.wisc.edu return miscRegs[MISCREG_SPSR_ABT]; 6510447Snilay@cs.wisc.edu case MODE_UNDEFINED: 6610447Snilay@cs.wisc.edu return miscRegs[MISCREG_SPSR_UND]; 6710447Snilay@cs.wisc.edu default: 6810447Snilay@cs.wisc.edu return miscRegs[MISCREG_SPSR]; 6910447Snilay@cs.wisc.edu } 7010447Snilay@cs.wisc.edu } 7110447Snilay@cs.wisc.edu return miscRegs[misc_reg]; 7210447Snilay@cs.wisc.edu} 7310447Snilay@cs.wisc.edu 7410447Snilay@cs.wisc.edu 7510447Snilay@cs.wisc.eduMiscReg 7610447Snilay@cs.wisc.eduISA::readMiscReg(int misc_reg, ThreadContext *tc) 7710447Snilay@cs.wisc.edu{ 7810447Snilay@cs.wisc.edu if (misc_reg == MISCREG_CPSR) { 7910447Snilay@cs.wisc.edu CPSR cpsr = miscRegs[misc_reg]; 8010447Snilay@cs.wisc.edu Addr pc = tc->readPC(); 8110447Snilay@cs.wisc.edu if (pc & (ULL(1) << PcJBitShift)) 8210447Snilay@cs.wisc.edu cpsr.j = 1; 8310447Snilay@cs.wisc.edu else 8410447Snilay@cs.wisc.edu cpsr.j = 0; 8510447Snilay@cs.wisc.edu if (pc & (ULL(1) << PcTBitShift)) 8610447Snilay@cs.wisc.edu cpsr.t = 1; 8710447Snilay@cs.wisc.edu else 8810447Snilay@cs.wisc.edu cpsr.t = 0; 8910447Snilay@cs.wisc.edu return cpsr; 9010447Snilay@cs.wisc.edu } 9110447Snilay@cs.wisc.edu if (misc_reg >= MISCREG_CP15_UNIMP_START && 9210447Snilay@cs.wisc.edu misc_reg < MISCREG_CP15_END) { 9310447Snilay@cs.wisc.edu panic("Unimplemented CP15 register %s read.\n", 9410447Snilay@cs.wisc.edu miscRegName[misc_reg]); 9510447Snilay@cs.wisc.edu } 9610447Snilay@cs.wisc.edu switch (misc_reg) { 9710447Snilay@cs.wisc.edu case MISCREG_CLIDR: 9810447Snilay@cs.wisc.edu warn("The clidr register always reports 0 caches.\n"); 9910447Snilay@cs.wisc.edu break; 10010447Snilay@cs.wisc.edu case MISCREG_CCSIDR: 10110447Snilay@cs.wisc.edu warn("The ccsidr register isn't implemented and " 10210447Snilay@cs.wisc.edu "always reads as 0.\n"); 10310447Snilay@cs.wisc.edu break; 10410447Snilay@cs.wisc.edu case MISCREG_ID_PFR0: 10510447Snilay@cs.wisc.edu return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM 10610447Snilay@cs.wisc.edu } 10710447Snilay@cs.wisc.edu return readMiscRegNoEffect(misc_reg); 10810447Snilay@cs.wisc.edu} 10910447Snilay@cs.wisc.edu 11010447Snilay@cs.wisc.eduvoid 11110447Snilay@cs.wisc.eduISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 11210447Snilay@cs.wisc.edu{ 11310447Snilay@cs.wisc.edu assert(misc_reg < NumMiscRegs); 11410447Snilay@cs.wisc.edu if (misc_reg == MISCREG_SPSR) { 11510447Snilay@cs.wisc.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 11610447Snilay@cs.wisc.edu switch (cpsr.mode) { 11710447Snilay@cs.wisc.edu case MODE_USER: 11810447Snilay@cs.wisc.edu miscRegs[MISCREG_SPSR] = val; 11910447Snilay@cs.wisc.edu return; 12010447Snilay@cs.wisc.edu case MODE_FIQ: 12110447Snilay@cs.wisc.edu miscRegs[MISCREG_SPSR_FIQ] = val; 122 return; 123 case MODE_IRQ: 124 miscRegs[MISCREG_SPSR_IRQ] = val; 125 return; 126 case MODE_SVC: 127 miscRegs[MISCREG_SPSR_SVC] = val; 128 return; 129 case MODE_MON: 130 miscRegs[MISCREG_SPSR_MON] = val; 131 return; 132 case MODE_ABORT: 133 miscRegs[MISCREG_SPSR_ABT] = val; 134 return; 135 case MODE_UNDEFINED: 136 miscRegs[MISCREG_SPSR_UND] = val; 137 return; 138 default: 139 miscRegs[MISCREG_SPSR] = val; 140 return; 141 } 142 } 143 miscRegs[misc_reg] = val; 144} 145 146void 147ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 148{ 149 MiscReg newVal = val; 150 if (misc_reg == MISCREG_CPSR) { 151 updateRegMap(val); 152 CPSR cpsr = val; 153 DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n", 154 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 155 Addr npc = tc->readNextPC() & ~PcModeMask; 156 if (cpsr.j) 157 npc = npc | (ULL(1) << PcJBitShift); 158 if (cpsr.t) 159 npc = npc | (ULL(1) << PcTBitShift); 160 161 tc->setNextPC(npc); 162 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 163 misc_reg < MISCREG_CP15_END) { 164 panic("Unimplemented CP15 register %s wrote with %#x.\n", 165 miscRegName[misc_reg], val); 166 } else { 167 switch (misc_reg) { 168 case MISCREG_ITSTATE: 169 { 170 ITSTATE itstate = newVal; 171 CPSR cpsr = miscRegs[MISCREG_CPSR]; 172 cpsr.it1 = itstate.bottom2; 173 cpsr.it2 = itstate.top6; 174 miscRegs[MISCREG_CPSR] = cpsr; 175 DPRINTF(MiscRegs, 176 "Updating ITSTATE -> %#x in CPSR -> %#x.\n", 177 (uint8_t)itstate, (uint32_t)cpsr); 178 } 179 break; 180 case MISCREG_CPACR: 181 { 182 CPACR newCpacr = 0; 183 CPACR valCpacr = val; 184 newCpacr.cp10 = valCpacr.cp10; 185 newCpacr.cp11 = valCpacr.cp11; 186 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) { 187 panic("Disabling coprocessors isn't implemented.\n"); 188 } 189 newVal = newCpacr; 190 } 191 break; 192 case MISCREG_CSSELR: 193 warn("The csselr register isn't implemented.\n"); 194 break; 195 case MISCREG_FPSCR: 196 { 197 const uint32_t ones = (uint32_t)(-1); 198 FPSCR fpscrMask = 0; 199 fpscrMask.ioc = ones; 200 fpscrMask.dzc = ones; 201 fpscrMask.ofc = ones; 202 fpscrMask.ufc = ones; 203 fpscrMask.ixc = ones; 204 fpscrMask.idc = ones; 205 fpscrMask.len = ones; 206 fpscrMask.stride = ones; 207 fpscrMask.rMode = ones; 208 fpscrMask.fz = ones; 209 fpscrMask.dn = ones; 210 fpscrMask.ahp = ones; 211 fpscrMask.qc = ones; 212 fpscrMask.v = ones; 213 fpscrMask.c = ones; 214 fpscrMask.z = ones; 215 fpscrMask.n = ones; 216 newVal = (newVal & (uint32_t)fpscrMask) | 217 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 218 } 219 break; 220 case MISCREG_FPEXC: 221 { 222 const uint32_t fpexcMask = 0x60000000; 223 newVal = (newVal & fpexcMask) | 224 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 225 } 226 break; 227 case MISCREG_SCTLR: 228 { 229 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 230 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 231 SCTLR new_sctlr = newVal; 232 new_sctlr.nmfi = (bool)sctlr.nmfi; 233 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 234 return; 235 } 236 case MISCREG_TLBTR: 237 case MISCREG_MVFR0: 238 case MISCREG_MVFR1: 239 case MISCREG_MPIDR: 240 case MISCREG_FPSID: 241 return; 242 case MISCREG_TLBIALLIS: 243 case MISCREG_TLBIALL: 244 warn("Need to flush all TLBs in MP\n"); 245 tc->getITBPtr()->flushAll(); 246 tc->getDTBPtr()->flushAll(); 247 return; 248 case MISCREG_ITLBIALL: 249 tc->getITBPtr()->flushAll(); 250 return; 251 case MISCREG_DTLBIALL: 252 tc->getDTBPtr()->flushAll(); 253 return; 254 case MISCREG_TLBIMVAIS: 255 case MISCREG_TLBIMVA: 256 warn("Need to flush all TLBs in MP\n"); 257 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 258 bits(newVal, 7,0)); 259 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 260 bits(newVal, 7,0)); 261 return; 262 case MISCREG_TLBIASIDIS: 263 case MISCREG_TLBIASID: 264 warn("Need to flush all TLBs in MP\n"); 265 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 266 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 267 return; 268 case MISCREG_TLBIMVAAIS: 269 case MISCREG_TLBIMVAA: 270 warn("Need to flush all TLBs in MP\n"); 271 tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 272 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 273 return; 274 case MISCREG_ITLBIMVA: 275 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 276 bits(newVal, 7,0)); 277 return; 278 case MISCREG_DTLBIMVA: 279 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 280 bits(newVal, 7,0)); 281 return; 282 case MISCREG_ITLBIASID: 283 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 284 return; 285 case MISCREG_DTLBIASID: 286 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 287 return; 288 } 289 } 290 setMiscRegNoEffect(misc_reg, newVal); 291} 292 293} 294