isa.cc revision 7408
17405SAli.Saidi@ARM.com/* 27405SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 427405SAli.Saidi@ARM.com 437405SAli.Saidi@ARM.comnamespace ArmISA 447405SAli.Saidi@ARM.com{ 457405SAli.Saidi@ARM.com 467405SAli.Saidi@ARM.comMiscReg 477405SAli.Saidi@ARM.comISA::readMiscRegNoEffect(int misc_reg) 487405SAli.Saidi@ARM.com{ 497405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 507405SAli.Saidi@ARM.com if (misc_reg == MISCREG_SPSR) { 517405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 527405SAli.Saidi@ARM.com switch (cpsr.mode) { 537405SAli.Saidi@ARM.com case MODE_USER: 547405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR]; 557405SAli.Saidi@ARM.com case MODE_FIQ: 567405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR_FIQ]; 577405SAli.Saidi@ARM.com case MODE_IRQ: 587405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR_IRQ]; 597405SAli.Saidi@ARM.com case MODE_SVC: 607405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR_SVC]; 617405SAli.Saidi@ARM.com case MODE_MON: 627405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR_MON]; 637405SAli.Saidi@ARM.com case MODE_ABORT: 647405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR_ABT]; 657405SAli.Saidi@ARM.com case MODE_UNDEFINED: 667405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR_UND]; 677405SAli.Saidi@ARM.com default: 687405SAli.Saidi@ARM.com return miscRegs[MISCREG_SPSR]; 697405SAli.Saidi@ARM.com } 707405SAli.Saidi@ARM.com } 717405SAli.Saidi@ARM.com return miscRegs[misc_reg]; 727405SAli.Saidi@ARM.com} 737405SAli.Saidi@ARM.com 747405SAli.Saidi@ARM.com 757405SAli.Saidi@ARM.comMiscReg 767405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 777405SAli.Saidi@ARM.com{ 787405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 797405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[misc_reg]; 807405SAli.Saidi@ARM.com Addr pc = tc->readPC(); 817405SAli.Saidi@ARM.com if (pc & (ULL(1) << PcJBitShift)) 827405SAli.Saidi@ARM.com cpsr.j = 1; 837405SAli.Saidi@ARM.com else 847405SAli.Saidi@ARM.com cpsr.j = 0; 857405SAli.Saidi@ARM.com if (pc & (ULL(1) << PcTBitShift)) 867405SAli.Saidi@ARM.com cpsr.t = 1; 877405SAli.Saidi@ARM.com else 887405SAli.Saidi@ARM.com cpsr.t = 0; 897405SAli.Saidi@ARM.com return cpsr; 907405SAli.Saidi@ARM.com } 917405SAli.Saidi@ARM.com if (misc_reg >= MISCREG_CP15_UNIMP_START && 927405SAli.Saidi@ARM.com misc_reg < MISCREG_CP15_END) { 937405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s read.\n", 947405SAli.Saidi@ARM.com miscRegName[misc_reg]); 957405SAli.Saidi@ARM.com } 967405SAli.Saidi@ARM.com switch (misc_reg) { 977405SAli.Saidi@ARM.com case MISCREG_CLIDR: 987405SAli.Saidi@ARM.com warn("The clidr register always reports 0 caches.\n"); 997405SAli.Saidi@ARM.com break; 1007405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 1017405SAli.Saidi@ARM.com warn("The ccsidr register isn't implemented and " 1027405SAli.Saidi@ARM.com "always reads as 0.\n"); 1037405SAli.Saidi@ARM.com break; 1047405SAli.Saidi@ARM.com case MISCREG_ID_PFR0: 1057405SAli.Saidi@ARM.com return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM 1067405SAli.Saidi@ARM.com } 1077405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 1087405SAli.Saidi@ARM.com} 1097405SAli.Saidi@ARM.com 1107405SAli.Saidi@ARM.comvoid 1117405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 1127405SAli.Saidi@ARM.com{ 1137405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 1147405SAli.Saidi@ARM.com if (misc_reg == MISCREG_SPSR) { 1157405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 1167405SAli.Saidi@ARM.com switch (cpsr.mode) { 1177405SAli.Saidi@ARM.com case MODE_USER: 1187405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR] = val; 1197405SAli.Saidi@ARM.com return; 1207405SAli.Saidi@ARM.com case MODE_FIQ: 1217405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_FIQ] = val; 1227405SAli.Saidi@ARM.com return; 1237405SAli.Saidi@ARM.com case MODE_IRQ: 1247405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_IRQ] = val; 1257405SAli.Saidi@ARM.com return; 1267405SAli.Saidi@ARM.com case MODE_SVC: 1277405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_SVC] = val; 1287405SAli.Saidi@ARM.com return; 1297405SAli.Saidi@ARM.com case MODE_MON: 1307405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_MON] = val; 1317405SAli.Saidi@ARM.com return; 1327405SAli.Saidi@ARM.com case MODE_ABORT: 1337405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_ABT] = val; 1347405SAli.Saidi@ARM.com return; 1357405SAli.Saidi@ARM.com case MODE_UNDEFINED: 1367405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_UND] = val; 1377405SAli.Saidi@ARM.com return; 1387405SAli.Saidi@ARM.com default: 1397405SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR] = val; 1407405SAli.Saidi@ARM.com return; 1417405SAli.Saidi@ARM.com } 1427405SAli.Saidi@ARM.com } 1437405SAli.Saidi@ARM.com miscRegs[misc_reg] = val; 1447405SAli.Saidi@ARM.com} 1457405SAli.Saidi@ARM.com 1467405SAli.Saidi@ARM.comvoid 1477405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 1487405SAli.Saidi@ARM.com{ 1497405SAli.Saidi@ARM.com MiscReg newVal = val; 1507405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 1517405SAli.Saidi@ARM.com updateRegMap(val); 1527405SAli.Saidi@ARM.com CPSR cpsr = val; 1537405SAli.Saidi@ARM.com DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n", 1547405SAli.Saidi@ARM.com cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 1557405SAli.Saidi@ARM.com Addr npc = tc->readNextPC() & ~PcModeMask; 1567405SAli.Saidi@ARM.com if (cpsr.j) 1577405SAli.Saidi@ARM.com npc = npc | (ULL(1) << PcJBitShift); 1587405SAli.Saidi@ARM.com if (cpsr.t) 1597405SAli.Saidi@ARM.com npc = npc | (ULL(1) << PcTBitShift); 1607405SAli.Saidi@ARM.com 1617405SAli.Saidi@ARM.com tc->setNextPC(npc); 1627408Sgblack@eecs.umich.edu } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 1637405SAli.Saidi@ARM.com misc_reg < MISCREG_CP15_END) { 1647405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s wrote with %#x.\n", 1657405SAli.Saidi@ARM.com miscRegName[misc_reg], val); 1667408Sgblack@eecs.umich.edu } else { 1677408Sgblack@eecs.umich.edu switch (misc_reg) { 1687408Sgblack@eecs.umich.edu case MISCREG_ITSTATE: 1697408Sgblack@eecs.umich.edu { 1707408Sgblack@eecs.umich.edu ITSTATE itstate = newVal; 1717408Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 1727408Sgblack@eecs.umich.edu cpsr.it1 = itstate.bottom2; 1737408Sgblack@eecs.umich.edu cpsr.it2 = itstate.top6; 1747408Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 1757408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, 1767408Sgblack@eecs.umich.edu "Updating ITSTATE -> %#x in CPSR -> %#x.\n", 1777408Sgblack@eecs.umich.edu (uint8_t)itstate, (uint32_t)cpsr); 1787405SAli.Saidi@ARM.com } 1797408Sgblack@eecs.umich.edu break; 1807408Sgblack@eecs.umich.edu case MISCREG_CPACR: 1817408Sgblack@eecs.umich.edu { 1827408Sgblack@eecs.umich.edu CPACR newCpacr = 0; 1837408Sgblack@eecs.umich.edu CPACR valCpacr = val; 1847408Sgblack@eecs.umich.edu newCpacr.cp10 = valCpacr.cp10; 1857408Sgblack@eecs.umich.edu newCpacr.cp11 = valCpacr.cp11; 1867408Sgblack@eecs.umich.edu if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) { 1877408Sgblack@eecs.umich.edu panic("Disabling coprocessors isn't implemented.\n"); 1887408Sgblack@eecs.umich.edu } 1897408Sgblack@eecs.umich.edu newVal = newCpacr; 1907408Sgblack@eecs.umich.edu } 1917408Sgblack@eecs.umich.edu break; 1927408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 1937408Sgblack@eecs.umich.edu warn("The csselr register isn't implemented.\n"); 1947408Sgblack@eecs.umich.edu break; 1957408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 1967408Sgblack@eecs.umich.edu { 1977408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 1987408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 1997408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 2007408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 2017408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 2027408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 2037408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 2047408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 2057408Sgblack@eecs.umich.edu fpscrMask.len = ones; 2067408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 2077408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 2087408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 2097408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 2107408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 2117408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 2127408Sgblack@eecs.umich.edu fpscrMask.v = ones; 2137408Sgblack@eecs.umich.edu fpscrMask.c = ones; 2147408Sgblack@eecs.umich.edu fpscrMask.z = ones; 2157408Sgblack@eecs.umich.edu fpscrMask.n = ones; 2167408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 2177408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 2187408Sgblack@eecs.umich.edu } 2197408Sgblack@eecs.umich.edu break; 2207408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 2217408Sgblack@eecs.umich.edu { 2227408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 2237408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 2247408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 2257408Sgblack@eecs.umich.edu } 2267408Sgblack@eecs.umich.edu break; 2277408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 2287408Sgblack@eecs.umich.edu { 2297408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 2307408Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 2317408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 2327408Sgblack@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 2337408Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 2347408Sgblack@eecs.umich.edu return; 2357408Sgblack@eecs.umich.edu } 2367408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 2377408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 2387408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 2397408Sgblack@eecs.umich.edu case MISCREG_MPIDR: 2407408Sgblack@eecs.umich.edu case MISCREG_FPSID: 2417408Sgblack@eecs.umich.edu return; 2427408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 2437408Sgblack@eecs.umich.edu case MISCREG_TLBIALL: 2447408Sgblack@eecs.umich.edu warn("Need to flush all TLBs in MP\n"); 2457408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 2467408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 2477408Sgblack@eecs.umich.edu return; 2487408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 2497408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 2507408Sgblack@eecs.umich.edu return; 2517408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 2527408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 2537408Sgblack@eecs.umich.edu return; 2547408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 2557408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 2567408Sgblack@eecs.umich.edu warn("Need to flush all TLBs in MP\n"); 2577408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 2587408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 2597408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 2607408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 2617408Sgblack@eecs.umich.edu return; 2627408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 2637408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 2647408Sgblack@eecs.umich.edu warn("Need to flush all TLBs in MP\n"); 2657408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 2667408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 2677408Sgblack@eecs.umich.edu return; 2687408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 2697408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 2707408Sgblack@eecs.umich.edu warn("Need to flush all TLBs in MP\n"); 2717408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 2727408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 2737408Sgblack@eecs.umich.edu return; 2747408Sgblack@eecs.umich.edu case MISCREG_ITLBIMVA: 2757408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 2767408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 2777408Sgblack@eecs.umich.edu return; 2787408Sgblack@eecs.umich.edu case MISCREG_DTLBIMVA: 2797408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 2807408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 2817408Sgblack@eecs.umich.edu return; 2827408Sgblack@eecs.umich.edu case MISCREG_ITLBIASID: 2837408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 2847408Sgblack@eecs.umich.edu return; 2857408Sgblack@eecs.umich.edu case MISCREG_DTLBIASID: 2867408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 2877405SAli.Saidi@ARM.com return; 2887405SAli.Saidi@ARM.com } 2897405SAli.Saidi@ARM.com } 2907405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 2917405SAli.Saidi@ARM.com} 2927405SAli.Saidi@ARM.com 2937405SAli.Saidi@ARM.com} 294