isa.cc revision 13581
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "arch/arm/tlbi_op.hh"
46#include "cpu/base.hh"
47#include "cpu/checker/cpu.hh"
48#include "debug/Arm.hh"
49#include "debug/MiscRegs.hh"
50#include "dev/arm/generic_timer.hh"
51#include "dev/arm/gic_v3.hh"
52#include "dev/arm/gic_v3_cpu_interface.hh"
53#include "params/ArmISA.hh"
54#include "sim/faults.hh"
55#include "sim/stat_control.hh"
56#include "sim/system.hh"
57
58namespace ArmISA
59{
60
61ISA::ISA(Params *p)
62    : SimObject(p),
63      system(NULL),
64      _decoderFlavour(p->decoderFlavour),
65      _vecRegRenameMode(p->vecRegRenameMode),
66      pmu(p->pmu),
67      impdefAsNop(p->impdef_nop)
68{
69    miscRegs[MISCREG_SCTLR_RST] = 0;
70
71    // Hook up a dummy device if we haven't been configured with a
72    // real PMU. By using a dummy device, we don't need to check that
73    // the PMU exist every time we try to access a PMU register.
74    if (!pmu)
75        pmu = &dummyDevice;
76
77    // Give all ISA devices a pointer to this ISA
78    pmu->setISA(this);
79
80    system = dynamic_cast<ArmSystem *>(p->system);
81
82    // Cache system-level properties
83    if (FullSystem && system) {
84        highestELIs64 = system->highestELIs64();
85        haveSecurity = system->haveSecurity();
86        haveLPAE = system->haveLPAE();
87        haveCrypto = system->haveCrypto();
88        haveVirtualization = system->haveVirtualization();
89        haveLargeAsid64 = system->haveLargeAsid64();
90        physAddrRange = system->physAddrRange();
91    } else {
92        highestELIs64 = true; // ArmSystem::highestELIs64 does the same
93        haveSecurity = haveLPAE = haveVirtualization = false;
94        haveCrypto = true;
95        haveLargeAsid64 = false;
96        physAddrRange = 32;  // dummy value
97    }
98
99    // GICv3 CPU interface system registers are supported
100    haveGICv3CPUInterface = false;
101
102    if (system && dynamic_cast<Gicv3 *>(system->getGIC())) {
103        haveGICv3CPUInterface = true;
104    }
105
106    initializeMiscRegMetadata();
107    preUnflattenMiscReg();
108
109    clear();
110}
111
112std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
113
114const ArmISAParams *
115ISA::params() const
116{
117    return dynamic_cast<const Params *>(_params);
118}
119
120void
121ISA::clear()
122{
123    const Params *p(params());
124
125    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
126    memset(miscRegs, 0, sizeof(miscRegs));
127
128    initID32(p);
129
130    // We always initialize AArch64 ID registers even
131    // if we are in AArch32. This is done since if we
132    // are in SE mode we don't know if our ArmProcess is
133    // AArch32 or AArch64
134    initID64(p);
135
136    // Start with an event in the mailbox
137    miscRegs[MISCREG_SEV_MAILBOX] = 1;
138
139    // Separate Instruction and Data TLBs
140    miscRegs[MISCREG_TLBTR] = 1;
141
142    MVFR0 mvfr0 = 0;
143    mvfr0.advSimdRegisters = 2;
144    mvfr0.singlePrecision = 2;
145    mvfr0.doublePrecision = 2;
146    mvfr0.vfpExceptionTrapping = 0;
147    mvfr0.divide = 1;
148    mvfr0.squareRoot = 1;
149    mvfr0.shortVectors = 1;
150    mvfr0.roundingModes = 1;
151    miscRegs[MISCREG_MVFR0] = mvfr0;
152
153    MVFR1 mvfr1 = 0;
154    mvfr1.flushToZero = 1;
155    mvfr1.defaultNaN = 1;
156    mvfr1.advSimdLoadStore = 1;
157    mvfr1.advSimdInteger = 1;
158    mvfr1.advSimdSinglePrecision = 1;
159    mvfr1.advSimdHalfPrecision = 1;
160    mvfr1.vfpHalfPrecision = 1;
161    miscRegs[MISCREG_MVFR1] = mvfr1;
162
163    // Reset values of PRRR and NMRR are implementation dependent
164
165    // @todo: PRRR and NMRR in secure state?
166    miscRegs[MISCREG_PRRR_NS] =
167        (1 << 19) | // 19
168        (0 << 18) | // 18
169        (0 << 17) | // 17
170        (1 << 16) | // 16
171        (2 << 14) | // 15:14
172        (0 << 12) | // 13:12
173        (2 << 10) | // 11:10
174        (2 << 8)  | // 9:8
175        (2 << 6)  | // 7:6
176        (2 << 4)  | // 5:4
177        (1 << 2)  | // 3:2
178        0;          // 1:0
179
180    miscRegs[MISCREG_NMRR_NS] =
181        (1 << 30) | // 31:30
182        (0 << 26) | // 27:26
183        (0 << 24) | // 25:24
184        (3 << 22) | // 23:22
185        (2 << 20) | // 21:20
186        (0 << 18) | // 19:18
187        (0 << 16) | // 17:16
188        (1 << 14) | // 15:14
189        (0 << 12) | // 13:12
190        (2 << 10) | // 11:10
191        (0 << 8)  | // 9:8
192        (3 << 6)  | // 7:6
193        (2 << 4)  | // 5:4
194        (0 << 2)  | // 3:2
195        0;          // 1:0
196
197    if (FullSystem && system->highestELIs64()) {
198        // Initialize AArch64 state
199        clear64(p);
200        return;
201    }
202
203    // Initialize AArch32 state...
204    clear32(p, sctlr_rst);
205}
206
207void
208ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
209{
210    CPSR cpsr = 0;
211    cpsr.mode = MODE_USER;
212
213    if (FullSystem) {
214        miscRegs[MISCREG_MVBAR] = system->resetAddr();
215    }
216
217    miscRegs[MISCREG_CPSR] = cpsr;
218    updateRegMap(cpsr);
219
220    SCTLR sctlr = 0;
221    sctlr.te = (bool) sctlr_rst.te;
222    sctlr.nmfi = (bool) sctlr_rst.nmfi;
223    sctlr.v = (bool) sctlr_rst.v;
224    sctlr.u = 1;
225    sctlr.xp = 1;
226    sctlr.rao2 = 1;
227    sctlr.rao3 = 1;
228    sctlr.rao4 = 0xf;  // SCTLR[6:3]
229    sctlr.uci = 1;
230    sctlr.dze = 1;
231    miscRegs[MISCREG_SCTLR_NS] = sctlr;
232    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
233    miscRegs[MISCREG_HCPTR] = 0;
234
235    miscRegs[MISCREG_CPACR] = 0;
236
237    miscRegs[MISCREG_FPSID] = p->fpsid;
238
239    if (haveLPAE) {
240        TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
241        ttbcr.eae = 0;
242        miscRegs[MISCREG_TTBCR_NS] = ttbcr;
243        // Enforce consistency with system-level settings
244        miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
245    }
246
247    if (haveSecurity) {
248        miscRegs[MISCREG_SCTLR_S] = sctlr;
249        miscRegs[MISCREG_SCR] = 0;
250        miscRegs[MISCREG_VBAR_S] = 0;
251    } else {
252        // we're always non-secure
253        miscRegs[MISCREG_SCR] = 1;
254    }
255
256    //XXX We need to initialize the rest of the state.
257}
258
259void
260ISA::clear64(const ArmISAParams *p)
261{
262    CPSR cpsr = 0;
263    Addr rvbar = system->resetAddr();
264    switch (system->highestEL()) {
265        // Set initial EL to highest implemented EL using associated stack
266        // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
267        // value
268      case EL3:
269        cpsr.mode = MODE_EL3H;
270        miscRegs[MISCREG_RVBAR_EL3] = rvbar;
271        break;
272      case EL2:
273        cpsr.mode = MODE_EL2H;
274        miscRegs[MISCREG_RVBAR_EL2] = rvbar;
275        break;
276      case EL1:
277        cpsr.mode = MODE_EL1H;
278        miscRegs[MISCREG_RVBAR_EL1] = rvbar;
279        break;
280      default:
281        panic("Invalid highest implemented exception level");
282        break;
283    }
284
285    // Initialize rest of CPSR
286    cpsr.daif = 0xf;  // Mask all interrupts
287    cpsr.ss = 0;
288    cpsr.il = 0;
289    miscRegs[MISCREG_CPSR] = cpsr;
290    updateRegMap(cpsr);
291
292    // Initialize other control registers
293    miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
294    if (haveSecurity) {
295        miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
296        miscRegs[MISCREG_SCR_EL3]   = 0x00000030;  // RES1 fields
297    } else if (haveVirtualization) {
298        // also  MISCREG_SCTLR_EL2 (by mapping)
299        miscRegs[MISCREG_HSCTLR] = 0x30c50830;
300    } else {
301        // also  MISCREG_SCTLR_EL1 (by mapping)
302        miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
303        // Always non-secure
304        miscRegs[MISCREG_SCR_EL3] = 1;
305    }
306}
307
308void
309ISA::initID32(const ArmISAParams *p)
310{
311    // Initialize configurable default values
312    miscRegs[MISCREG_MIDR] = p->midr;
313    miscRegs[MISCREG_MIDR_EL1] = p->midr;
314    miscRegs[MISCREG_VPIDR] = p->midr;
315
316    miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
317    miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
318    miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
319    miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
320    miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
321    miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
322
323    miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
324    miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
325    miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
326    miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
327
328    miscRegs[MISCREG_ID_ISAR5] = insertBits(
329        miscRegs[MISCREG_ID_ISAR5], 19, 4,
330        haveCrypto ? 0x1112 : 0x0);
331}
332
333void
334ISA::initID64(const ArmISAParams *p)
335{
336    // Initialize configurable id registers
337    miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
338    miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
339    miscRegs[MISCREG_ID_AA64DFR0_EL1] =
340        (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
341        (p->pmu ?             0x0000000000000100ULL : 0); // Enable PMUv3
342
343    miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
344    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
345    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
346    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
347    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
348    miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
349
350    miscRegs[MISCREG_ID_DFR0_EL1] =
351        (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
352
353    miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
354
355    // Enforce consistency with system-level settings...
356
357    // EL3
358    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
359        miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
360        haveSecurity ? 0x2 : 0x0);
361    // EL2
362    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
363        miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
364        haveVirtualization ? 0x2 : 0x0);
365    // Large ASID support
366    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
367        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
368        haveLargeAsid64 ? 0x2 : 0x0);
369    // Physical address size
370    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
371        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
372        encodePhysAddrRange64(physAddrRange));
373    // Crypto
374    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
375        miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
376        haveCrypto ? 0x1112 : 0x0);
377}
378
379void
380ISA::startup(ThreadContext *tc)
381{
382    pmu->setThreadContext(tc);
383
384    if (system) {
385        Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
386        if (gicv3) {
387            gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
388            gicv3CpuInterface->setISA(this);
389        }
390    }
391}
392
393
394RegVal
395ISA::readMiscRegNoEffect(int misc_reg) const
396{
397    assert(misc_reg < NumMiscRegs);
398
399    const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
400    const auto &map = getMiscIndices(misc_reg);
401    int lower = map.first, upper = map.second;
402    // NB!: apply architectural masks according to desired register,
403    // despite possibly getting value from different (mapped) register.
404    auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
405                                          |(miscRegs[upper] << 32));
406    if (val & reg.res0()) {
407        DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
408                miscRegName[misc_reg], val & reg.res0());
409    }
410    if ((val & reg.res1()) != reg.res1()) {
411        DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
412                miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
413    }
414    return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
415}
416
417
418RegVal
419ISA::readMiscReg(int misc_reg, ThreadContext *tc)
420{
421    CPSR cpsr = 0;
422    PCState pc = 0;
423    SCR scr = 0;
424
425    if (misc_reg == MISCREG_CPSR) {
426        cpsr = miscRegs[misc_reg];
427        pc = tc->pcState();
428        cpsr.j = pc.jazelle() ? 1 : 0;
429        cpsr.t = pc.thumb() ? 1 : 0;
430        return cpsr;
431    }
432
433#ifndef NDEBUG
434    if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
435        if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
436            warn("Unimplemented system register %s read.\n",
437                 miscRegName[misc_reg]);
438        else
439            panic("Unimplemented system register %s read.\n",
440                  miscRegName[misc_reg]);
441    }
442#endif
443
444    switch (unflattenMiscReg(misc_reg)) {
445      case MISCREG_HCR:
446        {
447            if (!haveVirtualization)
448                return 0;
449            else
450                return readMiscRegNoEffect(MISCREG_HCR);
451        }
452      case MISCREG_CPACR:
453        {
454            const uint32_t ones = (uint32_t)(-1);
455            CPACR cpacrMask = 0;
456            // Only cp10, cp11, and ase are implemented, nothing else should
457            // be readable? (straight copy from the write code)
458            cpacrMask.cp10 = ones;
459            cpacrMask.cp11 = ones;
460            cpacrMask.asedis = ones;
461
462            // Security Extensions may limit the readability of CPACR
463            if (haveSecurity) {
464                scr = readMiscRegNoEffect(MISCREG_SCR);
465                cpsr = readMiscRegNoEffect(MISCREG_CPSR);
466                if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
467                    NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
468                    // NB: Skipping the full loop, here
469                    if (!nsacr.cp10) cpacrMask.cp10 = 0;
470                    if (!nsacr.cp11) cpacrMask.cp11 = 0;
471                }
472            }
473            RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
474            val &= cpacrMask;
475            DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
476                    miscRegName[misc_reg], val);
477            return val;
478        }
479      case MISCREG_MPIDR:
480      case MISCREG_MPIDR_EL1:
481        return readMPIDR(system, tc);
482      case MISCREG_VMPIDR:
483      case MISCREG_VMPIDR_EL2:
484        // top bit defined as RES1
485        return readMiscRegNoEffect(misc_reg) | 0x80000000;
486      case MISCREG_ID_AFR0: // not implemented, so alias MIDR
487      case MISCREG_REVIDR:  // not implemented, so alias MIDR
488      case MISCREG_MIDR:
489        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
490        scr  = readMiscRegNoEffect(MISCREG_SCR);
491        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
492            return readMiscRegNoEffect(misc_reg);
493        } else {
494            return readMiscRegNoEffect(MISCREG_VPIDR);
495        }
496        break;
497      case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
498      case MISCREG_JMCR:  // Jazelle trivial implementation, RAZ/WI
499      case MISCREG_JIDR:  // Jazelle trivial implementation, RAZ/WI
500      case MISCREG_AIDR:  // AUX ID set to 0
501      case MISCREG_TCMTR: // No TCM's
502        return 0;
503
504      case MISCREG_CLIDR:
505        warn_once("The clidr register always reports 0 caches.\n");
506        warn_once("clidr LoUIS field of 0b001 to match current "
507                  "ARM implementations.\n");
508        return 0x00200000;
509      case MISCREG_CCSIDR:
510        warn_once("The ccsidr register isn't implemented and "
511                "always reads as 0.\n");
512        break;
513      case MISCREG_CTR:                 // AArch32, ARMv7, top bit set
514      case MISCREG_CTR_EL0:             // AArch64
515        {
516            //all caches have the same line size in gem5
517            //4 byte words in ARM
518            unsigned lineSizeWords =
519                tc->getSystemPtr()->cacheLineSize() / 4;
520            unsigned log2LineSizeWords = 0;
521
522            while (lineSizeWords >>= 1) {
523                ++log2LineSizeWords;
524            }
525
526            CTR ctr = 0;
527            //log2 of minimun i-cache line size (words)
528            ctr.iCacheLineSize = log2LineSizeWords;
529            //b11 - gem5 uses pipt
530            ctr.l1IndexPolicy = 0x3;
531            //log2 of minimum d-cache line size (words)
532            ctr.dCacheLineSize = log2LineSizeWords;
533            //log2 of max reservation size (words)
534            ctr.erg = log2LineSizeWords;
535            //log2 of max writeback size (words)
536            ctr.cwg = log2LineSizeWords;
537            //b100 - gem5 format is ARMv7
538            ctr.format = 0x4;
539
540            return ctr;
541        }
542      case MISCREG_ACTLR:
543        warn("Not doing anything for miscreg ACTLR\n");
544        break;
545
546      case MISCREG_PMXEVTYPER_PMCCFILTR:
547      case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
548      case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
549      case MISCREG_PMCR ... MISCREG_PMOVSSET:
550        return pmu->readMiscReg(misc_reg);
551
552      case MISCREG_CPSR_Q:
553        panic("shouldn't be reading this register seperately\n");
554      case MISCREG_FPSCR_QC:
555        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
556      case MISCREG_FPSCR_EXC:
557        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
558      case MISCREG_FPSR:
559        {
560            const uint32_t ones = (uint32_t)(-1);
561            FPSCR fpscrMask = 0;
562            fpscrMask.ioc = ones;
563            fpscrMask.dzc = ones;
564            fpscrMask.ofc = ones;
565            fpscrMask.ufc = ones;
566            fpscrMask.ixc = ones;
567            fpscrMask.idc = ones;
568            fpscrMask.qc = ones;
569            fpscrMask.v = ones;
570            fpscrMask.c = ones;
571            fpscrMask.z = ones;
572            fpscrMask.n = ones;
573            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
574        }
575      case MISCREG_FPCR:
576        {
577            const uint32_t ones = (uint32_t)(-1);
578            FPSCR fpscrMask  = 0;
579            fpscrMask.len    = ones;
580            fpscrMask.stride = ones;
581            fpscrMask.rMode  = ones;
582            fpscrMask.fz     = ones;
583            fpscrMask.dn     = ones;
584            fpscrMask.ahp    = ones;
585            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
586        }
587      case MISCREG_NZCV:
588        {
589            CPSR cpsr = 0;
590            cpsr.nz   = tc->readCCReg(CCREG_NZ);
591            cpsr.c    = tc->readCCReg(CCREG_C);
592            cpsr.v    = tc->readCCReg(CCREG_V);
593            return cpsr;
594        }
595      case MISCREG_DAIF:
596        {
597            CPSR cpsr = 0;
598            cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
599            return cpsr;
600        }
601      case MISCREG_SP_EL0:
602        {
603            return tc->readIntReg(INTREG_SP0);
604        }
605      case MISCREG_SP_EL1:
606        {
607            return tc->readIntReg(INTREG_SP1);
608        }
609      case MISCREG_SP_EL2:
610        {
611            return tc->readIntReg(INTREG_SP2);
612        }
613      case MISCREG_SPSEL:
614        {
615            return miscRegs[MISCREG_CPSR] & 0x1;
616        }
617      case MISCREG_CURRENTEL:
618        {
619            return miscRegs[MISCREG_CPSR] & 0xc;
620        }
621      case MISCREG_L2CTLR:
622        {
623            // mostly unimplemented, just set NumCPUs field from sim and return
624            L2CTLR l2ctlr = 0;
625            // b00:1CPU to b11:4CPUs
626            l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
627            return l2ctlr;
628        }
629      case MISCREG_DBGDIDR:
630        /* For now just implement the version number.
631         * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
632         */
633        return 0x5 << 16;
634      case MISCREG_DBGDSCRint:
635        return 0;
636      case MISCREG_ISR:
637        return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
638            readMiscRegNoEffect(MISCREG_HCR),
639            readMiscRegNoEffect(MISCREG_CPSR),
640            readMiscRegNoEffect(MISCREG_SCR));
641      case MISCREG_ISR_EL1:
642        return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
643            readMiscRegNoEffect(MISCREG_HCR_EL2),
644            readMiscRegNoEffect(MISCREG_CPSR),
645            readMiscRegNoEffect(MISCREG_SCR_EL3));
646      case MISCREG_DCZID_EL0:
647        return 0x04;  // DC ZVA clear 64-byte chunks
648      case MISCREG_HCPTR:
649        {
650            RegVal val = readMiscRegNoEffect(misc_reg);
651            // The trap bit associated with CP14 is defined as RAZ
652            val &= ~(1 << 14);
653            // If a CP bit in NSACR is 0 then the corresponding bit in
654            // HCPTR is RAO/WI
655            bool secure_lookup = haveSecurity &&
656                inSecureState(readMiscRegNoEffect(MISCREG_SCR),
657                              readMiscRegNoEffect(MISCREG_CPSR));
658            if (!secure_lookup) {
659                RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
660                val |= (mask ^ 0x7FFF) & 0xBFFF;
661            }
662            // Set the bits for unimplemented coprocessors to RAO/WI
663            val |= 0x33FF;
664            return (val);
665        }
666      case MISCREG_HDFAR: // alias for secure DFAR
667        return readMiscRegNoEffect(MISCREG_DFAR_S);
668      case MISCREG_HIFAR: // alias for secure IFAR
669        return readMiscRegNoEffect(MISCREG_IFAR_S);
670
671      case MISCREG_ID_PFR0:
672        // !ThumbEE | !Jazelle | Thumb | ARM
673        return 0x00000031;
674      case MISCREG_ID_PFR1:
675        {   // Timer | Virti | !M Profile | TrustZone | ARMv4
676            bool haveTimer = (system->getGenericTimer() != NULL);
677            return 0x00000001
678                 | (haveSecurity       ? 0x00000010 : 0x0)
679                 | (haveVirtualization ? 0x00001000 : 0x0)
680                 | (haveTimer          ? 0x00010000 : 0x0);
681        }
682      case MISCREG_ID_AA64PFR0_EL1:
683        return 0x0000000000000002 | // AArch{64,32} supported at EL0
684               0x0000000000000020                               | // EL1
685               (haveVirtualization    ? 0x0000000000000200 : 0) | // EL2
686               (haveSecurity          ? 0x0000000000002000 : 0) | // EL3
687               (haveGICv3CPUInterface ? 0x0000000001000000 : 0);
688      case MISCREG_ID_AA64PFR1_EL1:
689        return 0; // bits [63:0] RES0 (reserved for future use)
690
691      // Generic Timer registers
692      case MISCREG_CNTHV_CTL_EL2:
693      case MISCREG_CNTHV_CVAL_EL2:
694      case MISCREG_CNTHV_TVAL_EL2:
695      case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
696      case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
697      case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
698      case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
699        return getGenericTimer(tc).readMiscReg(misc_reg);
700
701      case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
702      case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
703        return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
704
705      default:
706        break;
707
708    }
709    return readMiscRegNoEffect(misc_reg);
710}
711
712void
713ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val)
714{
715    assert(misc_reg < NumMiscRegs);
716
717    const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
718    const auto &map = getMiscIndices(misc_reg);
719    int lower = map.first, upper = map.second;
720
721    auto v = (val & ~reg.wi()) | reg.rao();
722    if (upper > 0) {
723        miscRegs[lower] = bits(v, 31, 0);
724        miscRegs[upper] = bits(v, 63, 32);
725        DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
726                misc_reg, lower, upper, v);
727    } else {
728        miscRegs[lower] = v;
729        DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
730                misc_reg, lower, v);
731    }
732}
733
734void
735ISA::setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc)
736{
737
738    RegVal newVal = val;
739    bool secure_lookup;
740    SCR scr;
741
742    if (misc_reg == MISCREG_CPSR) {
743        updateRegMap(val);
744
745
746        CPSR old_cpsr = miscRegs[MISCREG_CPSR];
747        int old_mode = old_cpsr.mode;
748        CPSR cpsr = val;
749        if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
750            getITBPtr(tc)->invalidateMiscReg();
751            getDTBPtr(tc)->invalidateMiscReg();
752        }
753
754        DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
755                miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
756        PCState pc = tc->pcState();
757        pc.nextThumb(cpsr.t);
758        pc.nextJazelle(cpsr.j);
759        pc.illegalExec(cpsr.il == 1);
760
761        // Follow slightly different semantics if a CheckerCPU object
762        // is connected
763        CheckerCPU *checker = tc->getCheckerCpuPtr();
764        if (checker) {
765            tc->pcStateNoRecord(pc);
766        } else {
767            tc->pcState(pc);
768        }
769    } else {
770#ifndef NDEBUG
771        if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
772            if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
773                warn("Unimplemented system register %s write with %#x.\n",
774                    miscRegName[misc_reg], val);
775            else
776                panic("Unimplemented system register %s write with %#x.\n",
777                    miscRegName[misc_reg], val);
778        }
779#endif
780        switch (unflattenMiscReg(misc_reg)) {
781          case MISCREG_CPACR:
782            {
783
784                const uint32_t ones = (uint32_t)(-1);
785                CPACR cpacrMask = 0;
786                // Only cp10, cp11, and ase are implemented, nothing else should
787                // be writable
788                cpacrMask.cp10 = ones;
789                cpacrMask.cp11 = ones;
790                cpacrMask.asedis = ones;
791
792                // Security Extensions may limit the writability of CPACR
793                if (haveSecurity) {
794                    scr = readMiscRegNoEffect(MISCREG_SCR);
795                    CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
796                    if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
797                        NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
798                        // NB: Skipping the full loop, here
799                        if (!nsacr.cp10) cpacrMask.cp10 = 0;
800                        if (!nsacr.cp11) cpacrMask.cp11 = 0;
801                    }
802                }
803
804                RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);
805                newVal &= cpacrMask;
806                newVal |= old_val & ~cpacrMask;
807                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
808                        miscRegName[misc_reg], newVal);
809            }
810            break;
811          case MISCREG_CPTR_EL2:
812            {
813                const uint32_t ones = (uint32_t)(-1);
814                CPTR cptrMask = 0;
815                cptrMask.tcpac = ones;
816                cptrMask.tta = ones;
817                cptrMask.tfp = ones;
818                newVal &= cptrMask;
819                cptrMask = 0;
820                cptrMask.res1_13_12_el2 = ones;
821                cptrMask.res1_9_0_el2 = ones;
822                newVal |= cptrMask;
823                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
824                        miscRegName[misc_reg], newVal);
825            }
826            break;
827          case MISCREG_CPTR_EL3:
828            {
829                const uint32_t ones = (uint32_t)(-1);
830                CPTR cptrMask = 0;
831                cptrMask.tcpac = ones;
832                cptrMask.tta = ones;
833                cptrMask.tfp = ones;
834                newVal &= cptrMask;
835                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
836                        miscRegName[misc_reg], newVal);
837            }
838            break;
839          case MISCREG_CSSELR:
840            warn_once("The csselr register isn't implemented.\n");
841            return;
842
843          case MISCREG_DC_ZVA_Xt:
844            warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
845            return;
846
847          case MISCREG_FPSCR:
848            {
849                const uint32_t ones = (uint32_t)(-1);
850                FPSCR fpscrMask = 0;
851                fpscrMask.ioc = ones;
852                fpscrMask.dzc = ones;
853                fpscrMask.ofc = ones;
854                fpscrMask.ufc = ones;
855                fpscrMask.ixc = ones;
856                fpscrMask.idc = ones;
857                fpscrMask.ioe = ones;
858                fpscrMask.dze = ones;
859                fpscrMask.ofe = ones;
860                fpscrMask.ufe = ones;
861                fpscrMask.ixe = ones;
862                fpscrMask.ide = ones;
863                fpscrMask.len = ones;
864                fpscrMask.stride = ones;
865                fpscrMask.rMode = ones;
866                fpscrMask.fz = ones;
867                fpscrMask.dn = ones;
868                fpscrMask.ahp = ones;
869                fpscrMask.qc = ones;
870                fpscrMask.v = ones;
871                fpscrMask.c = ones;
872                fpscrMask.z = ones;
873                fpscrMask.n = ones;
874                newVal = (newVal & (uint32_t)fpscrMask) |
875                         (readMiscRegNoEffect(MISCREG_FPSCR) &
876                          ~(uint32_t)fpscrMask);
877                tc->getDecoderPtr()->setContext(newVal);
878            }
879            break;
880          case MISCREG_FPSR:
881            {
882                const uint32_t ones = (uint32_t)(-1);
883                FPSCR fpscrMask = 0;
884                fpscrMask.ioc = ones;
885                fpscrMask.dzc = ones;
886                fpscrMask.ofc = ones;
887                fpscrMask.ufc = ones;
888                fpscrMask.ixc = ones;
889                fpscrMask.idc = ones;
890                fpscrMask.qc = ones;
891                fpscrMask.v = ones;
892                fpscrMask.c = ones;
893                fpscrMask.z = ones;
894                fpscrMask.n = ones;
895                newVal = (newVal & (uint32_t)fpscrMask) |
896                         (readMiscRegNoEffect(MISCREG_FPSCR) &
897                          ~(uint32_t)fpscrMask);
898                misc_reg = MISCREG_FPSCR;
899            }
900            break;
901          case MISCREG_FPCR:
902            {
903                const uint32_t ones = (uint32_t)(-1);
904                FPSCR fpscrMask  = 0;
905                fpscrMask.len    = ones;
906                fpscrMask.stride = ones;
907                fpscrMask.rMode  = ones;
908                fpscrMask.fz     = ones;
909                fpscrMask.dn     = ones;
910                fpscrMask.ahp    = ones;
911                newVal = (newVal & (uint32_t)fpscrMask) |
912                         (readMiscRegNoEffect(MISCREG_FPSCR) &
913                          ~(uint32_t)fpscrMask);
914                misc_reg = MISCREG_FPSCR;
915            }
916            break;
917          case MISCREG_CPSR_Q:
918            {
919                assert(!(newVal & ~CpsrMaskQ));
920                newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
921                misc_reg = MISCREG_CPSR;
922            }
923            break;
924          case MISCREG_FPSCR_QC:
925            {
926                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
927                         (newVal & FpscrQcMask);
928                misc_reg = MISCREG_FPSCR;
929            }
930            break;
931          case MISCREG_FPSCR_EXC:
932            {
933                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
934                         (newVal & FpscrExcMask);
935                misc_reg = MISCREG_FPSCR;
936            }
937            break;
938          case MISCREG_FPEXC:
939            {
940                // vfpv3 architecture, section B.6.1 of DDI04068
941                // bit 29 - valid only if fpexc[31] is 0
942                const uint32_t fpexcMask = 0x60000000;
943                newVal = (newVal & fpexcMask) |
944                         (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
945            }
946            break;
947          case MISCREG_HCR:
948            {
949                if (!haveVirtualization)
950                    return;
951            }
952            break;
953          case MISCREG_IFSR:
954            {
955                // ARM ARM (ARM DDI 0406C.b) B4.1.96
956                const uint32_t ifsrMask =
957                    mask(31, 13) | mask(11, 11) | mask(8, 6);
958                newVal = newVal & ~ifsrMask;
959            }
960            break;
961          case MISCREG_DFSR:
962            {
963                // ARM ARM (ARM DDI 0406C.b) B4.1.52
964                const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
965                newVal = newVal & ~dfsrMask;
966            }
967            break;
968          case MISCREG_AMAIR0:
969          case MISCREG_AMAIR1:
970            {
971                // ARM ARM (ARM DDI 0406C.b) B4.1.5
972                // Valid only with LPAE
973                if (!haveLPAE)
974                    return;
975                DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
976            }
977            break;
978          case MISCREG_SCR:
979            getITBPtr(tc)->invalidateMiscReg();
980            getDTBPtr(tc)->invalidateMiscReg();
981            break;
982          case MISCREG_SCTLR:
983            {
984                DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
985                scr = readMiscRegNoEffect(MISCREG_SCR);
986
987                MiscRegIndex sctlr_idx;
988                if (haveSecurity && !highestELIs64 && !scr.ns) {
989                    sctlr_idx = MISCREG_SCTLR_S;
990                } else {
991                    sctlr_idx =  MISCREG_SCTLR_NS;
992                }
993
994                SCTLR sctlr = miscRegs[sctlr_idx];
995                SCTLR new_sctlr = newVal;
996                new_sctlr.nmfi =  ((bool)sctlr.nmfi) && !haveVirtualization;
997                miscRegs[sctlr_idx] = (RegVal)new_sctlr;
998                getITBPtr(tc)->invalidateMiscReg();
999                getDTBPtr(tc)->invalidateMiscReg();
1000            }
1001          case MISCREG_MIDR:
1002          case MISCREG_ID_PFR0:
1003          case MISCREG_ID_PFR1:
1004          case MISCREG_ID_DFR0:
1005          case MISCREG_ID_MMFR0:
1006          case MISCREG_ID_MMFR1:
1007          case MISCREG_ID_MMFR2:
1008          case MISCREG_ID_MMFR3:
1009          case MISCREG_ID_ISAR0:
1010          case MISCREG_ID_ISAR1:
1011          case MISCREG_ID_ISAR2:
1012          case MISCREG_ID_ISAR3:
1013          case MISCREG_ID_ISAR4:
1014          case MISCREG_ID_ISAR5:
1015
1016          case MISCREG_MPIDR:
1017          case MISCREG_FPSID:
1018          case MISCREG_TLBTR:
1019          case MISCREG_MVFR0:
1020          case MISCREG_MVFR1:
1021
1022          case MISCREG_ID_AA64AFR0_EL1:
1023          case MISCREG_ID_AA64AFR1_EL1:
1024          case MISCREG_ID_AA64DFR0_EL1:
1025          case MISCREG_ID_AA64DFR1_EL1:
1026          case MISCREG_ID_AA64ISAR0_EL1:
1027          case MISCREG_ID_AA64ISAR1_EL1:
1028          case MISCREG_ID_AA64MMFR0_EL1:
1029          case MISCREG_ID_AA64MMFR1_EL1:
1030          case MISCREG_ID_AA64MMFR2_EL1:
1031          case MISCREG_ID_AA64PFR0_EL1:
1032          case MISCREG_ID_AA64PFR1_EL1:
1033            // ID registers are constants.
1034            return;
1035
1036          // TLB Invalidate All
1037          case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1038            {
1039                assert32(tc);
1040                scr = readMiscReg(MISCREG_SCR, tc);
1041
1042                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1043                tlbiOp(tc);
1044                return;
1045            }
1046          // TLB Invalidate All, Inner Shareable
1047          case MISCREG_TLBIALLIS:
1048            {
1049                assert32(tc);
1050                scr = readMiscReg(MISCREG_SCR, tc);
1051
1052                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1053                tlbiOp.broadcast(tc);
1054                return;
1055            }
1056          // Instruction TLB Invalidate All
1057          case MISCREG_ITLBIALL:
1058            {
1059                assert32(tc);
1060                scr = readMiscReg(MISCREG_SCR, tc);
1061
1062                ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1063                tlbiOp(tc);
1064                return;
1065            }
1066          // Data TLB Invalidate All
1067          case MISCREG_DTLBIALL:
1068            {
1069                assert32(tc);
1070                scr = readMiscReg(MISCREG_SCR, tc);
1071
1072                DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1073                tlbiOp(tc);
1074                return;
1075            }
1076          // TLB Invalidate by VA
1077          // mcr tlbimval(is) is invalidating all matching entries
1078          // regardless of the level of lookup, since in gem5 we cache
1079          // in the tlb the last level of lookup only.
1080          case MISCREG_TLBIMVA:
1081          case MISCREG_TLBIMVAL:
1082            {
1083                assert32(tc);
1084                scr = readMiscReg(MISCREG_SCR, tc);
1085
1086                TLBIMVA tlbiOp(EL1,
1087                               haveSecurity && !scr.ns,
1088                               mbits(newVal, 31, 12),
1089                               bits(newVal, 7,0));
1090
1091                tlbiOp(tc);
1092                return;
1093            }
1094          // TLB Invalidate by VA, Inner Shareable
1095          case MISCREG_TLBIMVAIS:
1096          case MISCREG_TLBIMVALIS:
1097            {
1098                assert32(tc);
1099                scr = readMiscReg(MISCREG_SCR, tc);
1100
1101                TLBIMVA tlbiOp(EL1,
1102                               haveSecurity && !scr.ns,
1103                               mbits(newVal, 31, 12),
1104                               bits(newVal, 7,0));
1105
1106                tlbiOp.broadcast(tc);
1107                return;
1108            }
1109          // TLB Invalidate by ASID match
1110          case MISCREG_TLBIASID:
1111            {
1112                assert32(tc);
1113                scr = readMiscReg(MISCREG_SCR, tc);
1114
1115                TLBIASID tlbiOp(EL1,
1116                                haveSecurity && !scr.ns,
1117                                bits(newVal, 7,0));
1118
1119                tlbiOp(tc);
1120                return;
1121            }
1122          // TLB Invalidate by ASID match, Inner Shareable
1123          case MISCREG_TLBIASIDIS:
1124            {
1125                assert32(tc);
1126                scr = readMiscReg(MISCREG_SCR, tc);
1127
1128                TLBIASID tlbiOp(EL1,
1129                                haveSecurity && !scr.ns,
1130                                bits(newVal, 7,0));
1131
1132                tlbiOp.broadcast(tc);
1133                return;
1134            }
1135          // mcr tlbimvaal(is) is invalidating all matching entries
1136          // regardless of the level of lookup, since in gem5 we cache
1137          // in the tlb the last level of lookup only.
1138          // TLB Invalidate by VA, All ASID
1139          case MISCREG_TLBIMVAA:
1140          case MISCREG_TLBIMVAAL:
1141            {
1142                assert32(tc);
1143                scr = readMiscReg(MISCREG_SCR, tc);
1144
1145                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1146                                mbits(newVal, 31,12), false);
1147
1148                tlbiOp(tc);
1149                return;
1150            }
1151          // TLB Invalidate by VA, All ASID, Inner Shareable
1152          case MISCREG_TLBIMVAAIS:
1153          case MISCREG_TLBIMVAALIS:
1154            {
1155                assert32(tc);
1156                scr = readMiscReg(MISCREG_SCR, tc);
1157
1158                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1159                                mbits(newVal, 31,12), false);
1160
1161                tlbiOp.broadcast(tc);
1162                return;
1163            }
1164          // mcr tlbimvalh(is) is invalidating all matching entries
1165          // regardless of the level of lookup, since in gem5 we cache
1166          // in the tlb the last level of lookup only.
1167          // TLB Invalidate by VA, Hyp mode
1168          case MISCREG_TLBIMVAH:
1169          case MISCREG_TLBIMVALH:
1170            {
1171                assert32(tc);
1172                scr = readMiscReg(MISCREG_SCR, tc);
1173
1174                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1175                                mbits(newVal, 31,12), true);
1176
1177                tlbiOp(tc);
1178                return;
1179            }
1180          // TLB Invalidate by VA, Hyp mode, Inner Shareable
1181          case MISCREG_TLBIMVAHIS:
1182          case MISCREG_TLBIMVALHIS:
1183            {
1184                assert32(tc);
1185                scr = readMiscReg(MISCREG_SCR, tc);
1186
1187                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1188                                mbits(newVal, 31,12), true);
1189
1190                tlbiOp.broadcast(tc);
1191                return;
1192            }
1193          // mcr tlbiipas2l(is) is invalidating all matching entries
1194          // regardless of the level of lookup, since in gem5 we cache
1195          // in the tlb the last level of lookup only.
1196          // TLB Invalidate by Intermediate Physical Address, Stage 2
1197          case MISCREG_TLBIIPAS2:
1198          case MISCREG_TLBIIPAS2L:
1199            {
1200                assert32(tc);
1201                scr = readMiscReg(MISCREG_SCR, tc);
1202
1203                TLBIIPA tlbiOp(EL1,
1204                               haveSecurity && !scr.ns,
1205                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1206
1207                tlbiOp(tc);
1208                return;
1209            }
1210          // TLB Invalidate by Intermediate Physical Address, Stage 2,
1211          // Inner Shareable
1212          case MISCREG_TLBIIPAS2IS:
1213          case MISCREG_TLBIIPAS2LIS:
1214            {
1215                assert32(tc);
1216                scr = readMiscReg(MISCREG_SCR, tc);
1217
1218                TLBIIPA tlbiOp(EL1,
1219                               haveSecurity && !scr.ns,
1220                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1221
1222                tlbiOp.broadcast(tc);
1223                return;
1224            }
1225          // Instruction TLB Invalidate by VA
1226          case MISCREG_ITLBIMVA:
1227            {
1228                assert32(tc);
1229                scr = readMiscReg(MISCREG_SCR, tc);
1230
1231                ITLBIMVA tlbiOp(EL1,
1232                                haveSecurity && !scr.ns,
1233                                mbits(newVal, 31, 12),
1234                                bits(newVal, 7,0));
1235
1236                tlbiOp(tc);
1237                return;
1238            }
1239          // Data TLB Invalidate by VA
1240          case MISCREG_DTLBIMVA:
1241            {
1242                assert32(tc);
1243                scr = readMiscReg(MISCREG_SCR, tc);
1244
1245                DTLBIMVA tlbiOp(EL1,
1246                                haveSecurity && !scr.ns,
1247                                mbits(newVal, 31, 12),
1248                                bits(newVal, 7,0));
1249
1250                tlbiOp(tc);
1251                return;
1252            }
1253          // Instruction TLB Invalidate by ASID match
1254          case MISCREG_ITLBIASID:
1255            {
1256                assert32(tc);
1257                scr = readMiscReg(MISCREG_SCR, tc);
1258
1259                ITLBIASID tlbiOp(EL1,
1260                                 haveSecurity && !scr.ns,
1261                                 bits(newVal, 7,0));
1262
1263                tlbiOp(tc);
1264                return;
1265            }
1266          // Data TLB Invalidate by ASID match
1267          case MISCREG_DTLBIASID:
1268            {
1269                assert32(tc);
1270                scr = readMiscReg(MISCREG_SCR, tc);
1271
1272                DTLBIASID tlbiOp(EL1,
1273                                 haveSecurity && !scr.ns,
1274                                 bits(newVal, 7,0));
1275
1276                tlbiOp(tc);
1277                return;
1278            }
1279          // TLB Invalidate All, Non-Secure Non-Hyp
1280          case MISCREG_TLBIALLNSNH:
1281            {
1282                assert32(tc);
1283
1284                TLBIALLN tlbiOp(EL1, false);
1285                tlbiOp(tc);
1286                return;
1287            }
1288          // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1289          case MISCREG_TLBIALLNSNHIS:
1290            {
1291                assert32(tc);
1292
1293                TLBIALLN tlbiOp(EL1, false);
1294                tlbiOp.broadcast(tc);
1295                return;
1296            }
1297          // TLB Invalidate All, Hyp mode
1298          case MISCREG_TLBIALLH:
1299            {
1300                assert32(tc);
1301
1302                TLBIALLN tlbiOp(EL1, true);
1303                tlbiOp(tc);
1304                return;
1305            }
1306          // TLB Invalidate All, Hyp mode, Inner Shareable
1307          case MISCREG_TLBIALLHIS:
1308            {
1309                assert32(tc);
1310
1311                TLBIALLN tlbiOp(EL1, true);
1312                tlbiOp.broadcast(tc);
1313                return;
1314            }
1315          // AArch64 TLB Invalidate All, EL3
1316          case MISCREG_TLBI_ALLE3:
1317            {
1318                assert64(tc);
1319
1320                TLBIALL tlbiOp(EL3, true);
1321                tlbiOp(tc);
1322                return;
1323            }
1324          // AArch64 TLB Invalidate All, EL3, Inner Shareable
1325          case MISCREG_TLBI_ALLE3IS:
1326            {
1327                assert64(tc);
1328
1329                TLBIALL tlbiOp(EL3, true);
1330                tlbiOp.broadcast(tc);
1331                return;
1332            }
1333          // AArch64 TLB Invalidate All, EL2, Inner Shareable
1334          case MISCREG_TLBI_ALLE2:
1335          case MISCREG_TLBI_ALLE2IS:
1336            {
1337                assert64(tc);
1338                scr = readMiscReg(MISCREG_SCR, tc);
1339
1340                TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
1341                tlbiOp(tc);
1342                return;
1343            }
1344          // AArch64 TLB Invalidate All, EL1
1345          case MISCREG_TLBI_ALLE1:
1346          case MISCREG_TLBI_VMALLE1:
1347          case MISCREG_TLBI_VMALLS12E1:
1348            // @todo: handle VMID and stage 2 to enable Virtualization
1349            {
1350                assert64(tc);
1351                scr = readMiscReg(MISCREG_SCR, tc);
1352
1353                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1354                tlbiOp(tc);
1355                return;
1356            }
1357          // AArch64 TLB Invalidate All, EL1, Inner Shareable
1358          case MISCREG_TLBI_ALLE1IS:
1359          case MISCREG_TLBI_VMALLE1IS:
1360          case MISCREG_TLBI_VMALLS12E1IS:
1361            // @todo: handle VMID and stage 2 to enable Virtualization
1362            {
1363                assert64(tc);
1364                scr = readMiscReg(MISCREG_SCR, tc);
1365
1366                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1367                tlbiOp.broadcast(tc);
1368                return;
1369            }
1370          // VAEx(IS) and VALEx(IS) are the same because TLBs
1371          // only store entries
1372          // from the last level of translation table walks
1373          // @todo: handle VMID to enable Virtualization
1374          // AArch64 TLB Invalidate by VA, EL3
1375          case MISCREG_TLBI_VAE3_Xt:
1376          case MISCREG_TLBI_VALE3_Xt:
1377            {
1378                assert64(tc);
1379
1380                TLBIMVA tlbiOp(EL3, true,
1381                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1382                               0xbeef);
1383                tlbiOp(tc);
1384                return;
1385            }
1386          // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1387          case MISCREG_TLBI_VAE3IS_Xt:
1388          case MISCREG_TLBI_VALE3IS_Xt:
1389            {
1390                assert64(tc);
1391
1392                TLBIMVA tlbiOp(EL3, true,
1393                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1394                               0xbeef);
1395
1396                tlbiOp.broadcast(tc);
1397                return;
1398            }
1399          // AArch64 TLB Invalidate by VA, EL2
1400          case MISCREG_TLBI_VAE2_Xt:
1401          case MISCREG_TLBI_VALE2_Xt:
1402            {
1403                assert64(tc);
1404                scr = readMiscReg(MISCREG_SCR, tc);
1405
1406                TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1407                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1408                               0xbeef);
1409                tlbiOp(tc);
1410                return;
1411            }
1412          // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1413          case MISCREG_TLBI_VAE2IS_Xt:
1414          case MISCREG_TLBI_VALE2IS_Xt:
1415            {
1416                assert64(tc);
1417                scr = readMiscReg(MISCREG_SCR, tc);
1418
1419                TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1420                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1421                               0xbeef);
1422
1423                tlbiOp.broadcast(tc);
1424                return;
1425            }
1426          // AArch64 TLB Invalidate by VA, EL1
1427          case MISCREG_TLBI_VAE1_Xt:
1428          case MISCREG_TLBI_VALE1_Xt:
1429            {
1430                assert64(tc);
1431                scr = readMiscReg(MISCREG_SCR, tc);
1432                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1433                                              bits(newVal, 55, 48);
1434
1435                TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1436                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1437                               asid);
1438
1439                tlbiOp(tc);
1440                return;
1441            }
1442          // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1443          case MISCREG_TLBI_VAE1IS_Xt:
1444          case MISCREG_TLBI_VALE1IS_Xt:
1445            {
1446                assert64(tc);
1447                scr = readMiscReg(MISCREG_SCR, tc);
1448                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1449                                              bits(newVal, 55, 48);
1450
1451                TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1452                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1453                               asid);
1454
1455                tlbiOp.broadcast(tc);
1456                return;
1457            }
1458          // AArch64 TLB Invalidate by ASID, EL1
1459          // @todo: handle VMID to enable Virtualization
1460          case MISCREG_TLBI_ASIDE1_Xt:
1461            {
1462                assert64(tc);
1463                scr = readMiscReg(MISCREG_SCR, tc);
1464                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1465                                              bits(newVal, 55, 48);
1466
1467                TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1468                tlbiOp(tc);
1469                return;
1470            }
1471          // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1472          case MISCREG_TLBI_ASIDE1IS_Xt:
1473            {
1474                assert64(tc);
1475                scr = readMiscReg(MISCREG_SCR, tc);
1476                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1477                                              bits(newVal, 55, 48);
1478
1479                TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1480                tlbiOp.broadcast(tc);
1481                return;
1482            }
1483          // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1484          // entries from the last level of translation table walks
1485          // AArch64 TLB Invalidate by VA, All ASID, EL1
1486          case MISCREG_TLBI_VAAE1_Xt:
1487          case MISCREG_TLBI_VAALE1_Xt:
1488            {
1489                assert64(tc);
1490                scr = readMiscReg(MISCREG_SCR, tc);
1491
1492                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1493                    static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
1494
1495                tlbiOp(tc);
1496                return;
1497            }
1498          // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1499          case MISCREG_TLBI_VAAE1IS_Xt:
1500          case MISCREG_TLBI_VAALE1IS_Xt:
1501            {
1502                assert64(tc);
1503                scr = readMiscReg(MISCREG_SCR, tc);
1504
1505                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1506                    static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
1507
1508                tlbiOp.broadcast(tc);
1509                return;
1510            }
1511          // AArch64 TLB Invalidate by Intermediate Physical Address,
1512          // Stage 2, EL1
1513          case MISCREG_TLBI_IPAS2E1_Xt:
1514          case MISCREG_TLBI_IPAS2LE1_Xt:
1515            {
1516                assert64(tc);
1517                scr = readMiscReg(MISCREG_SCR, tc);
1518
1519                TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1520                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1521
1522                tlbiOp(tc);
1523                return;
1524            }
1525          // AArch64 TLB Invalidate by Intermediate Physical Address,
1526          // Stage 2, EL1, Inner Shareable
1527          case MISCREG_TLBI_IPAS2E1IS_Xt:
1528          case MISCREG_TLBI_IPAS2LE1IS_Xt:
1529            {
1530                assert64(tc);
1531                scr = readMiscReg(MISCREG_SCR, tc);
1532
1533                TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1534                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1535
1536                tlbiOp.broadcast(tc);
1537                return;
1538            }
1539          case MISCREG_ACTLR:
1540            warn("Not doing anything for write of miscreg ACTLR\n");
1541            break;
1542
1543          case MISCREG_PMXEVTYPER_PMCCFILTR:
1544          case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1545          case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1546          case MISCREG_PMCR ... MISCREG_PMOVSSET:
1547            pmu->setMiscReg(misc_reg, newVal);
1548            break;
1549
1550
1551          case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1552            {
1553                HSTR hstrMask = 0;
1554                hstrMask.tjdbx = 1;
1555                newVal &= ~((uint32_t) hstrMask);
1556                break;
1557            }
1558          case MISCREG_HCPTR:
1559            {
1560                // If a CP bit in NSACR is 0 then the corresponding bit in
1561                // HCPTR is RAO/WI. Same applies to NSASEDIS
1562                secure_lookup = haveSecurity &&
1563                    inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1564                                  readMiscRegNoEffect(MISCREG_CPSR));
1565                if (!secure_lookup) {
1566                    RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1567                    RegVal mask =
1568                        (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1569                    newVal = (newVal & ~mask) | (oldValue & mask);
1570                }
1571                break;
1572            }
1573          case MISCREG_HDFAR: // alias for secure DFAR
1574            misc_reg = MISCREG_DFAR_S;
1575            break;
1576          case MISCREG_HIFAR: // alias for secure IFAR
1577            misc_reg = MISCREG_IFAR_S;
1578            break;
1579          case MISCREG_ATS1CPR:
1580          case MISCREG_ATS1CPW:
1581          case MISCREG_ATS1CUR:
1582          case MISCREG_ATS1CUW:
1583          case MISCREG_ATS12NSOPR:
1584          case MISCREG_ATS12NSOPW:
1585          case MISCREG_ATS12NSOUR:
1586          case MISCREG_ATS12NSOUW:
1587          case MISCREG_ATS1HR:
1588          case MISCREG_ATS1HW:
1589            {
1590              Request::Flags flags = 0;
1591              BaseTLB::Mode mode = BaseTLB::Read;
1592              TLB::ArmTranslationType tranType = TLB::NormalTran;
1593              Fault fault;
1594              switch(misc_reg) {
1595                case MISCREG_ATS1CPR:
1596                  flags    = TLB::MustBeOne;
1597                  tranType = TLB::S1CTran;
1598                  mode     = BaseTLB::Read;
1599                  break;
1600                case MISCREG_ATS1CPW:
1601                  flags    = TLB::MustBeOne;
1602                  tranType = TLB::S1CTran;
1603                  mode     = BaseTLB::Write;
1604                  break;
1605                case MISCREG_ATS1CUR:
1606                  flags    = TLB::MustBeOne | TLB::UserMode;
1607                  tranType = TLB::S1CTran;
1608                  mode     = BaseTLB::Read;
1609                  break;
1610                case MISCREG_ATS1CUW:
1611                  flags    = TLB::MustBeOne | TLB::UserMode;
1612                  tranType = TLB::S1CTran;
1613                  mode     = BaseTLB::Write;
1614                  break;
1615                case MISCREG_ATS12NSOPR:
1616                  if (!haveSecurity)
1617                      panic("Security Extensions required for ATS12NSOPR");
1618                  flags    = TLB::MustBeOne;
1619                  tranType = TLB::S1S2NsTran;
1620                  mode     = BaseTLB::Read;
1621                  break;
1622                case MISCREG_ATS12NSOPW:
1623                  if (!haveSecurity)
1624                      panic("Security Extensions required for ATS12NSOPW");
1625                  flags    = TLB::MustBeOne;
1626                  tranType = TLB::S1S2NsTran;
1627                  mode     = BaseTLB::Write;
1628                  break;
1629                case MISCREG_ATS12NSOUR:
1630                  if (!haveSecurity)
1631                      panic("Security Extensions required for ATS12NSOUR");
1632                  flags    = TLB::MustBeOne | TLB::UserMode;
1633                  tranType = TLB::S1S2NsTran;
1634                  mode     = BaseTLB::Read;
1635                  break;
1636                case MISCREG_ATS12NSOUW:
1637                  if (!haveSecurity)
1638                      panic("Security Extensions required for ATS12NSOUW");
1639                  flags    = TLB::MustBeOne | TLB::UserMode;
1640                  tranType = TLB::S1S2NsTran;
1641                  mode     = BaseTLB::Write;
1642                  break;
1643                case MISCREG_ATS1HR: // only really useful from secure mode.
1644                  flags    = TLB::MustBeOne;
1645                  tranType = TLB::HypMode;
1646                  mode     = BaseTLB::Read;
1647                  break;
1648                case MISCREG_ATS1HW:
1649                  flags    = TLB::MustBeOne;
1650                  tranType = TLB::HypMode;
1651                  mode     = BaseTLB::Write;
1652                  break;
1653              }
1654              // If we're in timing mode then doing the translation in
1655              // functional mode then we're slightly distorting performance
1656              // results obtained from simulations. The translation should be
1657              // done in the same mode the core is running in. NOTE: This
1658              // can't be an atomic translation because that causes problems
1659              // with unexpected atomic snoop requests.
1660              warn("Translating via %s in functional mode! Fix Me!\n",
1661                   miscRegName[misc_reg]);
1662
1663              auto req = std::make_shared<Request>(
1664                  0, val, 0, flags,  Request::funcMasterId,
1665                  tc->pcState().pc(), tc->contextId());
1666
1667              fault = getDTBPtr(tc)->translateFunctional(
1668                      req, tc, mode, tranType);
1669
1670              TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1671              HCR   hcr   = readMiscRegNoEffect(MISCREG_HCR);
1672
1673              RegVal newVal;
1674              if (fault == NoFault) {
1675                  Addr paddr = req->getPaddr();
1676                  if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1677                     ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1678                      newVal = (paddr & mask(39, 12)) |
1679                               (getDTBPtr(tc)->getAttr());
1680                  } else {
1681                      newVal = (paddr & 0xfffff000) |
1682                               (getDTBPtr(tc)->getAttr());
1683                  }
1684                  DPRINTF(MiscRegs,
1685                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1686                          val, newVal);
1687              } else {
1688                  ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1689                  armFault->update(tc);
1690                  // Set fault bit and FSR
1691                  FSR fsr = armFault->getFsr(tc);
1692
1693                  newVal = ((fsr >> 9) & 1) << 11;
1694                  if (newVal) {
1695                    // LPAE - rearange fault status
1696                    newVal |= ((fsr >>  0) & 0x3f) << 1;
1697                  } else {
1698                    // VMSA - rearange fault status
1699                    newVal |= ((fsr >>  0) & 0xf) << 1;
1700                    newVal |= ((fsr >> 10) & 0x1) << 5;
1701                    newVal |= ((fsr >> 12) & 0x1) << 6;
1702                  }
1703                  newVal |= 0x1; // F bit
1704                  newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1705                  newVal |= armFault->isStage2() ? 0x200 : 0;
1706                  DPRINTF(MiscRegs,
1707                          "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1708                          val, fsr, newVal);
1709              }
1710              setMiscRegNoEffect(MISCREG_PAR, newVal);
1711              return;
1712            }
1713          case MISCREG_TTBCR:
1714            {
1715                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1716                const uint32_t ones = (uint32_t)(-1);
1717                TTBCR ttbcrMask = 0;
1718                TTBCR ttbcrNew = newVal;
1719
1720                // ARM DDI 0406C.b, ARMv7-32
1721                ttbcrMask.n = ones; // T0SZ
1722                if (haveSecurity) {
1723                    ttbcrMask.pd0 = ones;
1724                    ttbcrMask.pd1 = ones;
1725                }
1726                ttbcrMask.epd0 = ones;
1727                ttbcrMask.irgn0 = ones;
1728                ttbcrMask.orgn0 = ones;
1729                ttbcrMask.sh0 = ones;
1730                ttbcrMask.ps = ones; // T1SZ
1731                ttbcrMask.a1 = ones;
1732                ttbcrMask.epd1 = ones;
1733                ttbcrMask.irgn1 = ones;
1734                ttbcrMask.orgn1 = ones;
1735                ttbcrMask.sh1 = ones;
1736                if (haveLPAE)
1737                    ttbcrMask.eae = ones;
1738
1739                if (haveLPAE && ttbcrNew.eae) {
1740                    newVal = newVal & ttbcrMask;
1741                } else {
1742                    newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1743                }
1744                // Invalidate TLB MiscReg
1745                getITBPtr(tc)->invalidateMiscReg();
1746                getDTBPtr(tc)->invalidateMiscReg();
1747                break;
1748            }
1749          case MISCREG_TTBR0:
1750          case MISCREG_TTBR1:
1751            {
1752                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1753                if (haveLPAE) {
1754                    if (ttbcr.eae) {
1755                        // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1756                        // ARMv8 AArch32 bit 63-56 only
1757                        uint64_t ttbrMask = mask(63,56) | mask(47,40);
1758                        newVal = (newVal & (~ttbrMask));
1759                    }
1760                }
1761                // Invalidate TLB MiscReg
1762                getITBPtr(tc)->invalidateMiscReg();
1763                getDTBPtr(tc)->invalidateMiscReg();
1764                break;
1765            }
1766          case MISCREG_SCTLR_EL1:
1767          case MISCREG_CONTEXTIDR:
1768          case MISCREG_PRRR:
1769          case MISCREG_NMRR:
1770          case MISCREG_MAIR0:
1771          case MISCREG_MAIR1:
1772          case MISCREG_DACR:
1773          case MISCREG_VTTBR:
1774          case MISCREG_SCR_EL3:
1775          case MISCREG_HCR_EL2:
1776          case MISCREG_TCR_EL1:
1777          case MISCREG_TCR_EL2:
1778          case MISCREG_TCR_EL3:
1779          case MISCREG_SCTLR_EL2:
1780          case MISCREG_SCTLR_EL3:
1781          case MISCREG_HSCTLR:
1782          case MISCREG_TTBR0_EL1:
1783          case MISCREG_TTBR1_EL1:
1784          case MISCREG_TTBR0_EL2:
1785          case MISCREG_TTBR1_EL2:
1786          case MISCREG_TTBR0_EL3:
1787            getITBPtr(tc)->invalidateMiscReg();
1788            getDTBPtr(tc)->invalidateMiscReg();
1789            break;
1790          case MISCREG_NZCV:
1791            {
1792                CPSR cpsr = val;
1793
1794                tc->setCCReg(CCREG_NZ, cpsr.nz);
1795                tc->setCCReg(CCREG_C,  cpsr.c);
1796                tc->setCCReg(CCREG_V,  cpsr.v);
1797            }
1798            break;
1799          case MISCREG_DAIF:
1800            {
1801                CPSR cpsr = miscRegs[MISCREG_CPSR];
1802                cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1803                newVal = cpsr;
1804                misc_reg = MISCREG_CPSR;
1805            }
1806            break;
1807          case MISCREG_SP_EL0:
1808            tc->setIntReg(INTREG_SP0, newVal);
1809            break;
1810          case MISCREG_SP_EL1:
1811            tc->setIntReg(INTREG_SP1, newVal);
1812            break;
1813          case MISCREG_SP_EL2:
1814            tc->setIntReg(INTREG_SP2, newVal);
1815            break;
1816          case MISCREG_SPSEL:
1817            {
1818                CPSR cpsr = miscRegs[MISCREG_CPSR];
1819                cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1820                newVal = cpsr;
1821                misc_reg = MISCREG_CPSR;
1822            }
1823            break;
1824          case MISCREG_CURRENTEL:
1825            {
1826                CPSR cpsr = miscRegs[MISCREG_CPSR];
1827                cpsr.el = (uint8_t) ((CPSR) newVal).el;
1828                newVal = cpsr;
1829                misc_reg = MISCREG_CPSR;
1830            }
1831            break;
1832          case MISCREG_AT_S1E1R_Xt:
1833          case MISCREG_AT_S1E1W_Xt:
1834          case MISCREG_AT_S1E0R_Xt:
1835          case MISCREG_AT_S1E0W_Xt:
1836          case MISCREG_AT_S1E2R_Xt:
1837          case MISCREG_AT_S1E2W_Xt:
1838          case MISCREG_AT_S12E1R_Xt:
1839          case MISCREG_AT_S12E1W_Xt:
1840          case MISCREG_AT_S12E0R_Xt:
1841          case MISCREG_AT_S12E0W_Xt:
1842          case MISCREG_AT_S1E3R_Xt:
1843          case MISCREG_AT_S1E3W_Xt:
1844            {
1845                RequestPtr req = std::make_shared<Request>();
1846                Request::Flags flags = 0;
1847                BaseTLB::Mode mode = BaseTLB::Read;
1848                TLB::ArmTranslationType tranType = TLB::NormalTran;
1849                Fault fault;
1850                switch(misc_reg) {
1851                  case MISCREG_AT_S1E1R_Xt:
1852                    flags    = TLB::MustBeOne;
1853                    tranType = TLB::S1E1Tran;
1854                    mode     = BaseTLB::Read;
1855                    break;
1856                  case MISCREG_AT_S1E1W_Xt:
1857                    flags    = TLB::MustBeOne;
1858                    tranType = TLB::S1E1Tran;
1859                    mode     = BaseTLB::Write;
1860                    break;
1861                  case MISCREG_AT_S1E0R_Xt:
1862                    flags    = TLB::MustBeOne | TLB::UserMode;
1863                    tranType = TLB::S1E0Tran;
1864                    mode     = BaseTLB::Read;
1865                    break;
1866                  case MISCREG_AT_S1E0W_Xt:
1867                    flags    = TLB::MustBeOne | TLB::UserMode;
1868                    tranType = TLB::S1E0Tran;
1869                    mode     = BaseTLB::Write;
1870                    break;
1871                  case MISCREG_AT_S1E2R_Xt:
1872                    flags    = TLB::MustBeOne;
1873                    tranType = TLB::S1E2Tran;
1874                    mode     = BaseTLB::Read;
1875                    break;
1876                  case MISCREG_AT_S1E2W_Xt:
1877                    flags    = TLB::MustBeOne;
1878                    tranType = TLB::S1E2Tran;
1879                    mode     = BaseTLB::Write;
1880                    break;
1881                  case MISCREG_AT_S12E0R_Xt:
1882                    flags    = TLB::MustBeOne | TLB::UserMode;
1883                    tranType = TLB::S12E0Tran;
1884                    mode     = BaseTLB::Read;
1885                    break;
1886                  case MISCREG_AT_S12E0W_Xt:
1887                    flags    = TLB::MustBeOne | TLB::UserMode;
1888                    tranType = TLB::S12E0Tran;
1889                    mode     = BaseTLB::Write;
1890                    break;
1891                  case MISCREG_AT_S12E1R_Xt:
1892                    flags    = TLB::MustBeOne;
1893                    tranType = TLB::S12E1Tran;
1894                    mode     = BaseTLB::Read;
1895                    break;
1896                  case MISCREG_AT_S12E1W_Xt:
1897                    flags    = TLB::MustBeOne;
1898                    tranType = TLB::S12E1Tran;
1899                    mode     = BaseTLB::Write;
1900                    break;
1901                  case MISCREG_AT_S1E3R_Xt:
1902                    flags    = TLB::MustBeOne;
1903                    tranType = TLB::S1E3Tran;
1904                    mode     = BaseTLB::Read;
1905                    break;
1906                  case MISCREG_AT_S1E3W_Xt:
1907                    flags    = TLB::MustBeOne;
1908                    tranType = TLB::S1E3Tran;
1909                    mode     = BaseTLB::Write;
1910                    break;
1911                }
1912                // If we're in timing mode then doing the translation in
1913                // functional mode then we're slightly distorting performance
1914                // results obtained from simulations. The translation should be
1915                // done in the same mode the core is running in. NOTE: This
1916                // can't be an atomic translation because that causes problems
1917                // with unexpected atomic snoop requests.
1918                warn("Translating via %s in functional mode! Fix Me!\n",
1919                     miscRegName[misc_reg]);
1920
1921                req->setVirt(0, val, 0, flags,  Request::funcMasterId,
1922                               tc->pcState().pc());
1923                req->setContext(tc->contextId());
1924                fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1925                                                           tranType);
1926
1927                RegVal newVal;
1928                if (fault == NoFault) {
1929                    Addr paddr = req->getPaddr();
1930                    uint64_t attr = getDTBPtr(tc)->getAttr();
1931                    uint64_t attr1 = attr >> 56;
1932                    if (!attr1 || attr1 ==0x44) {
1933                        attr |= 0x100;
1934                        attr &= ~ uint64_t(0x80);
1935                    }
1936                    newVal = (paddr & mask(47, 12)) | attr;
1937                    DPRINTF(MiscRegs,
1938                          "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1939                          val, newVal);
1940                } else {
1941                    ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1942                    armFault->update(tc);
1943                    // Set fault bit and FSR
1944                    FSR fsr = armFault->getFsr(tc);
1945
1946                    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1947                    if (cpsr.width) { // AArch32
1948                        newVal = ((fsr >> 9) & 1) << 11;
1949                        // rearrange fault status
1950                        newVal |= ((fsr >>  0) & 0x3f) << 1;
1951                        newVal |= 0x1; // F bit
1952                        newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1953                        newVal |= armFault->isStage2() ? 0x200 : 0;
1954                    } else { // AArch64
1955                        newVal = 1; // F bit
1956                        newVal |= fsr << 1; // FST
1957                        // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1958                        newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1959                        newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1960                        newVal |= 1 << 11; // RES1
1961                    }
1962                    DPRINTF(MiscRegs,
1963                            "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1964                            val, fsr, newVal);
1965                }
1966                setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1967                return;
1968            }
1969          case MISCREG_SPSR_EL3:
1970          case MISCREG_SPSR_EL2:
1971          case MISCREG_SPSR_EL1:
1972            // Force bits 23:21 to 0
1973            newVal = val & ~(0x7 << 21);
1974            break;
1975          case MISCREG_L2CTLR:
1976            warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1977                 miscRegName[misc_reg], uint32_t(val));
1978            break;
1979
1980          // Generic Timer registers
1981          case MISCREG_CNTHV_CTL_EL2:
1982          case MISCREG_CNTHV_CVAL_EL2:
1983          case MISCREG_CNTHV_TVAL_EL2:
1984          case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1985          case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1986          case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1987          case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1988            getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1989            break;
1990
1991          case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
1992          case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
1993            getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal);
1994            return;
1995        }
1996    }
1997    setMiscRegNoEffect(misc_reg, newVal);
1998}
1999
2000BaseISADevice &
2001ISA::getGenericTimer(ThreadContext *tc)
2002{
2003    // We only need to create an ISA interface the first time we try
2004    // to access the timer.
2005    if (timer)
2006        return *timer.get();
2007
2008    assert(system);
2009    GenericTimer *generic_timer(system->getGenericTimer());
2010    if (!generic_timer) {
2011        panic("Trying to get a generic timer from a system that hasn't "
2012              "been configured to use a generic timer.\n");
2013    }
2014
2015    timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2016    timer->setThreadContext(tc);
2017
2018    return *timer.get();
2019}
2020
2021BaseISADevice &
2022ISA::getGICv3CPUInterface(ThreadContext *tc)
2023{
2024    panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
2025    return *gicv3CpuInterface.get();
2026}
2027
2028}
2029
2030ArmISA::ISA *
2031ArmISAParams::create()
2032{
2033    return new ArmISA::ISA(this);
2034}
2035