isa.cc revision 13549
17405SAli.Saidi@ARM.com/* 211573SDylan.Johnson@ARM.com * Copyright (c) 2010-2018 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 439050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 448887Sgeoffrey.blake@arm.com#include "arch/arm/tlb.hh" 4510461SAndreas.Sandberg@ARM.com#include "arch/arm/tlbi_op.hh" 468232Snate@binkert.org#include "cpu/base.hh" 478232Snate@binkert.org#include "cpu/checker/cpu.hh" 4810844Sandreas.sandberg@arm.com#include "debug/Arm.hh" 499384SAndreas.Sandberg@arm.com#include "debug/MiscRegs.hh" 507678Sgblack@eecs.umich.edu#include "dev/arm/generic_timer.hh" 518059SAli.Saidi@ARM.com#include "dev/arm/gic_v3.hh" 528284SAli.Saidi@ARM.com#include "dev/arm/gic_v3_cpu_interface.hh" 537405SAli.Saidi@ARM.com#include "params/ArmISA.hh" 547405SAli.Saidi@ARM.com#include "sim/faults.hh" 557405SAli.Saidi@ARM.com#include "sim/stat_control.hh" 567405SAli.Saidi@ARM.com#include "sim/system.hh" 5710037SARM gem5 Developers 5810037SARM gem5 Developersnamespace ArmISA 5910037SARM gem5 Developers{ 6010037SARM gem5 Developers 6110037SARM gem5 DevelopersISA::ISA(Params *p) 6210037SARM gem5 Developers : SimObject(p), 6310037SARM gem5 Developers system(NULL), 6410037SARM gem5 Developers _decoderFlavour(p->decoderFlavour), 6510037SARM gem5 Developers _vecRegRenameMode(p->vecRegRenameMode), 6610037SARM gem5 Developers pmu(p->pmu), 6710037SARM gem5 Developers impdefAsNop(p->impdef_nop) 6810037SARM gem5 Developers{ 6910037SARM gem5 Developers miscRegs[MISCREG_SCTLR_RST] = 0; 7010037SARM gem5 Developers 7110037SARM gem5 Developers // Hook up a dummy device if we haven't been configured with a 7210037SARM gem5 Developers // real PMU. By using a dummy device, we don't need to check that 7310037SARM gem5 Developers // the PMU exist every time we try to access a PMU register. 7410037SARM gem5 Developers if (!pmu) 7510037SARM gem5 Developers pmu = &dummyDevice; 7610037SARM gem5 Developers 7710037SARM gem5 Developers // Give all ISA devices a pointer to this ISA 7810037SARM gem5 Developers pmu->setISA(this); 7910037SARM gem5 Developers 8010037SARM gem5 Developers system = dynamic_cast<ArmSystem *>(p->system); 8110037SARM gem5 Developers 8210037SARM gem5 Developers // Cache system-level properties 8310037SARM gem5 Developers if (FullSystem && system) { 8410037SARM gem5 Developers highestELIs64 = system->highestELIs64(); 8510037SARM gem5 Developers haveSecurity = system->haveSecurity(); 8610037SARM gem5 Developers haveLPAE = system->haveLPAE(); 8710037SARM gem5 Developers haveCrypto = system->haveCrypto(); 8810037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 8910037SARM gem5 Developers haveLargeAsid64 = system->haveLargeAsid64(); 9010037SARM gem5 Developers physAddrRange = system->physAddrRange(); 9110037SARM gem5 Developers } else { 9210037SARM gem5 Developers highestELIs64 = true; // ArmSystem::highestELIs64 does the same 9310037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 9410037SARM gem5 Developers haveCrypto = true; 9510037SARM gem5 Developers haveLargeAsid64 = false; 9610037SARM gem5 Developers physAddrRange = 32; // dummy value 9710037SARM gem5 Developers } 9810037SARM gem5 Developers 9910037SARM gem5 Developers // GICv3 CPU interface system registers are supported 10010037SARM gem5 Developers haveGICv3CPUInterface = false; 10110037SARM gem5 Developers 10210037SARM gem5 Developers if (system && dynamic_cast<Gicv3 *>(system->getGIC())) { 10310037SARM gem5 Developers haveGICv3CPUInterface = true; 10410037SARM gem5 Developers } 10510037SARM gem5 Developers 10610037SARM gem5 Developers initializeMiscRegMetadata(); 10710037SARM gem5 Developers preUnflattenMiscReg(); 10810037SARM gem5 Developers 10910037SARM gem5 Developers clear(); 11010037SARM gem5 Developers} 11110037SARM gem5 Developers 11210037SARM gem5 Developersstd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 11310037SARM gem5 Developers 11410037SARM gem5 Developersconst ArmISAParams * 11510037SARM gem5 DevelopersISA::params() const 11610037SARM gem5 Developers{ 11710037SARM gem5 Developers return dynamic_cast<const Params *>(_params); 11810037SARM gem5 Developers} 11910037SARM gem5 Developers 12010037SARM gem5 Developersvoid 12110037SARM gem5 DevelopersISA::clear() 12210037SARM gem5 Developers{ 12310037SARM gem5 Developers const Params *p(params()); 12410037SARM gem5 Developers 12510037SARM gem5 Developers SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 12610037SARM gem5 Developers memset(miscRegs, 0, sizeof(miscRegs)); 1279384SAndreas.Sandberg@arm.com 12810461SAndreas.Sandberg@ARM.com initID32(p); 12910461SAndreas.Sandberg@ARM.com 13011165SRekai.GonzalezAlberquilla@arm.com // We always initialize AArch64 ID registers even 13110461SAndreas.Sandberg@ARM.com // if we are in AArch32. This is done since if we 13210461SAndreas.Sandberg@ARM.com // are in SE mode we don't know if our ArmProcess is 1339384SAndreas.Sandberg@arm.com // AArch32 or AArch64 1349384SAndreas.Sandberg@arm.com initID64(p); 1359384SAndreas.Sandberg@arm.com 1369384SAndreas.Sandberg@arm.com // Start with an event in the mailbox 13710037SARM gem5 Developers miscRegs[MISCREG_SEV_MAILBOX] = 1; 13810461SAndreas.Sandberg@ARM.com 13910461SAndreas.Sandberg@ARM.com // Separate Instruction and Data TLBs 14010461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_TLBTR] = 1; 14110461SAndreas.Sandberg@ARM.com 14210461SAndreas.Sandberg@ARM.com MVFR0 mvfr0 = 0; 14310461SAndreas.Sandberg@ARM.com mvfr0.advSimdRegisters = 2; 14410609Sandreas.sandberg@arm.com mvfr0.singlePrecision = 2; 14510609Sandreas.sandberg@arm.com mvfr0.doublePrecision = 2; 14610609Sandreas.sandberg@arm.com mvfr0.vfpExceptionTrapping = 0; 14710037SARM gem5 Developers mvfr0.divide = 1; 14810037SARM gem5 Developers mvfr0.squareRoot = 1; 14910037SARM gem5 Developers mvfr0.shortVectors = 1; 15010037SARM gem5 Developers mvfr0.roundingModes = 1; 15110037SARM gem5 Developers miscRegs[MISCREG_MVFR0] = mvfr0; 15210037SARM gem5 Developers 15310037SARM gem5 Developers MVFR1 mvfr1 = 0; 15410037SARM gem5 Developers mvfr1.flushToZero = 1; 15510037SARM gem5 Developers mvfr1.defaultNaN = 1; 15610037SARM gem5 Developers mvfr1.advSimdLoadStore = 1; 15710037SARM gem5 Developers mvfr1.advSimdInteger = 1; 15810037SARM gem5 Developers mvfr1.advSimdSinglePrecision = 1; 15910037SARM gem5 Developers mvfr1.advSimdHalfPrecision = 1; 16010037SARM gem5 Developers mvfr1.vfpHalfPrecision = 1; 16110037SARM gem5 Developers miscRegs[MISCREG_MVFR1] = mvfr1; 16210037SARM gem5 Developers 16310037SARM gem5 Developers // Reset values of PRRR and NMRR are implementation dependent 16410037SARM gem5 Developers 16510037SARM gem5 Developers // @todo: PRRR and NMRR in secure state? 16610037SARM gem5 Developers miscRegs[MISCREG_PRRR_NS] = 16710037SARM gem5 Developers (1 << 19) | // 19 16810037SARM gem5 Developers (0 << 18) | // 18 16910037SARM gem5 Developers (0 << 17) | // 17 17010037SARM gem5 Developers (1 << 16) | // 16 17110037SARM gem5 Developers (2 << 14) | // 15:14 17210037SARM gem5 Developers (0 << 12) | // 13:12 17310037SARM gem5 Developers (2 << 10) | // 11:10 1749384SAndreas.Sandberg@arm.com (2 << 8) | // 9:8 1759384SAndreas.Sandberg@arm.com (2 << 6) | // 7:6 1769384SAndreas.Sandberg@arm.com (2 << 4) | // 5:4 1779384SAndreas.Sandberg@arm.com (1 << 2) | // 3:2 1789384SAndreas.Sandberg@arm.com 0; // 1:0 1799384SAndreas.Sandberg@arm.com 1809384SAndreas.Sandberg@arm.com miscRegs[MISCREG_NMRR_NS] = 1819384SAndreas.Sandberg@arm.com (1 << 30) | // 31:30 1829384SAndreas.Sandberg@arm.com (0 << 26) | // 27:26 1837427Sgblack@eecs.umich.edu (0 << 24) | // 25:24 1847427Sgblack@eecs.umich.edu (3 << 22) | // 23:22 1857427Sgblack@eecs.umich.edu (2 << 20) | // 21:20 1869385SAndreas.Sandberg@arm.com (0 << 18) | // 19:18 1879385SAndreas.Sandberg@arm.com (0 << 16) | // 17:16 1887427Sgblack@eecs.umich.edu (1 << 14) | // 15:14 1897427Sgblack@eecs.umich.edu (0 << 12) | // 13:12 19010037SARM gem5 Developers (2 << 10) | // 11:10 19110037SARM gem5 Developers (0 << 8) | // 9:8 19210037SARM gem5 Developers (3 << 6) | // 7:6 19310037SARM gem5 Developers (2 << 4) | // 5:4 19410037SARM gem5 Developers (0 << 2) | // 3:2 19510037SARM gem5 Developers 0; // 1:0 19610037SARM gem5 Developers 19710037SARM gem5 Developers if (FullSystem && system->highestELIs64()) { 19810037SARM gem5 Developers // Initialize AArch64 state 19910037SARM gem5 Developers clear64(p); 20010037SARM gem5 Developers return; 20110037SARM gem5 Developers } 20210037SARM gem5 Developers 20310037SARM gem5 Developers // Initialize AArch32 state... 2047427Sgblack@eecs.umich.edu clear32(p, sctlr_rst); 2057427Sgblack@eecs.umich.edu} 2067427Sgblack@eecs.umich.edu 2077427Sgblack@eecs.umich.eduvoid 2087427Sgblack@eecs.umich.eduISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 2097427Sgblack@eecs.umich.edu{ 21010037SARM gem5 Developers CPSR cpsr = 0; 21110037SARM gem5 Developers cpsr.mode = MODE_USER; 21210037SARM gem5 Developers 21310037SARM gem5 Developers if (FullSystem) { 2147427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVBAR] = system->resetAddr(); 2157427Sgblack@eecs.umich.edu } 2167427Sgblack@eecs.umich.edu 21710037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 21810204SAli.Saidi@ARM.com updateRegMap(cpsr); 21910204SAli.Saidi@ARM.com 22010037SARM gem5 Developers SCTLR sctlr = 0; 2217427Sgblack@eecs.umich.edu sctlr.te = (bool) sctlr_rst.te; 22210037SARM gem5 Developers sctlr.nmfi = (bool) sctlr_rst.nmfi; 2237427Sgblack@eecs.umich.edu sctlr.v = (bool) sctlr_rst.v; 22410037SARM gem5 Developers sctlr.u = 1; 2257427Sgblack@eecs.umich.edu sctlr.xp = 1; 2267427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 22710037SARM gem5 Developers sctlr.rao3 = 1; 2287427Sgblack@eecs.umich.edu sctlr.rao4 = 0xf; // SCTLR[6:3] 2297427Sgblack@eecs.umich.edu sctlr.uci = 1; 2307427Sgblack@eecs.umich.edu sctlr.dze = 1; 2317427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_NS] = sctlr; 2327427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 2337427Sgblack@eecs.umich.edu miscRegs[MISCREG_HCPTR] = 0; 2347427Sgblack@eecs.umich.edu 2357427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPACR] = 0; 2367427Sgblack@eecs.umich.edu 2377427Sgblack@eecs.umich.edu miscRegs[MISCREG_FPSID] = p->fpsid; 2387427Sgblack@eecs.umich.edu 2397427Sgblack@eecs.umich.edu if (haveLPAE) { 2407427Sgblack@eecs.umich.edu TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 2417427Sgblack@eecs.umich.edu ttbcr.eae = 0; 2427427Sgblack@eecs.umich.edu miscRegs[MISCREG_TTBCR_NS] = ttbcr; 2437427Sgblack@eecs.umich.edu // Enforce consistency with system-level settings 2447427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 2457427Sgblack@eecs.umich.edu } 2467427Sgblack@eecs.umich.edu 2477427Sgblack@eecs.umich.edu if (haveSecurity) { 2487427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_S] = sctlr; 2497427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR] = 0; 2507427Sgblack@eecs.umich.edu miscRegs[MISCREG_VBAR_S] = 0; 2517436Sdam.sunwoo@arm.com } else { 2527436Sdam.sunwoo@arm.com // we're always non-secure 25310037SARM gem5 Developers miscRegs[MISCREG_SCR] = 1; 25410037SARM gem5 Developers } 2557436Sdam.sunwoo@arm.com 2567436Sdam.sunwoo@arm.com //XXX We need to initialize the rest of the state. 2577436Sdam.sunwoo@arm.com} 2587436Sdam.sunwoo@arm.com 2597436Sdam.sunwoo@arm.comvoid 2607436Sdam.sunwoo@arm.comISA::clear64(const ArmISAParams *p) 2617436Sdam.sunwoo@arm.com{ 2627436Sdam.sunwoo@arm.com CPSR cpsr = 0; 2637436Sdam.sunwoo@arm.com Addr rvbar = system->resetAddr(); 2647436Sdam.sunwoo@arm.com switch (system->highestEL()) { 2657436Sdam.sunwoo@arm.com // Set initial EL to highest implemented EL using associated stack 2667436Sdam.sunwoo@arm.com // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 26710037SARM gem5 Developers // value 2687436Sdam.sunwoo@arm.com case EL3: 2697436Sdam.sunwoo@arm.com cpsr.mode = MODE_EL3H; 2707436Sdam.sunwoo@arm.com miscRegs[MISCREG_RVBAR_EL3] = rvbar; 2717436Sdam.sunwoo@arm.com break; 2727436Sdam.sunwoo@arm.com case EL2: 2737436Sdam.sunwoo@arm.com cpsr.mode = MODE_EL2H; 2747436Sdam.sunwoo@arm.com miscRegs[MISCREG_RVBAR_EL2] = rvbar; 2757436Sdam.sunwoo@arm.com break; 2767436Sdam.sunwoo@arm.com case EL1: 2777436Sdam.sunwoo@arm.com cpsr.mode = MODE_EL1H; 2787436Sdam.sunwoo@arm.com miscRegs[MISCREG_RVBAR_EL1] = rvbar; 2797436Sdam.sunwoo@arm.com break; 2807436Sdam.sunwoo@arm.com default: 2817436Sdam.sunwoo@arm.com panic("Invalid highest implemented exception level"); 2827436Sdam.sunwoo@arm.com break; 2837436Sdam.sunwoo@arm.com } 2847644Sali.saidi@arm.com 2858147SAli.Saidi@ARM.com // Initialize rest of CPSR 2869385SAndreas.Sandberg@arm.com cpsr.daif = 0xf; // Mask all interrupts 2879385SAndreas.Sandberg@arm.com cpsr.ss = 0; 2889385SAndreas.Sandberg@arm.com cpsr.il = 0; 2899385SAndreas.Sandberg@arm.com miscRegs[MISCREG_CPSR] = cpsr; 2909385SAndreas.Sandberg@arm.com updateRegMap(cpsr); 2919385SAndreas.Sandberg@arm.com 2929385SAndreas.Sandberg@arm.com // Initialize other control registers 2939385SAndreas.Sandberg@arm.com miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 2949385SAndreas.Sandberg@arm.com if (haveSecurity) { 2959385SAndreas.Sandberg@arm.com miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 2969385SAndreas.Sandberg@arm.com miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 2979385SAndreas.Sandberg@arm.com } else if (haveVirtualization) { 2989385SAndreas.Sandberg@arm.com // also MISCREG_SCTLR_EL2 (by mapping) 2999385SAndreas.Sandberg@arm.com miscRegs[MISCREG_HSCTLR] = 0x30c50830; 3009385SAndreas.Sandberg@arm.com } else { 3019385SAndreas.Sandberg@arm.com // also MISCREG_SCTLR_EL1 (by mapping) 3029385SAndreas.Sandberg@arm.com miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 3039385SAndreas.Sandberg@arm.com // Always non-secure 30410037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 1; 30510037SARM gem5 Developers } 30610037SARM gem5 Developers} 30710037SARM gem5 Developers 30810037SARM gem5 Developersvoid 30910037SARM gem5 DevelopersISA::initID32(const ArmISAParams *p) 31010037SARM gem5 Developers{ 31110037SARM gem5 Developers // Initialize configurable default values 31210037SARM gem5 Developers miscRegs[MISCREG_MIDR] = p->midr; 31310037SARM gem5 Developers miscRegs[MISCREG_MIDR_EL1] = p->midr; 31410037SARM gem5 Developers miscRegs[MISCREG_VPIDR] = p->midr; 31510037SARM gem5 Developers 31610037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 31710037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 31810037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 31910037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 3208147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 3217427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 3227427Sgblack@eecs.umich.edu 3237427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 32410037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 32510037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 32610037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 32710037SARM gem5 Developers 32810037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR5] = insertBits( 32910037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR5], 19, 4, 33010037SARM gem5 Developers haveCrypto ? 0x1112 : 0x0); 33110037SARM gem5 Developers} 33210037SARM gem5 Developers 33310037SARM gem5 Developersvoid 33410037SARM gem5 DevelopersISA::initID64(const ArmISAParams *p) 33510037SARM gem5 Developers{ 33610037SARM gem5 Developers // Initialize configurable id registers 33710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 33810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 33910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR0_EL1] = 34010037SARM gem5 Developers (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 34110037SARM gem5 Developers (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 34210037SARM gem5 Developers 34310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 34410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 34510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 34610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 34710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 34810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 34910037SARM gem5 Developers 35010037SARM gem5 Developers miscRegs[MISCREG_ID_DFR0_EL1] = 35110037SARM gem5 Developers (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 35210037SARM gem5 Developers 35310037SARM gem5 Developers miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 35410037SARM gem5 Developers 35510037SARM gem5 Developers // Enforce consistency with system-level settings... 35610037SARM gem5 Developers 35710037SARM gem5 Developers // EL3 35810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 35910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 36010037SARM gem5 Developers haveSecurity ? 0x2 : 0x0); 36110037SARM gem5 Developers // EL2 36211574SCurtis.Dunham@arm.com miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 36311574SCurtis.Dunham@arm.com miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 36410037SARM gem5 Developers haveVirtualization ? 0x2 : 0x0); 36510037SARM gem5 Developers // Large ASID support 36610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 36710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 36810037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 36910037SARM gem5 Developers // Physical address size 37010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 37110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 37210037SARM gem5 Developers encodePhysAddrRange64(physAddrRange)); 37310461SAndreas.Sandberg@ARM.com // Crypto 37410461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 37510461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 37610461SAndreas.Sandberg@ARM.com haveCrypto ? 0x1112 : 0x0); 37710037SARM gem5 Developers} 37810037SARM gem5 Developers 37910037SARM gem5 Developersvoid 38010037SARM gem5 DevelopersISA::startup(ThreadContext *tc) 38110037SARM gem5 Developers{ 38210037SARM gem5 Developers pmu->setThreadContext(tc); 38310037SARM gem5 Developers 38410037SARM gem5 Developers if (system) { 38510461SAndreas.Sandberg@ARM.com Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); 38610461SAndreas.Sandberg@ARM.com if (gicv3) { 38710461SAndreas.Sandberg@ARM.com gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); 38810461SAndreas.Sandberg@ARM.com gicv3CpuInterface->setISA(this); 38910461SAndreas.Sandberg@ARM.com } 39010037SARM gem5 Developers } 39110037SARM gem5 Developers} 39210037SARM gem5 Developers 39310037SARM gem5 Developers 39410037SARM gem5 DevelopersMiscReg 39511574SCurtis.Dunham@arm.comISA::readMiscRegNoEffect(int misc_reg) const 39610037SARM gem5 Developers{ 39710037SARM gem5 Developers assert(misc_reg < NumMiscRegs); 39810037SARM gem5 Developers 39911574SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 40010037SARM gem5 Developers const auto &map = getMiscIndices(misc_reg); 40110037SARM gem5 Developers int lower = map.first, upper = map.second; 40210037SARM gem5 Developers // NB!: apply architectural masks according to desired register, 40310037SARM gem5 Developers // despite possibly getting value from different (mapped) register. 40410037SARM gem5 Developers auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 40510037SARM gem5 Developers |(miscRegs[upper] << 32)); 40610037SARM gem5 Developers if (val & reg.res0()) { 40710037SARM gem5 Developers DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 40810037SARM gem5 Developers miscRegName[misc_reg], val & reg.res0()); 40910037SARM gem5 Developers } 4107405SAli.Saidi@ARM.com if ((val & reg.res1()) != reg.res1()) { 41110035Sandreas.hansson@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 4127405SAli.Saidi@ARM.com miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 4137405SAli.Saidi@ARM.com } 4147614Sminkyu.jeong@arm.com return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 41510037SARM gem5 Developers} 41610037SARM gem5 Developers 41710037SARM gem5 Developers 4187614Sminkyu.jeong@arm.comMiscReg 41910037SARM gem5 DevelopersISA::readMiscReg(int misc_reg, ThreadContext *tc) 42010037SARM gem5 Developers{ 42110037SARM gem5 Developers CPSR cpsr = 0; 42210037SARM gem5 Developers PCState pc = 0; 42310037SARM gem5 Developers SCR scr = 0; 42410037SARM gem5 Developers 42510037SARM gem5 Developers if (misc_reg == MISCREG_CPSR) { 42610037SARM gem5 Developers cpsr = miscRegs[misc_reg]; 42710037SARM gem5 Developers pc = tc->pcState(); 42810037SARM gem5 Developers cpsr.j = pc.jazelle() ? 1 : 0; 42910037SARM gem5 Developers cpsr.t = pc.thumb() ? 1 : 0; 43010037SARM gem5 Developers return cpsr; 43110037SARM gem5 Developers } 43210037SARM gem5 Developers 4337614Sminkyu.jeong@arm.com#ifndef NDEBUG 4347405SAli.Saidi@ARM.com if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 4357405SAli.Saidi@ARM.com if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 4367405SAli.Saidi@ARM.com warn("Unimplemented system register %s read.\n", 4377405SAli.Saidi@ARM.com miscRegName[misc_reg]); 4387405SAli.Saidi@ARM.com else 4397405SAli.Saidi@ARM.com panic("Unimplemented system register %s read.\n", 44010037SARM gem5 Developers miscRegName[misc_reg]); 44110037SARM gem5 Developers } 44210037SARM gem5 Developers#endif 4439050Schander.sudanthi@arm.com 4447405SAli.Saidi@ARM.com switch (unflattenMiscReg(misc_reg)) { 44510037SARM gem5 Developers case MISCREG_HCR: 44610037SARM gem5 Developers { 4477720Sgblack@eecs.umich.edu if (!haveVirtualization) 4487720Sgblack@eecs.umich.edu return 0; 4497405SAli.Saidi@ARM.com else 4507405SAli.Saidi@ARM.com return readMiscRegNoEffect(MISCREG_HCR); 4517757SAli.Saidi@ARM.com } 45210037SARM gem5 Developers case MISCREG_CPACR: 45310037SARM gem5 Developers { 45410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 45510037SARM gem5 Developers CPACR cpacrMask = 0; 45610037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 45710037SARM gem5 Developers // be readable? (straight copy from the write code) 45810037SARM gem5 Developers cpacrMask.cp10 = ones; 45910037SARM gem5 Developers cpacrMask.cp11 = ones; 46010037SARM gem5 Developers cpacrMask.asedis = ones; 46110037SARM gem5 Developers 46210037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 46310037SARM gem5 Developers if (haveSecurity) { 46410037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 46510037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 46610037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 46710037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 46810037SARM gem5 Developers // NB: Skipping the full loop, here 46910037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 47010037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 47110037SARM gem5 Developers } 47210037SARM gem5 Developers } 47310037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 47410037SARM gem5 Developers val &= cpacrMask; 47510037SARM gem5 Developers DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 47610037SARM gem5 Developers miscRegName[misc_reg], val); 47710037SARM gem5 Developers return val; 47810037SARM gem5 Developers } 47910037SARM gem5 Developers case MISCREG_MPIDR: 48010037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 48110037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 48210037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 48310037SARM gem5 Developers return getMPIDR(system, tc); 48410037SARM gem5 Developers } else { 48510037SARM gem5 Developers return readMiscReg(MISCREG_VMPIDR, tc); 48610037SARM gem5 Developers } 48710037SARM gem5 Developers break; 48810037SARM gem5 Developers case MISCREG_MPIDR_EL1: 48910037SARM gem5 Developers // @todo in the absence of v8 virtualization support just return MPIDR_EL1 49010037SARM gem5 Developers return getMPIDR(system, tc) & 0xffffffff; 49110037SARM gem5 Developers case MISCREG_VMPIDR: 49210037SARM gem5 Developers // top bit defined as RES1 49310037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 49410037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 49510037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 49610037SARM gem5 Developers case MISCREG_MIDR: 49710037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 4988284SAli.Saidi@ARM.com scr = readMiscRegNoEffect(MISCREG_SCR); 49910037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 50010037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 50110037SARM gem5 Developers } else { 50210037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_VPIDR); 5039050Schander.sudanthi@arm.com } 50410037SARM gem5 Developers break; 50510037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 50610037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 50710037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 50810037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 50910037SARM gem5 Developers case MISCREG_TCMTR: // No TCM's 51010037SARM gem5 Developers return 0; 51110037SARM gem5 Developers 51210037SARM gem5 Developers case MISCREG_CLIDR: 51310037SARM gem5 Developers warn_once("The clidr register always reports 0 caches.\n"); 51410037SARM gem5 Developers warn_once("clidr LoUIS field of 0b001 to match current " 51510037SARM gem5 Developers "ARM implementations.\n"); 51610037SARM gem5 Developers return 0x00200000; 51710037SARM gem5 Developers case MISCREG_CCSIDR: 51810037SARM gem5 Developers warn_once("The ccsidr register isn't implemented and " 51910037SARM gem5 Developers "always reads as 0.\n"); 52010037SARM gem5 Developers break; 52110037SARM gem5 Developers case MISCREG_CTR: // AArch32, ARMv7, top bit set 5229050Schander.sudanthi@arm.com case MISCREG_CTR_EL0: // AArch64 5238284SAli.Saidi@ARM.com { 52410037SARM gem5 Developers //all caches have the same line size in gem5 52510037SARM gem5 Developers //4 byte words in ARM 52610037SARM gem5 Developers unsigned lineSizeWords = 52710037SARM gem5 Developers tc->getSystemPtr()->cacheLineSize() / 4; 52810037SARM gem5 Developers unsigned log2LineSizeWords = 0; 52910037SARM gem5 Developers 53010037SARM gem5 Developers while (lineSizeWords >>= 1) { 5317405SAli.Saidi@ARM.com ++log2LineSizeWords; 5327731SAli.Saidi@ARM.com } 5338468Swade.walker@arm.com 5348468Swade.walker@arm.com CTR ctr = 0; 5358468Swade.walker@arm.com //log2 of minimun i-cache line size (words) 5367405SAli.Saidi@ARM.com ctr.iCacheLineSize = log2LineSizeWords; 5377731SAli.Saidi@ARM.com //b11 - gem5 uses pipt 5387405SAli.Saidi@ARM.com ctr.l1IndexPolicy = 0x3; 5397405SAli.Saidi@ARM.com //log2 of minimum d-cache line size (words) 5407583SAli.Saidi@arm.com ctr.dCacheLineSize = log2LineSizeWords; 5419130Satgutier@umich.edu //log2 of max reservation size (words) 5429130Satgutier@umich.edu ctr.erg = log2LineSizeWords; 5439130Satgutier@umich.edu //log2 of max writeback size (words) 5449130Satgutier@umich.edu ctr.cwg = log2LineSizeWords; 5459814Sandreas.hansson@arm.com //b100 - gem5 format is ARMv7 5469130Satgutier@umich.edu ctr.format = 0x4; 5479130Satgutier@umich.edu 5489130Satgutier@umich.edu return ctr; 5499130Satgutier@umich.edu } 5509130Satgutier@umich.edu case MISCREG_ACTLR: 5519130Satgutier@umich.edu warn("Not doing anything for miscreg ACTLR\n"); 5529130Satgutier@umich.edu break; 5539130Satgutier@umich.edu 5549130Satgutier@umich.edu case MISCREG_PMXEVTYPER_PMCCFILTR: 5559130Satgutier@umich.edu case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 5569130Satgutier@umich.edu case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 5579130Satgutier@umich.edu case MISCREG_PMCR ... MISCREG_PMOVSSET: 5589130Satgutier@umich.edu return pmu->readMiscReg(misc_reg); 5599130Satgutier@umich.edu 5609130Satgutier@umich.edu case MISCREG_CPSR_Q: 5619130Satgutier@umich.edu panic("shouldn't be reading this register seperately\n"); 5629130Satgutier@umich.edu case MISCREG_FPSCR_QC: 5639130Satgutier@umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 5649130Satgutier@umich.edu case MISCREG_FPSCR_EXC: 5659130Satgutier@umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 5669130Satgutier@umich.edu case MISCREG_FPSR: 5679130Satgutier@umich.edu { 5687583SAli.Saidi@arm.com const uint32_t ones = (uint32_t)(-1); 5697583SAli.Saidi@arm.com FPSCR fpscrMask = 0; 5707583SAli.Saidi@arm.com fpscrMask.ioc = ones; 57110461SAndreas.Sandberg@ARM.com fpscrMask.dzc = ones; 57210461SAndreas.Sandberg@ARM.com fpscrMask.ofc = ones; 57310461SAndreas.Sandberg@ARM.com fpscrMask.ufc = ones; 57410461SAndreas.Sandberg@ARM.com fpscrMask.ixc = ones; 57510461SAndreas.Sandberg@ARM.com fpscrMask.idc = ones; 57610461SAndreas.Sandberg@ARM.com fpscrMask.qc = ones; 57710461SAndreas.Sandberg@ARM.com fpscrMask.v = ones; 5788302SAli.Saidi@ARM.com fpscrMask.c = ones; 5798302SAli.Saidi@ARM.com fpscrMask.z = ones; 5807783SGiacomo.Gabrielli@arm.com fpscrMask.n = ones; 5817783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 5827783SGiacomo.Gabrielli@arm.com } 5837783SGiacomo.Gabrielli@arm.com case MISCREG_FPCR: 58410037SARM gem5 Developers { 58510037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 58610037SARM gem5 Developers FPSCR fpscrMask = 0; 58710037SARM gem5 Developers fpscrMask.len = ones; 58810037SARM gem5 Developers fpscrMask.stride = ones; 58910037SARM gem5 Developers fpscrMask.rMode = ones; 59010037SARM gem5 Developers fpscrMask.fz = ones; 59110037SARM gem5 Developers fpscrMask.dn = ones; 59210037SARM gem5 Developers fpscrMask.ahp = ones; 59310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 59410037SARM gem5 Developers } 59510037SARM gem5 Developers case MISCREG_NZCV: 59610037SARM gem5 Developers { 59710037SARM gem5 Developers CPSR cpsr = 0; 59810037SARM gem5 Developers cpsr.nz = tc->readCCReg(CCREG_NZ); 59910037SARM gem5 Developers cpsr.c = tc->readCCReg(CCREG_C); 60010037SARM gem5 Developers cpsr.v = tc->readCCReg(CCREG_V); 60110037SARM gem5 Developers return cpsr; 60210037SARM gem5 Developers } 60310037SARM gem5 Developers case MISCREG_DAIF: 60410037SARM gem5 Developers { 60510037SARM gem5 Developers CPSR cpsr = 0; 60610037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 60710037SARM gem5 Developers return cpsr; 60810037SARM gem5 Developers } 60910037SARM gem5 Developers case MISCREG_SP_EL0: 61010037SARM gem5 Developers { 61110037SARM gem5 Developers return tc->readIntReg(INTREG_SP0); 61210037SARM gem5 Developers } 61310037SARM gem5 Developers case MISCREG_SP_EL1: 61410037SARM gem5 Developers { 61510037SARM gem5 Developers return tc->readIntReg(INTREG_SP1); 61610037SARM gem5 Developers } 61710037SARM gem5 Developers case MISCREG_SP_EL2: 61810037SARM gem5 Developers { 61910037SARM gem5 Developers return tc->readIntReg(INTREG_SP2); 62010037SARM gem5 Developers } 62110037SARM gem5 Developers case MISCREG_SPSEL: 62210338SCurtis.Dunham@arm.com { 62310338SCurtis.Dunham@arm.com return miscRegs[MISCREG_CPSR] & 0x1; 62410338SCurtis.Dunham@arm.com } 62510037SARM gem5 Developers case MISCREG_CURRENTEL: 62610037SARM gem5 Developers { 62710037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0xc; 62810037SARM gem5 Developers } 62910037SARM gem5 Developers case MISCREG_L2CTLR: 63010037SARM gem5 Developers { 63110037SARM gem5 Developers // mostly unimplemented, just set NumCPUs field from sim and return 63210037SARM gem5 Developers L2CTLR l2ctlr = 0; 63310037SARM gem5 Developers // b00:1CPU to b11:4CPUs 63410037SARM gem5 Developers l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 63510037SARM gem5 Developers return l2ctlr; 63610037SARM gem5 Developers } 63710037SARM gem5 Developers case MISCREG_DBGDIDR: 63810037SARM gem5 Developers /* For now just implement the version number. 63910037SARM gem5 Developers * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 64010037SARM gem5 Developers */ 64110037SARM gem5 Developers return 0x5 << 16; 64210037SARM gem5 Developers case MISCREG_DBGDSCRint: 64310037SARM gem5 Developers return 0; 64410037SARM gem5 Developers case MISCREG_ISR: 64510037SARM gem5 Developers return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 64610037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR), 64710037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 64810037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR)); 64910037SARM gem5 Developers case MISCREG_ISR_EL1: 65010037SARM gem5 Developers return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 65110037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR_EL2), 65210037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 6538549Sdaniel.johnson@arm.com readMiscRegNoEffect(MISCREG_SCR_EL3)); 6548868SMatt.Horsnell@arm.com case MISCREG_DCZID_EL0: 6558868SMatt.Horsnell@arm.com return 0x04; // DC ZVA clear 64-byte chunks 6568868SMatt.Horsnell@arm.com case MISCREG_HCPTR: 6578868SMatt.Horsnell@arm.com { 6588868SMatt.Horsnell@arm.com MiscReg val = readMiscRegNoEffect(misc_reg); 6598868SMatt.Horsnell@arm.com // The trap bit associated with CP14 is defined as RAZ 6608868SMatt.Horsnell@arm.com val &= ~(1 << 14); 6618868SMatt.Horsnell@arm.com // If a CP bit in NSACR is 0 then the corresponding bit in 6628868SMatt.Horsnell@arm.com // HCPTR is RAO/WI 66310461SAndreas.Sandberg@ARM.com bool secure_lookup = haveSecurity && 6648868SMatt.Horsnell@arm.com inSecureState(readMiscRegNoEffect(MISCREG_SCR), 66510461SAndreas.Sandberg@ARM.com readMiscRegNoEffect(MISCREG_CPSR)); 66610037SARM gem5 Developers if (!secure_lookup) { 6678868SMatt.Horsnell@arm.com MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 66810037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 66911150Smitch.hayenga@arm.com } 67010037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 67110037SARM gem5 Developers val |= 0x33FF; 67210037SARM gem5 Developers return (val); 67310037SARM gem5 Developers } 67411150Smitch.hayenga@arm.com case MISCREG_HDFAR: // alias for secure DFAR 67510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 67610037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 67710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 67810037SARM gem5 Developers 67910037SARM gem5 Developers case MISCREG_ID_PFR0: 68010037SARM gem5 Developers // !ThumbEE | !Jazelle | Thumb | ARM 68110037SARM gem5 Developers return 0x00000031; 68210037SARM gem5 Developers case MISCREG_ID_PFR1: 68310037SARM gem5 Developers { // Timer | Virti | !M Profile | TrustZone | ARMv4 68410037SARM gem5 Developers bool haveTimer = (system->getGenericTimer() != NULL); 68510037SARM gem5 Developers return 0x00000001 68610037SARM gem5 Developers | (haveSecurity ? 0x00000010 : 0x0) 68710037SARM gem5 Developers | (haveVirtualization ? 0x00001000 : 0x0) 68810037SARM gem5 Developers | (haveTimer ? 0x00010000 : 0x0); 68910037SARM gem5 Developers } 69010037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 69110037SARM gem5 Developers return 0x0000000000000002 | // AArch{64,32} supported at EL0 69210037SARM gem5 Developers 0x0000000000000020 | // EL1 69310037SARM gem5 Developers (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 69410037SARM gem5 Developers (haveSecurity ? 0x0000000000002000 : 0) | // EL3 69510037SARM gem5 Developers (haveGICv3CPUInterface ? 0x0000000001000000 : 0); 69610037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 69710037SARM gem5 Developers return 0; // bits [63:0] RES0 (reserved for future use) 69810037SARM gem5 Developers 69910037SARM gem5 Developers // Generic Timer registers 70010037SARM gem5 Developers case MISCREG_CNTHV_CTL_EL2: 70110037SARM gem5 Developers case MISCREG_CNTHV_CVAL_EL2: 70210037SARM gem5 Developers case MISCREG_CNTHV_TVAL_EL2: 70310037SARM gem5 Developers case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 70410037SARM gem5 Developers case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 70510037SARM gem5 Developers case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 70610037SARM gem5 Developers case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 70710037SARM gem5 Developers return getGenericTimer(tc).readMiscReg(misc_reg); 70810037SARM gem5 Developers 70910037SARM gem5 Developers case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 71010037SARM gem5 Developers case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 71110037SARM gem5 Developers return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 71210037SARM gem5 Developers 71310037SARM gem5 Developers default: 71410037SARM gem5 Developers break; 71510037SARM gem5 Developers 71610037SARM gem5 Developers } 71710037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 71810037SARM gem5 Developers} 71910037SARM gem5 Developers 72010037SARM gem5 Developersvoid 72110037SARM gem5 DevelopersISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 72210037SARM gem5 Developers{ 72310037SARM gem5 Developers assert(misc_reg < NumMiscRegs); 72410037SARM gem5 Developers 72510037SARM gem5 Developers const auto ® = lookUpMiscReg[misc_reg]; // bit masks 72610037SARM gem5 Developers const auto &map = getMiscIndices(misc_reg); 72710037SARM gem5 Developers int lower = map.first, upper = map.second; 72810037SARM gem5 Developers 72910037SARM gem5 Developers auto v = (val & ~reg.wi()) | reg.rao(); 73010037SARM gem5 Developers if (upper > 0) { 73110844Sandreas.sandberg@arm.com miscRegs[lower] = bits(v, 31, 0); 73210037SARM gem5 Developers miscRegs[upper] = bits(v, 63, 32); 73310844Sandreas.sandberg@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 73410844Sandreas.sandberg@arm.com misc_reg, lower, upper, v); 73510844Sandreas.sandberg@arm.com } else { 73610844Sandreas.sandberg@arm.com miscRegs[lower] = v; 73710844Sandreas.sandberg@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 73810844Sandreas.sandberg@arm.com misc_reg, lower, v); 73910188Sgeoffrey.blake@arm.com } 74010037SARM gem5 Developers} 74110037SARM gem5 Developers 7427405SAli.Saidi@ARM.comvoid 7437405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 7447405SAli.Saidi@ARM.com{ 7457405SAli.Saidi@ARM.com 7467405SAli.Saidi@ARM.com MiscReg newVal = val; 7477405SAli.Saidi@ARM.com bool secure_lookup; 7487405SAli.Saidi@ARM.com SCR scr; 7497405SAli.Saidi@ARM.com 7507614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_CPSR) { 75110037SARM gem5 Developers updateRegMap(val); 75210037SARM gem5 Developers 7537614Sminkyu.jeong@arm.com 75410037SARM gem5 Developers CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 75510037SARM gem5 Developers int old_mode = old_cpsr.mode; 75610037SARM gem5 Developers CPSR cpsr = val; 75710037SARM gem5 Developers if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 75810037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 75910037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 76010037SARM gem5 Developers } 76110037SARM gem5 Developers 76210037SARM gem5 Developers DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 76310037SARM gem5 Developers miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 76410037SARM gem5 Developers PCState pc = tc->pcState(); 76510037SARM gem5 Developers pc.nextThumb(cpsr.t); 76610037SARM gem5 Developers pc.nextJazelle(cpsr.j); 76710037SARM gem5 Developers pc.illegalExec(cpsr.il == 1); 76810037SARM gem5 Developers 76910037SARM gem5 Developers // Follow slightly different semantics if a CheckerCPU object 77010037SARM gem5 Developers // is connected 77110037SARM gem5 Developers CheckerCPU *checker = tc->getCheckerCpuPtr(); 77210037SARM gem5 Developers if (checker) { 7737405SAli.Saidi@ARM.com tc->pcStateNoRecord(pc); 7747405SAli.Saidi@ARM.com } else { 7757405SAli.Saidi@ARM.com tc->pcState(pc); 7767405SAli.Saidi@ARM.com } 7777405SAli.Saidi@ARM.com } else { 7787749SAli.Saidi@ARM.com#ifndef NDEBUG 7797405SAli.Saidi@ARM.com if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 7808284SAli.Saidi@ARM.com if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 78110037SARM gem5 Developers warn("Unimplemented system register %s write with %#x.\n", 78210037SARM gem5 Developers miscRegName[misc_reg], val); 7838284SAli.Saidi@ARM.com else 7848284SAli.Saidi@ARM.com panic("Unimplemented system register %s write with %#x.\n", 78510037SARM gem5 Developers miscRegName[misc_reg], val); 78610037SARM gem5 Developers } 78710037SARM gem5 Developers#endif 7888284SAli.Saidi@ARM.com switch (unflattenMiscReg(misc_reg)) { 7897405SAli.Saidi@ARM.com case MISCREG_CPACR: 7907405SAli.Saidi@ARM.com { 7917749SAli.Saidi@ARM.com 7927749SAli.Saidi@ARM.com const uint32_t ones = (uint32_t)(-1); 7937749SAli.Saidi@ARM.com CPACR cpacrMask = 0; 7947749SAli.Saidi@ARM.com // Only cp10, cp11, and ase are implemented, nothing else should 7957405SAli.Saidi@ARM.com // be writable 7967749SAli.Saidi@ARM.com cpacrMask.cp10 = ones; 7977749SAli.Saidi@ARM.com cpacrMask.cp11 = ones; 7987749SAli.Saidi@ARM.com cpacrMask.asedis = ones; 7997749SAli.Saidi@ARM.com 8007749SAli.Saidi@ARM.com // Security Extensions may limit the writability of CPACR 8017614Sminkyu.jeong@arm.com if (haveSecurity) { 8027614Sminkyu.jeong@arm.com scr = readMiscRegNoEffect(MISCREG_SCR); 8037720Sgblack@eecs.umich.edu CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 8047720Sgblack@eecs.umich.edu if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 8057720Sgblack@eecs.umich.edu NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 8068887Sgeoffrey.blake@arm.com // NB: Skipping the full loop, here 8078887Sgeoffrey.blake@arm.com if (!nsacr.cp10) cpacrMask.cp10 = 0; 8088887Sgeoffrey.blake@arm.com if (!nsacr.cp11) cpacrMask.cp11 = 0; 8098887Sgeoffrey.blake@arm.com } 8108887Sgeoffrey.blake@arm.com } 8118887Sgeoffrey.blake@arm.com 8128887Sgeoffrey.blake@arm.com MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 8138887Sgeoffrey.blake@arm.com newVal &= cpacrMask; 8148887Sgeoffrey.blake@arm.com newVal |= old_val & ~cpacrMask; 8157408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 81610037SARM gem5 Developers miscRegName[misc_reg], newVal); 81710037SARM gem5 Developers } 81810037SARM gem5 Developers break; 81910037SARM gem5 Developers case MISCREG_CPTR_EL2: 82010037SARM gem5 Developers { 82110037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 82210037SARM gem5 Developers CPTR cptrMask = 0; 82310037SARM gem5 Developers cptrMask.tcpac = ones; 82410037SARM gem5 Developers cptrMask.tta = ones; 82510037SARM gem5 Developers cptrMask.tfp = ones; 82610037SARM gem5 Developers newVal &= cptrMask; 8277408Sgblack@eecs.umich.edu cptrMask = 0; 8287408Sgblack@eecs.umich.edu cptrMask.res1_13_12_el2 = ones; 8298206SWilliam.Wang@arm.com cptrMask.res1_9_0_el2 = ones; 8308206SWilliam.Wang@arm.com newVal |= cptrMask; 8318206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 8328206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 8338206SWilliam.Wang@arm.com } 8348206SWilliam.Wang@arm.com break; 8358206SWilliam.Wang@arm.com case MISCREG_CPTR_EL3: 8368206SWilliam.Wang@arm.com { 83710037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 83810037SARM gem5 Developers CPTR cptrMask = 0; 83910037SARM gem5 Developers cptrMask.tcpac = ones; 84010037SARM gem5 Developers cptrMask.tta = ones; 84110037SARM gem5 Developers cptrMask.tfp = ones; 84210037SARM gem5 Developers newVal &= cptrMask; 84310037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 84410037SARM gem5 Developers miscRegName[misc_reg], newVal); 84510037SARM gem5 Developers } 84610037SARM gem5 Developers break; 84710037SARM gem5 Developers case MISCREG_CSSELR: 84810037SARM gem5 Developers warn_once("The csselr register isn't implemented.\n"); 84910037SARM gem5 Developers return; 85010037SARM gem5 Developers 8518206SWilliam.Wang@arm.com case MISCREG_DC_ZVA_Xt: 85210037SARM gem5 Developers warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 85310037SARM gem5 Developers return; 85410037SARM gem5 Developers 85510037SARM gem5 Developers case MISCREG_FPSCR: 85610037SARM gem5 Developers { 85710037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 85810037SARM gem5 Developers FPSCR fpscrMask = 0; 85910037SARM gem5 Developers fpscrMask.ioc = ones; 86010037SARM gem5 Developers fpscrMask.dzc = ones; 86110037SARM gem5 Developers fpscrMask.ofc = ones; 86210037SARM gem5 Developers fpscrMask.ufc = ones; 86310037SARM gem5 Developers fpscrMask.ixc = ones; 86410037SARM gem5 Developers fpscrMask.idc = ones; 86510037SARM gem5 Developers fpscrMask.ioe = ones; 86610037SARM gem5 Developers fpscrMask.dze = ones; 86710037SARM gem5 Developers fpscrMask.ofe = ones; 86810037SARM gem5 Developers fpscrMask.ufe = ones; 86910037SARM gem5 Developers fpscrMask.ixe = ones; 87010037SARM gem5 Developers fpscrMask.ide = ones; 87110037SARM gem5 Developers fpscrMask.len = ones; 87210037SARM gem5 Developers fpscrMask.stride = ones; 87310037SARM gem5 Developers fpscrMask.rMode = ones; 87410037SARM gem5 Developers fpscrMask.fz = ones; 87510037SARM gem5 Developers fpscrMask.dn = ones; 87610037SARM gem5 Developers fpscrMask.ahp = ones; 87710037SARM gem5 Developers fpscrMask.qc = ones; 87810037SARM gem5 Developers fpscrMask.v = ones; 87910037SARM gem5 Developers fpscrMask.c = ones; 88010037SARM gem5 Developers fpscrMask.z = ones; 88110037SARM gem5 Developers fpscrMask.n = ones; 88210037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 88310037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 88410037SARM gem5 Developers ~(uint32_t)fpscrMask); 88510037SARM gem5 Developers tc->getDecoderPtr()->setContext(newVal); 88610037SARM gem5 Developers } 88710037SARM gem5 Developers break; 88810037SARM gem5 Developers case MISCREG_FPSR: 88910037SARM gem5 Developers { 89010037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 89110037SARM gem5 Developers FPSCR fpscrMask = 0; 8928206SWilliam.Wang@arm.com fpscrMask.ioc = ones; 8938206SWilliam.Wang@arm.com fpscrMask.dzc = ones; 8947408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 8957408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 8967408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 8977731SAli.Saidi@ARM.com fpscrMask.idc = ones; 8988206SWilliam.Wang@arm.com fpscrMask.qc = ones; 89910037SARM gem5 Developers fpscrMask.v = ones; 90010037SARM gem5 Developers fpscrMask.c = ones; 90110037SARM gem5 Developers fpscrMask.z = ones; 90210037SARM gem5 Developers fpscrMask.n = ones; 90310037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 9047408Sgblack@eecs.umich.edu (readMiscRegNoEffect(MISCREG_FPSCR) & 9057408Sgblack@eecs.umich.edu ~(uint32_t)fpscrMask); 9067408Sgblack@eecs.umich.edu misc_reg = MISCREG_FPSCR; 9077408Sgblack@eecs.umich.edu } 9087408Sgblack@eecs.umich.edu break; 9097408Sgblack@eecs.umich.edu case MISCREG_FPCR: 9107408Sgblack@eecs.umich.edu { 9117408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 9127408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 9137408Sgblack@eecs.umich.edu fpscrMask.len = ones; 91410037SARM gem5 Developers fpscrMask.stride = ones; 91510037SARM gem5 Developers fpscrMask.rMode = ones; 91610037SARM gem5 Developers fpscrMask.fz = ones; 91710037SARM gem5 Developers fpscrMask.dn = ones; 91810037SARM gem5 Developers fpscrMask.ahp = ones; 91910037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 9207408Sgblack@eecs.umich.edu (readMiscRegNoEffect(MISCREG_FPSCR) & 9217408Sgblack@eecs.umich.edu ~(uint32_t)fpscrMask); 9227408Sgblack@eecs.umich.edu misc_reg = MISCREG_FPSCR; 9237408Sgblack@eecs.umich.edu } 9247408Sgblack@eecs.umich.edu break; 9257408Sgblack@eecs.umich.edu case MISCREG_CPSR_Q: 9267408Sgblack@eecs.umich.edu { 9277408Sgblack@eecs.umich.edu assert(!(newVal & ~CpsrMaskQ)); 9287408Sgblack@eecs.umich.edu newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 9297408Sgblack@eecs.umich.edu misc_reg = MISCREG_CPSR; 9307408Sgblack@eecs.umich.edu } 9317408Sgblack@eecs.umich.edu break; 93210037SARM gem5 Developers case MISCREG_FPSCR_QC: 93310037SARM gem5 Developers { 9349377Sgblack@eecs.umich.edu newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 9357408Sgblack@eecs.umich.edu (newVal & FpscrQcMask); 9367408Sgblack@eecs.umich.edu misc_reg = MISCREG_FPSCR; 93710037SARM gem5 Developers } 93810037SARM gem5 Developers break; 93910037SARM gem5 Developers case MISCREG_FPSCR_EXC: 94010037SARM gem5 Developers { 94110037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 94210037SARM gem5 Developers (newVal & FpscrExcMask); 94310037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 94410037SARM gem5 Developers } 94510037SARM gem5 Developers break; 94610037SARM gem5 Developers case MISCREG_FPEXC: 94710037SARM gem5 Developers { 94810037SARM gem5 Developers // vfpv3 architecture, section B.6.1 of DDI04068 94910037SARM gem5 Developers // bit 29 - valid only if fpexc[31] is 0 95010037SARM gem5 Developers const uint32_t fpexcMask = 0x60000000; 95110037SARM gem5 Developers newVal = (newVal & fpexcMask) | 95210037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 95310037SARM gem5 Developers } 95410037SARM gem5 Developers break; 95510037SARM gem5 Developers case MISCREG_HCR: 95610037SARM gem5 Developers { 95710037SARM gem5 Developers if (!haveVirtualization) 95810037SARM gem5 Developers return; 95910037SARM gem5 Developers } 96010037SARM gem5 Developers break; 96110037SARM gem5 Developers case MISCREG_IFSR: 96210037SARM gem5 Developers { 96310037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.96 96410037SARM gem5 Developers const uint32_t ifsrMask = 96510037SARM gem5 Developers mask(31, 13) | mask(11, 11) | mask(8, 6); 96610037SARM gem5 Developers newVal = newVal & ~ifsrMask; 96710037SARM gem5 Developers } 96810037SARM gem5 Developers break; 96910037SARM gem5 Developers case MISCREG_DFSR: 97010037SARM gem5 Developers { 97110037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.52 97210037SARM gem5 Developers const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 97310037SARM gem5 Developers newVal = newVal & ~dfsrMask; 97410037SARM gem5 Developers } 97510037SARM gem5 Developers break; 97610037SARM gem5 Developers case MISCREG_AMAIR0: 97710037SARM gem5 Developers case MISCREG_AMAIR1: 97810037SARM gem5 Developers { 97910037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 9808302SAli.Saidi@ARM.com // Valid only with LPAE 9818302SAli.Saidi@ARM.com if (!haveLPAE) 9828302SAli.Saidi@ARM.com return; 98310037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 9848302SAli.Saidi@ARM.com } 9858302SAli.Saidi@ARM.com break; 9868302SAli.Saidi@ARM.com case MISCREG_SCR: 9877783SGiacomo.Gabrielli@arm.com getITBPtr(tc)->invalidateMiscReg(); 9887783SGiacomo.Gabrielli@arm.com getDTBPtr(tc)->invalidateMiscReg(); 98910037SARM gem5 Developers break; 99010037SARM gem5 Developers case MISCREG_SCTLR: 9917783SGiacomo.Gabrielli@arm.com { 9927783SGiacomo.Gabrielli@arm.com DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 9937783SGiacomo.Gabrielli@arm.com scr = readMiscRegNoEffect(MISCREG_SCR); 9947783SGiacomo.Gabrielli@arm.com 9957783SGiacomo.Gabrielli@arm.com MiscRegIndex sctlr_idx; 99610037SARM gem5 Developers if (haveSecurity && !highestELIs64 && !scr.ns) { 99710037SARM gem5 Developers sctlr_idx = MISCREG_SCTLR_S; 9987783SGiacomo.Gabrielli@arm.com } else { 9997783SGiacomo.Gabrielli@arm.com sctlr_idx = MISCREG_SCTLR_NS; 10007783SGiacomo.Gabrielli@arm.com } 10017408Sgblack@eecs.umich.edu 10027408Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[sctlr_idx]; 10038206SWilliam.Wang@arm.com SCTLR new_sctlr = newVal; 10048206SWilliam.Wang@arm.com new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 10057408Sgblack@eecs.umich.edu miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 10067408Sgblack@eecs.umich.edu getITBPtr(tc)->invalidateMiscReg(); 100710037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 10087408Sgblack@eecs.umich.edu } 10097408Sgblack@eecs.umich.edu case MISCREG_MIDR: 101010037SARM gem5 Developers case MISCREG_ID_PFR0: 101110037SARM gem5 Developers case MISCREG_ID_PFR1: 101210037SARM gem5 Developers case MISCREG_ID_DFR0: 101310037SARM gem5 Developers case MISCREG_ID_MMFR0: 101410037SARM gem5 Developers case MISCREG_ID_MMFR1: 101510037SARM gem5 Developers case MISCREG_ID_MMFR2: 101610037SARM gem5 Developers case MISCREG_ID_MMFR3: 101710037SARM gem5 Developers case MISCREG_ID_ISAR0: 101810037SARM gem5 Developers case MISCREG_ID_ISAR1: 101910037SARM gem5 Developers case MISCREG_ID_ISAR2: 102010037SARM gem5 Developers case MISCREG_ID_ISAR3: 102110037SARM gem5 Developers case MISCREG_ID_ISAR4: 102210037SARM gem5 Developers case MISCREG_ID_ISAR5: 102310037SARM gem5 Developers 102410037SARM gem5 Developers case MISCREG_MPIDR: 102510037SARM gem5 Developers case MISCREG_FPSID: 102610037SARM gem5 Developers case MISCREG_TLBTR: 102710037SARM gem5 Developers case MISCREG_MVFR0: 102810037SARM gem5 Developers case MISCREG_MVFR1: 102910037SARM gem5 Developers 103010037SARM gem5 Developers case MISCREG_ID_AA64AFR0_EL1: 103110037SARM gem5 Developers case MISCREG_ID_AA64AFR1_EL1: 103210037SARM gem5 Developers case MISCREG_ID_AA64DFR0_EL1: 103310037SARM gem5 Developers case MISCREG_ID_AA64DFR1_EL1: 103410037SARM gem5 Developers case MISCREG_ID_AA64ISAR0_EL1: 103510037SARM gem5 Developers case MISCREG_ID_AA64ISAR1_EL1: 103610037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 103710037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 103810037SARM gem5 Developers case MISCREG_ID_AA64MMFR2_EL1: 103910037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 104010037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 104110037SARM gem5 Developers // ID registers are constants. 104210037SARM gem5 Developers return; 104310037SARM gem5 Developers 104410037SARM gem5 Developers // TLB Invalidate All 10457408Sgblack@eecs.umich.edu case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 10467408Sgblack@eecs.umich.edu { 10477408Sgblack@eecs.umich.edu assert32(tc); 104810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 104910037SARM gem5 Developers 105010037SARM gem5 Developers TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 105110037SARM gem5 Developers tlbiOp(tc); 105210037SARM gem5 Developers return; 105310037SARM gem5 Developers } 105410037SARM gem5 Developers // TLB Invalidate All, Inner Shareable 105510037SARM gem5 Developers case MISCREG_TLBIALLIS: 105610037SARM gem5 Developers { 105710037SARM gem5 Developers assert32(tc); 105810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 105910037SARM gem5 Developers 106010037SARM gem5 Developers TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 10617408Sgblack@eecs.umich.edu tlbiOp.broadcast(tc); 106210037SARM gem5 Developers return; 106310037SARM gem5 Developers } 10647749SAli.Saidi@ARM.com // Instruction TLB Invalidate All 10657749SAli.Saidi@ARM.com case MISCREG_ITLBIALL: 10667408Sgblack@eecs.umich.edu { 10679385SAndreas.Sandberg@arm.com assert32(tc); 10689385SAndreas.Sandberg@arm.com scr = readMiscReg(MISCREG_SCR, tc); 10699385SAndreas.Sandberg@arm.com 107010461SAndreas.Sandberg@ARM.com ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 10719385SAndreas.Sandberg@arm.com tlbiOp(tc); 10729385SAndreas.Sandberg@arm.com return; 10739385SAndreas.Sandberg@arm.com } 10749385SAndreas.Sandberg@arm.com // Data TLB Invalidate All 10759385SAndreas.Sandberg@arm.com case MISCREG_DTLBIALL: 10769385SAndreas.Sandberg@arm.com { 10779385SAndreas.Sandberg@arm.com assert32(tc); 10789385SAndreas.Sandberg@arm.com scr = readMiscReg(MISCREG_SCR, tc); 10799385SAndreas.Sandberg@arm.com 10809385SAndreas.Sandberg@arm.com DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 10819385SAndreas.Sandberg@arm.com tlbiOp(tc); 10829385SAndreas.Sandberg@arm.com return; 10839385SAndreas.Sandberg@arm.com } 10847408Sgblack@eecs.umich.edu // TLB Invalidate by VA 10857408Sgblack@eecs.umich.edu // mcr tlbimval(is) is invalidating all matching entries 10867408Sgblack@eecs.umich.edu // regardless of the level of lookup, since in gem5 we cache 108710037SARM gem5 Developers // in the tlb the last level of lookup only. 108810037SARM gem5 Developers case MISCREG_TLBIMVA: 108910037SARM gem5 Developers case MISCREG_TLBIMVAL: 109010037SARM gem5 Developers { 109110037SARM gem5 Developers assert32(tc); 109210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 109310037SARM gem5 Developers 109410037SARM gem5 Developers TLBIMVA tlbiOp(EL1, 109510037SARM gem5 Developers haveSecurity && !scr.ns, 109610037SARM gem5 Developers mbits(newVal, 31, 12), 109710037SARM gem5 Developers bits(newVal, 7,0)); 10989385SAndreas.Sandberg@arm.com 10997408Sgblack@eecs.umich.edu tlbiOp(tc); 11009385SAndreas.Sandberg@arm.com return; 110110037SARM gem5 Developers } 11027408Sgblack@eecs.umich.edu // TLB Invalidate by VA, Inner Shareable 110310037SARM gem5 Developers case MISCREG_TLBIMVAIS: 110410037SARM gem5 Developers case MISCREG_TLBIMVALIS: 110510037SARM gem5 Developers { 110610037SARM gem5 Developers assert32(tc); 110710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 11088284SAli.Saidi@ARM.com 11098284SAli.Saidi@ARM.com TLBIMVA tlbiOp(EL1, 11108284SAli.Saidi@ARM.com haveSecurity && !scr.ns, 11118284SAli.Saidi@ARM.com mbits(newVal, 31, 12), 111210037SARM gem5 Developers bits(newVal, 7,0)); 111310037SARM gem5 Developers 11148887Sgeoffrey.blake@arm.com tlbiOp.broadcast(tc); 11158887Sgeoffrey.blake@arm.com return; 11168887Sgeoffrey.blake@arm.com } 11178733Sgeoffrey.blake@arm.com // TLB Invalidate by ASID match 111810037SARM gem5 Developers case MISCREG_TLBIASID: 111910037SARM gem5 Developers { 112010037SARM gem5 Developers assert32(tc); 112110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 11228733Sgeoffrey.blake@arm.com 11238284SAli.Saidi@ARM.com TLBIASID tlbiOp(EL1, 11247408Sgblack@eecs.umich.edu haveSecurity && !scr.ns, 112510037SARM gem5 Developers bits(newVal, 7,0)); 11267408Sgblack@eecs.umich.edu 112710037SARM gem5 Developers tlbiOp(tc); 112810037SARM gem5 Developers return; 112910037SARM gem5 Developers } 113010037SARM gem5 Developers // TLB Invalidate by ASID match, Inner Shareable 113110037SARM gem5 Developers case MISCREG_TLBIASIDIS: 11327408Sgblack@eecs.umich.edu { 113310037SARM gem5 Developers assert32(tc); 11347408Sgblack@eecs.umich.edu scr = readMiscReg(MISCREG_SCR, tc); 113510037SARM gem5 Developers 113610037SARM gem5 Developers TLBIASID tlbiOp(EL1, 113710037SARM gem5 Developers haveSecurity && !scr.ns, 113810037SARM gem5 Developers bits(newVal, 7,0)); 113910037SARM gem5 Developers 11407408Sgblack@eecs.umich.edu tlbiOp.broadcast(tc); 114110037SARM gem5 Developers return; 11427408Sgblack@eecs.umich.edu } 11437408Sgblack@eecs.umich.edu // mcr tlbimvaal(is) is invalidating all matching entries 114410037SARM gem5 Developers // regardless of the level of lookup, since in gem5 we cache 114510037SARM gem5 Developers // in the tlb the last level of lookup only. 114610037SARM gem5 Developers // TLB Invalidate by VA, All ASID 114710037SARM gem5 Developers case MISCREG_TLBIMVAA: 11488284SAli.Saidi@ARM.com case MISCREG_TLBIMVAAL: 11498284SAli.Saidi@ARM.com { 11508284SAli.Saidi@ARM.com assert32(tc); 11518284SAli.Saidi@ARM.com scr = readMiscReg(MISCREG_SCR, tc); 11528284SAli.Saidi@ARM.com 115310037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 115410037SARM gem5 Developers mbits(newVal, 31,12), false); 11558284SAli.Saidi@ARM.com 115610037SARM gem5 Developers tlbiOp(tc); 115710037SARM gem5 Developers return; 11588887Sgeoffrey.blake@arm.com } 11598887Sgeoffrey.blake@arm.com // TLB Invalidate by VA, All ASID, Inner Shareable 11608733Sgeoffrey.blake@arm.com case MISCREG_TLBIMVAAIS: 11618733Sgeoffrey.blake@arm.com case MISCREG_TLBIMVAALIS: 116210037SARM gem5 Developers { 11638733Sgeoffrey.blake@arm.com assert32(tc); 116410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 11658733Sgeoffrey.blake@arm.com 11668284SAli.Saidi@ARM.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 11677408Sgblack@eecs.umich.edu mbits(newVal, 31,12), false); 116810037SARM gem5 Developers 11697408Sgblack@eecs.umich.edu tlbiOp.broadcast(tc); 11707408Sgblack@eecs.umich.edu return; 117110037SARM gem5 Developers } 117210037SARM gem5 Developers // mcr tlbimvalh(is) is invalidating all matching entries 117310037SARM gem5 Developers // regardless of the level of lookup, since in gem5 we cache 117410037SARM gem5 Developers // in the tlb the last level of lookup only. 11758284SAli.Saidi@ARM.com // TLB Invalidate by VA, Hyp mode 11768284SAli.Saidi@ARM.com case MISCREG_TLBIMVAH: 11778284SAli.Saidi@ARM.com case MISCREG_TLBIMVALH: 11788284SAli.Saidi@ARM.com { 117910037SARM gem5 Developers assert32(tc); 118010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 118110037SARM gem5 Developers 118210037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 11838887Sgeoffrey.blake@arm.com mbits(newVal, 31,12), true); 11848733Sgeoffrey.blake@arm.com 118510037SARM gem5 Developers tlbiOp(tc); 118610037SARM gem5 Developers return; 118710037SARM gem5 Developers } 118810037SARM gem5 Developers // TLB Invalidate by VA, Hyp mode, Inner Shareable 11898733Sgeoffrey.blake@arm.com case MISCREG_TLBIMVAHIS: 11908284SAli.Saidi@ARM.com case MISCREG_TLBIMVALHIS: 11917408Sgblack@eecs.umich.edu { 119210037SARM gem5 Developers assert32(tc); 11937408Sgblack@eecs.umich.edu scr = readMiscReg(MISCREG_SCR, tc); 11947408Sgblack@eecs.umich.edu 119510037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 119610037SARM gem5 Developers mbits(newVal, 31,12), true); 119710037SARM gem5 Developers 119810037SARM gem5 Developers tlbiOp.broadcast(tc); 119910037SARM gem5 Developers return; 120010037SARM gem5 Developers } 120110037SARM gem5 Developers // mcr tlbiipas2l(is) is invalidating all matching entries 120210037SARM gem5 Developers // regardless of the level of lookup, since in gem5 we cache 120310037SARM gem5 Developers // in the tlb the last level of lookup only. 120410037SARM gem5 Developers // TLB Invalidate by Intermediate Physical Address, Stage 2 120510037SARM gem5 Developers case MISCREG_TLBIIPAS2: 120610037SARM gem5 Developers case MISCREG_TLBIIPAS2L: 120710037SARM gem5 Developers { 120810037SARM gem5 Developers assert32(tc); 120910037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 121010037SARM gem5 Developers 121110037SARM gem5 Developers TLBIIPA tlbiOp(EL1, 121210037SARM gem5 Developers haveSecurity && !scr.ns, 121310037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 121410037SARM gem5 Developers 121510037SARM gem5 Developers tlbiOp(tc); 121610037SARM gem5 Developers return; 121710037SARM gem5 Developers } 121810037SARM gem5 Developers // TLB Invalidate by Intermediate Physical Address, Stage 2, 121910037SARM gem5 Developers // Inner Shareable 122010037SARM gem5 Developers case MISCREG_TLBIIPAS2IS: 122110037SARM gem5 Developers case MISCREG_TLBIIPAS2LIS: 122210037SARM gem5 Developers { 122310037SARM gem5 Developers assert32(tc); 122410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 122510037SARM gem5 Developers 122610037SARM gem5 Developers TLBIIPA tlbiOp(EL1, 122710037SARM gem5 Developers haveSecurity && !scr.ns, 122810037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 122910037SARM gem5 Developers 123010037SARM gem5 Developers tlbiOp.broadcast(tc); 123110037SARM gem5 Developers return; 123210037SARM gem5 Developers } 123310037SARM gem5 Developers // Instruction TLB Invalidate by VA 123410037SARM gem5 Developers case MISCREG_ITLBIMVA: 123510037SARM gem5 Developers { 123610037SARM gem5 Developers assert32(tc); 123710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 123810037SARM gem5 Developers 123910037SARM gem5 Developers ITLBIMVA tlbiOp(EL1, 124010037SARM gem5 Developers haveSecurity && !scr.ns, 124110037SARM gem5 Developers mbits(newVal, 31, 12), 124210037SARM gem5 Developers bits(newVal, 7,0)); 124310037SARM gem5 Developers 124410037SARM gem5 Developers tlbiOp(tc); 124510037SARM gem5 Developers return; 124610037SARM gem5 Developers } 124710037SARM gem5 Developers // Data TLB Invalidate by VA 124810037SARM gem5 Developers case MISCREG_DTLBIMVA: 124910037SARM gem5 Developers { 125010037SARM gem5 Developers assert32(tc); 125110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 125210037SARM gem5 Developers 125310037SARM gem5 Developers DTLBIMVA tlbiOp(EL1, 125410037SARM gem5 Developers haveSecurity && !scr.ns, 125510037SARM gem5 Developers mbits(newVal, 31, 12), 125610037SARM gem5 Developers bits(newVal, 7,0)); 125710037SARM gem5 Developers 125810037SARM gem5 Developers tlbiOp(tc); 125910037SARM gem5 Developers return; 126010037SARM gem5 Developers } 126110037SARM gem5 Developers // Instruction TLB Invalidate by ASID match 126210037SARM gem5 Developers case MISCREG_ITLBIASID: 126310037SARM gem5 Developers { 126410037SARM gem5 Developers assert32(tc); 126510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 126610037SARM gem5 Developers 126710037SARM gem5 Developers ITLBIASID tlbiOp(EL1, 126810037SARM gem5 Developers haveSecurity && !scr.ns, 126910037SARM gem5 Developers bits(newVal, 7,0)); 127010037SARM gem5 Developers 127110037SARM gem5 Developers tlbiOp(tc); 127210037SARM gem5 Developers return; 127310037SARM gem5 Developers } 127410037SARM gem5 Developers // Data TLB Invalidate by ASID match 127510037SARM gem5 Developers case MISCREG_DTLBIASID: 127610037SARM gem5 Developers { 127710037SARM gem5 Developers assert32(tc); 127810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 127910037SARM gem5 Developers 128010037SARM gem5 Developers DTLBIASID tlbiOp(EL1, 128110037SARM gem5 Developers haveSecurity && !scr.ns, 128210037SARM gem5 Developers bits(newVal, 7,0)); 128310037SARM gem5 Developers 128410037SARM gem5 Developers tlbiOp(tc); 128510037SARM gem5 Developers return; 128610037SARM gem5 Developers } 128710037SARM gem5 Developers // TLB Invalidate All, Non-Secure Non-Hyp 128810037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 128910037SARM gem5 Developers { 129010037SARM gem5 Developers assert32(tc); 129110037SARM gem5 Developers 129210037SARM gem5 Developers TLBIALLN tlbiOp(EL1, false); 129310037SARM gem5 Developers tlbiOp(tc); 129410037SARM gem5 Developers return; 129510037SARM gem5 Developers } 129610037SARM gem5 Developers // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 129710037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 129810037SARM gem5 Developers { 129910037SARM gem5 Developers assert32(tc); 130010037SARM gem5 Developers 130110037SARM gem5 Developers TLBIALLN tlbiOp(EL1, false); 130210037SARM gem5 Developers tlbiOp.broadcast(tc); 130310037SARM gem5 Developers return; 130410037SARM gem5 Developers } 130510037SARM gem5 Developers // TLB Invalidate All, Hyp mode 130610037SARM gem5 Developers case MISCREG_TLBIALLH: 130710037SARM gem5 Developers { 130810037SARM gem5 Developers assert32(tc); 130910037SARM gem5 Developers 131010037SARM gem5 Developers TLBIALLN tlbiOp(EL1, true); 131110037SARM gem5 Developers tlbiOp(tc); 131210037SARM gem5 Developers return; 131310037SARM gem5 Developers } 131410037SARM gem5 Developers // TLB Invalidate All, Hyp mode, Inner Shareable 131510037SARM gem5 Developers case MISCREG_TLBIALLHIS: 131610037SARM gem5 Developers { 131710037SARM gem5 Developers assert32(tc); 131810037SARM gem5 Developers 131910037SARM gem5 Developers TLBIALLN tlbiOp(EL1, true); 132010037SARM gem5 Developers tlbiOp.broadcast(tc); 132110037SARM gem5 Developers return; 132210037SARM gem5 Developers } 132310037SARM gem5 Developers // AArch64 TLB Invalidate All, EL3 132410037SARM gem5 Developers case MISCREG_TLBI_ALLE3: 132510037SARM gem5 Developers { 132610037SARM gem5 Developers assert64(tc); 132710037SARM gem5 Developers 132810037SARM gem5 Developers TLBIALL tlbiOp(EL3, true); 132910037SARM gem5 Developers tlbiOp(tc); 133010037SARM gem5 Developers return; 133110037SARM gem5 Developers } 133210037SARM gem5 Developers // AArch64 TLB Invalidate All, EL3, Inner Shareable 133310037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 133410037SARM gem5 Developers { 133510037SARM gem5 Developers assert64(tc); 133610037SARM gem5 Developers 133710037SARM gem5 Developers TLBIALL tlbiOp(EL3, true); 133810037SARM gem5 Developers tlbiOp.broadcast(tc); 133910037SARM gem5 Developers return; 13408284SAli.Saidi@ARM.com } 13418284SAli.Saidi@ARM.com // AArch64 TLB Invalidate All, EL2, Inner Shareable 13428284SAli.Saidi@ARM.com case MISCREG_TLBI_ALLE2: 13438284SAli.Saidi@ARM.com case MISCREG_TLBI_ALLE2IS: 134410037SARM gem5 Developers { 134510709SAndreas.Sandberg@ARM.com assert64(tc); 134610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 134710037SARM gem5 Developers 134810037SARM gem5 Developers TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); 134910037SARM gem5 Developers tlbiOp(tc); 135010037SARM gem5 Developers return; 135110037SARM gem5 Developers } 135210037SARM gem5 Developers // AArch64 TLB Invalidate All, EL1 135310037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 135410037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 135510037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 135610037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 135710037SARM gem5 Developers { 135810037SARM gem5 Developers assert64(tc); 135910037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 136010037SARM gem5 Developers 136110037SARM gem5 Developers TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 136210037SARM gem5 Developers tlbiOp(tc); 136310037SARM gem5 Developers return; 136410037SARM gem5 Developers } 136510037SARM gem5 Developers // AArch64 TLB Invalidate All, EL1, Inner Shareable 136610037SARM gem5 Developers case MISCREG_TLBI_ALLE1IS: 136710037SARM gem5 Developers case MISCREG_TLBI_VMALLE1IS: 136810037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1IS: 136910037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 137010037SARM gem5 Developers { 137110037SARM gem5 Developers assert64(tc); 137210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 137310037SARM gem5 Developers 137410037SARM gem5 Developers TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 137510037SARM gem5 Developers tlbiOp.broadcast(tc); 137610037SARM gem5 Developers return; 137710037SARM gem5 Developers } 137810037SARM gem5 Developers // VAEx(IS) and VALEx(IS) are the same because TLBs 137910037SARM gem5 Developers // only store entries 13808887Sgeoffrey.blake@arm.com // from the last level of translation table walks 13818887Sgeoffrey.blake@arm.com // @todo: handle VMID to enable Virtualization 13828733Sgeoffrey.blake@arm.com // AArch64 TLB Invalidate by VA, EL3 138310037SARM gem5 Developers case MISCREG_TLBI_VAE3_Xt: 138410037SARM gem5 Developers case MISCREG_TLBI_VALE3_Xt: 138510037SARM gem5 Developers { 138610037SARM gem5 Developers assert64(tc); 13878733Sgeoffrey.blake@arm.com 13888284SAli.Saidi@ARM.com TLBIMVA tlbiOp(EL3, true, 13897408Sgblack@eecs.umich.edu static_cast<Addr>(bits(newVal, 43, 0)) << 12, 139010037SARM gem5 Developers 0xbeef); 139110037SARM gem5 Developers tlbiOp(tc); 139210037SARM gem5 Developers return; 139310037SARM gem5 Developers } 139410037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 139510037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 139611584SDylan.Johnson@ARM.com case MISCREG_TLBI_VALE3IS_Xt: 139711584SDylan.Johnson@ARM.com { 139811584SDylan.Johnson@ARM.com assert64(tc); 139911584SDylan.Johnson@ARM.com 140011584SDylan.Johnson@ARM.com TLBIMVA tlbiOp(EL3, true, 140111584SDylan.Johnson@ARM.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 140211584SDylan.Johnson@ARM.com 0xbeef); 140311584SDylan.Johnson@ARM.com 140411584SDylan.Johnson@ARM.com tlbiOp.broadcast(tc); 140511584SDylan.Johnson@ARM.com return; 140611584SDylan.Johnson@ARM.com } 140711584SDylan.Johnson@ARM.com // AArch64 TLB Invalidate by VA, EL2 140811584SDylan.Johnson@ARM.com case MISCREG_TLBI_VAE2_Xt: 140911584SDylan.Johnson@ARM.com case MISCREG_TLBI_VALE2_Xt: 141011584SDylan.Johnson@ARM.com { 141111584SDylan.Johnson@ARM.com assert64(tc); 141211584SDylan.Johnson@ARM.com scr = readMiscReg(MISCREG_SCR, tc); 141311584SDylan.Johnson@ARM.com 141411584SDylan.Johnson@ARM.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 141511584SDylan.Johnson@ARM.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 141611584SDylan.Johnson@ARM.com 0xbeef); 14177405SAli.Saidi@ARM.com tlbiOp(tc); 14187583SAli.Saidi@arm.com return; 14197583SAli.Saidi@arm.com } 14207583SAli.Saidi@arm.com // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 142110461SAndreas.Sandberg@ARM.com case MISCREG_TLBI_VAE2IS_Xt: 142210461SAndreas.Sandberg@ARM.com case MISCREG_TLBI_VALE2IS_Xt: 142310461SAndreas.Sandberg@ARM.com { 142410461SAndreas.Sandberg@ARM.com assert64(tc); 142510461SAndreas.Sandberg@ARM.com scr = readMiscReg(MISCREG_SCR, tc); 142610461SAndreas.Sandberg@ARM.com 14277583SAli.Saidi@arm.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 142810461SAndreas.Sandberg@ARM.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 142910461SAndreas.Sandberg@ARM.com 0xbeef); 143010037SARM gem5 Developers 143110037SARM gem5 Developers tlbiOp.broadcast(tc); 143210037SARM gem5 Developers return; 143310037SARM gem5 Developers } 143410037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL1 143510037SARM gem5 Developers case MISCREG_TLBI_VAE1_Xt: 143610037SARM gem5 Developers case MISCREG_TLBI_VALE1_Xt: 143710037SARM gem5 Developers { 143810037SARM gem5 Developers assert64(tc); 143910037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 144010037SARM gem5 Developers auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 144110037SARM gem5 Developers bits(newVal, 55, 48); 144210037SARM gem5 Developers 144310037SARM gem5 Developers TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 144410037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 144510037SARM gem5 Developers asid); 144610037SARM gem5 Developers 144710037SARM gem5 Developers tlbiOp(tc); 144810037SARM gem5 Developers return; 144910037SARM gem5 Developers } 145010037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 145110037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 145210037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 145310037SARM gem5 Developers { 145410037SARM gem5 Developers assert64(tc); 145510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 145610037SARM gem5 Developers auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 145710037SARM gem5 Developers bits(newVal, 55, 48); 145810037SARM gem5 Developers 145910037SARM gem5 Developers TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 146010037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 146110037SARM gem5 Developers asid); 146210037SARM gem5 Developers 146310037SARM gem5 Developers tlbiOp.broadcast(tc); 146410037SARM gem5 Developers return; 146510037SARM gem5 Developers } 146610037SARM gem5 Developers // AArch64 TLB Invalidate by ASID, EL1 14677436Sdam.sunwoo@arm.com // @todo: handle VMID to enable Virtualization 146811608Snikos.nikoleris@arm.com case MISCREG_TLBI_ASIDE1_Xt: 146910037SARM gem5 Developers { 147010037SARM gem5 Developers assert64(tc); 14717436Sdam.sunwoo@arm.com scr = readMiscReg(MISCREG_SCR, tc); 14727436Sdam.sunwoo@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 147310037SARM gem5 Developers bits(newVal, 55, 48); 147410037SARM gem5 Developers 147510037SARM gem5 Developers TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 147610037SARM gem5 Developers tlbiOp(tc); 147710037SARM gem5 Developers return; 147810037SARM gem5 Developers } 147910037SARM gem5 Developers // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 148010037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 148110037SARM gem5 Developers { 148210037SARM gem5 Developers assert64(tc); 148310037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 148410037SARM gem5 Developers auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 148510037SARM gem5 Developers bits(newVal, 55, 48); 148610037SARM gem5 Developers 148710037SARM gem5 Developers TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 148810037SARM gem5 Developers tlbiOp.broadcast(tc); 148910037SARM gem5 Developers return; 149010037SARM gem5 Developers } 149110037SARM gem5 Developers // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 149210037SARM gem5 Developers // entries from the last level of translation table walks 149310037SARM gem5 Developers // AArch64 TLB Invalidate by VA, All ASID, EL1 149410037SARM gem5 Developers case MISCREG_TLBI_VAAE1_Xt: 149510037SARM gem5 Developers case MISCREG_TLBI_VAALE1_Xt: 149610037SARM gem5 Developers { 149710037SARM gem5 Developers assert64(tc); 149810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 149910037SARM gem5 Developers 150010037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 150110037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 150210037SARM gem5 Developers 150310037SARM gem5 Developers tlbiOp(tc); 150410037SARM gem5 Developers return; 150510037SARM gem5 Developers } 150610037SARM gem5 Developers // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 150710037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 150810037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 150910037SARM gem5 Developers { 151010037SARM gem5 Developers assert64(tc); 151110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 151210037SARM gem5 Developers 151310037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 151410037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 151510037SARM gem5 Developers 151610037SARM gem5 Developers tlbiOp.broadcast(tc); 151710037SARM gem5 Developers return; 151810037SARM gem5 Developers } 151910037SARM gem5 Developers // AArch64 TLB Invalidate by Intermediate Physical Address, 152010037SARM gem5 Developers // Stage 2, EL1 152110037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1_Xt: 152210037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1_Xt: 152310037SARM gem5 Developers { 152410037SARM gem5 Developers assert64(tc); 152510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 152610037SARM gem5 Developers 152710037SARM gem5 Developers TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 152810037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 152910037SARM gem5 Developers 153010037SARM gem5 Developers tlbiOp(tc); 15317436Sdam.sunwoo@arm.com return; 153210037SARM gem5 Developers } 153310037SARM gem5 Developers // AArch64 TLB Invalidate by Intermediate Physical Address, 153410037SARM gem5 Developers // Stage 2, EL1, Inner Shareable 153510037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1IS_Xt: 153610037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1IS_Xt: 153710037SARM gem5 Developers { 153810037SARM gem5 Developers assert64(tc); 153911560Sandreas.sandberg@arm.com scr = readMiscReg(MISCREG_SCR, tc); 154011435Smitch.hayenga@arm.com 154110653Sandreas.hansson@arm.com TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 154210037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 154310037SARM gem5 Developers 154410037SARM gem5 Developers tlbiOp.broadcast(tc); 154510037SARM gem5 Developers return; 15467436Sdam.sunwoo@arm.com } 154710653Sandreas.hansson@arm.com case MISCREG_ACTLR: 154810037SARM gem5 Developers warn("Not doing anything for write of miscreg ACTLR\n"); 154910037SARM gem5 Developers break; 155010037SARM gem5 Developers 155110037SARM gem5 Developers case MISCREG_PMXEVTYPER_PMCCFILTR: 155210037SARM gem5 Developers case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 155310037SARM gem5 Developers case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 155410037SARM gem5 Developers case MISCREG_PMCR ... MISCREG_PMOVSSET: 155510037SARM gem5 Developers pmu->setMiscReg(misc_reg, newVal); 15567436Sdam.sunwoo@arm.com break; 15577436Sdam.sunwoo@arm.com 155810037SARM gem5 Developers 155910037SARM gem5 Developers case MISCREG_HSTR: // TJDBX, now redifined to be RES0 156010037SARM gem5 Developers { 156110037SARM gem5 Developers HSTR hstrMask = 0; 156210037SARM gem5 Developers hstrMask.tjdbx = 1; 156310037SARM gem5 Developers newVal &= ~((uint32_t) hstrMask); 156410037SARM gem5 Developers break; 156510037SARM gem5 Developers } 156610037SARM gem5 Developers case MISCREG_HCPTR: 156710037SARM gem5 Developers { 156810037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 156910037SARM gem5 Developers // HCPTR is RAO/WI. Same applies to NSASEDIS 157010037SARM gem5 Developers secure_lookup = haveSecurity && 157110037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 157210037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 157310037SARM gem5 Developers if (!secure_lookup) { 157410037SARM gem5 Developers MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 157510037SARM gem5 Developers MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 157610037SARM gem5 Developers newVal = (newVal & ~mask) | (oldValue & mask); 157710037SARM gem5 Developers } 157810037SARM gem5 Developers break; 157910037SARM gem5 Developers } 15807436Sdam.sunwoo@arm.com case MISCREG_HDFAR: // alias for secure DFAR 158110037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 15827436Sdam.sunwoo@arm.com break; 15837436Sdam.sunwoo@arm.com case MISCREG_HIFAR: // alias for secure IFAR 158410037SARM gem5 Developers misc_reg = MISCREG_IFAR_S; 158510037SARM gem5 Developers break; 158610037SARM gem5 Developers case MISCREG_ATS1CPR: 158710037SARM gem5 Developers case MISCREG_ATS1CPW: 158810037SARM gem5 Developers case MISCREG_ATS1CUR: 158910037SARM gem5 Developers case MISCREG_ATS1CUW: 159010037SARM gem5 Developers case MISCREG_ATS12NSOPR: 159110037SARM gem5 Developers case MISCREG_ATS12NSOPW: 159210037SARM gem5 Developers case MISCREG_ATS12NSOUR: 159310037SARM gem5 Developers case MISCREG_ATS12NSOUW: 159410037SARM gem5 Developers case MISCREG_ATS1HR: 159510037SARM gem5 Developers case MISCREG_ATS1HW: 159610037SARM gem5 Developers { 159710037SARM gem5 Developers Request::Flags flags = 0; 159810037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 159910037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 160010037SARM gem5 Developers Fault fault; 160110037SARM gem5 Developers switch(misc_reg) { 160210037SARM gem5 Developers case MISCREG_ATS1CPR: 160310037SARM gem5 Developers flags = TLB::MustBeOne; 160410037SARM gem5 Developers tranType = TLB::S1CTran; 160510037SARM gem5 Developers mode = BaseTLB::Read; 160610037SARM gem5 Developers break; 160710037SARM gem5 Developers case MISCREG_ATS1CPW: 160810037SARM gem5 Developers flags = TLB::MustBeOne; 160910037SARM gem5 Developers tranType = TLB::S1CTran; 161010037SARM gem5 Developers mode = BaseTLB::Write; 161110037SARM gem5 Developers break; 161210037SARM gem5 Developers case MISCREG_ATS1CUR: 161310037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 161410037SARM gem5 Developers tranType = TLB::S1CTran; 161510037SARM gem5 Developers mode = BaseTLB::Read; 161610037SARM gem5 Developers break; 161710037SARM gem5 Developers case MISCREG_ATS1CUW: 161810037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 161910037SARM gem5 Developers tranType = TLB::S1CTran; 162010037SARM gem5 Developers mode = BaseTLB::Write; 162110037SARM gem5 Developers break; 162210037SARM gem5 Developers case MISCREG_ATS12NSOPR: 162310037SARM gem5 Developers if (!haveSecurity) 162410037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 162510037SARM gem5 Developers flags = TLB::MustBeOne; 162610037SARM gem5 Developers tranType = TLB::S1S2NsTran; 162710037SARM gem5 Developers mode = BaseTLB::Read; 162810037SARM gem5 Developers break; 162910508SAli.Saidi@ARM.com case MISCREG_ATS12NSOPW: 163010508SAli.Saidi@ARM.com if (!haveSecurity) 163110508SAli.Saidi@ARM.com panic("Security Extensions required for ATS12NSOPW"); 163210508SAli.Saidi@ARM.com flags = TLB::MustBeOne; 163310508SAli.Saidi@ARM.com tranType = TLB::S1S2NsTran; 163410508SAli.Saidi@ARM.com mode = BaseTLB::Write; 16357749SAli.Saidi@ARM.com break; 16367749SAli.Saidi@ARM.com case MISCREG_ATS12NSOUR: 16377749SAli.Saidi@ARM.com if (!haveSecurity) 163810037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 163910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 16407749SAli.Saidi@ARM.com tranType = TLB::S1S2NsTran; 164110037SARM gem5 Developers mode = BaseTLB::Read; 164210037SARM gem5 Developers break; 164311575SDylan.Johnson@ARM.com case MISCREG_ATS12NSOUW: 164410037SARM gem5 Developers if (!haveSecurity) 164510037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 164610037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 164710508SAli.Saidi@ARM.com tranType = TLB::S1S2NsTran; 164810508SAli.Saidi@ARM.com mode = BaseTLB::Write; 164911573SDylan.Johnson@ARM.com break; 165010037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 165110037SARM gem5 Developers flags = TLB::MustBeOne; 165210037SARM gem5 Developers tranType = TLB::HypMode; 165310037SARM gem5 Developers mode = BaseTLB::Read; 16547749SAli.Saidi@ARM.com break; 16557749SAli.Saidi@ARM.com case MISCREG_ATS1HW: 16567749SAli.Saidi@ARM.com flags = TLB::MustBeOne; 165710037SARM gem5 Developers tranType = TLB::HypMode; 165810037SARM gem5 Developers mode = BaseTLB::Write; 165910037SARM gem5 Developers break; 166010037SARM gem5 Developers } 166110338SCurtis.Dunham@arm.com // If we're in timing mode then doing the translation in 166210338SCurtis.Dunham@arm.com // functional mode then we're slightly distorting performance 166310338SCurtis.Dunham@arm.com // results obtained from simulations. The translation should be 166410037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 166510037SARM gem5 Developers // can't be an atomic translation because that causes problems 166610037SARM gem5 Developers // with unexpected atomic snoop requests. 166710037SARM gem5 Developers warn("Translating via %s in functional mode! Fix Me!\n", 166810037SARM gem5 Developers miscRegName[misc_reg]); 166910037SARM gem5 Developers 167010037SARM gem5 Developers auto req = std::make_shared<Request>( 167110037SARM gem5 Developers 0, val, 0, flags, Request::funcMasterId, 167210037SARM gem5 Developers tc->pcState().pc(), tc->contextId()); 167310037SARM gem5 Developers 167410037SARM gem5 Developers fault = getDTBPtr(tc)->translateFunctional( 167510037SARM gem5 Developers req, tc, mode, tranType); 167610037SARM gem5 Developers 167710037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 167810037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 167910037SARM gem5 Developers 168010037SARM gem5 Developers MiscReg newVal; 168110037SARM gem5 Developers if (fault == NoFault) { 168210037SARM gem5 Developers Addr paddr = req->getPaddr(); 168310037SARM gem5 Developers if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 168410037SARM gem5 Developers ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 168510037SARM gem5 Developers newVal = (paddr & mask(39, 12)) | 168610037SARM gem5 Developers (getDTBPtr(tc)->getAttr()); 168710037SARM gem5 Developers } else { 168810037SARM gem5 Developers newVal = (paddr & 0xfffff000) | 168910037SARM gem5 Developers (getDTBPtr(tc)->getAttr()); 169010037SARM gem5 Developers } 169110037SARM gem5 Developers DPRINTF(MiscRegs, 169210037SARM gem5 Developers "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 169310037SARM gem5 Developers val, newVal); 169410037SARM gem5 Developers } else { 169510037SARM gem5 Developers ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 169610037SARM gem5 Developers armFault->update(tc); 169710037SARM gem5 Developers // Set fault bit and FSR 169810037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 169910037SARM gem5 Developers 170010037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 170110037SARM gem5 Developers if (newVal) { 170210037SARM gem5 Developers // LPAE - rearange fault status 170310037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 170410037SARM gem5 Developers } else { 170510037SARM gem5 Developers // VMSA - rearange fault status 170610037SARM gem5 Developers newVal |= ((fsr >> 0) & 0xf) << 1; 170710037SARM gem5 Developers newVal |= ((fsr >> 10) & 0x1) << 5; 170810037SARM gem5 Developers newVal |= ((fsr >> 12) & 0x1) << 6; 170910037SARM gem5 Developers } 171010037SARM gem5 Developers newVal |= 0x1; // F bit 171110037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 171210037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 171311608Snikos.nikoleris@arm.com DPRINTF(MiscRegs, 171410037SARM gem5 Developers "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 171510037SARM gem5 Developers val, fsr, newVal); 171610037SARM gem5 Developers } 171710037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 171810037SARM gem5 Developers return; 171910037SARM gem5 Developers } 172011577SDylan.Johnson@ARM.com case MISCREG_TTBCR: 172110037SARM gem5 Developers { 172210037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 172310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 172410037SARM gem5 Developers TTBCR ttbcrMask = 0; 172511577SDylan.Johnson@ARM.com TTBCR ttbcrNew = newVal; 172610037SARM gem5 Developers 172710037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 172810037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 172910037SARM gem5 Developers if (haveSecurity) { 173011577SDylan.Johnson@ARM.com ttbcrMask.pd0 = ones; 173110037SARM gem5 Developers ttbcrMask.pd1 = ones; 173210037SARM gem5 Developers } 173310037SARM gem5 Developers ttbcrMask.epd0 = ones; 173410037SARM gem5 Developers ttbcrMask.irgn0 = ones; 173511577SDylan.Johnson@ARM.com ttbcrMask.orgn0 = ones; 173610037SARM gem5 Developers ttbcrMask.sh0 = ones; 173710037SARM gem5 Developers ttbcrMask.ps = ones; // T1SZ 173810037SARM gem5 Developers ttbcrMask.a1 = ones; 173910037SARM gem5 Developers ttbcrMask.epd1 = ones; 174011577SDylan.Johnson@ARM.com ttbcrMask.irgn1 = ones; 174110037SARM gem5 Developers ttbcrMask.orgn1 = ones; 174210037SARM gem5 Developers ttbcrMask.sh1 = ones; 174310037SARM gem5 Developers if (haveLPAE) 174410037SARM gem5 Developers ttbcrMask.eae = ones; 174511577SDylan.Johnson@ARM.com 174610037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 174710037SARM gem5 Developers newVal = newVal & ttbcrMask; 174810037SARM gem5 Developers } else { 174910037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 175011577SDylan.Johnson@ARM.com } 175110037SARM gem5 Developers // Invalidate TLB MiscReg 175210037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 175310037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 175410037SARM gem5 Developers break; 175511577SDylan.Johnson@ARM.com } 175610037SARM gem5 Developers case MISCREG_TTBR0: 175710037SARM gem5 Developers case MISCREG_TTBR1: 175810037SARM gem5 Developers { 175910037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 176011577SDylan.Johnson@ARM.com if (haveLPAE) { 176110037SARM gem5 Developers if (ttbcr.eae) { 176210037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 176310037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 176410037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 176511577SDylan.Johnson@ARM.com newVal = (newVal & (~ttbrMask)); 176610037SARM gem5 Developers } 176710037SARM gem5 Developers } 176810037SARM gem5 Developers // Invalidate TLB MiscReg 176910037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 177011577SDylan.Johnson@ARM.com getDTBPtr(tc)->invalidateMiscReg(); 177110037SARM gem5 Developers break; 177210037SARM gem5 Developers } 177310037SARM gem5 Developers case MISCREG_SCTLR_EL1: 177410037SARM gem5 Developers case MISCREG_CONTEXTIDR: 177511577SDylan.Johnson@ARM.com case MISCREG_PRRR: 177610037SARM gem5 Developers case MISCREG_NMRR: 177710037SARM gem5 Developers case MISCREG_MAIR0: 177810037SARM gem5 Developers case MISCREG_MAIR1: 177910037SARM gem5 Developers case MISCREG_DACR: 178010037SARM gem5 Developers case MISCREG_VTTBR: 178110037SARM gem5 Developers case MISCREG_SCR_EL3: 178210037SARM gem5 Developers case MISCREG_HCR_EL2: 178310037SARM gem5 Developers case MISCREG_TCR_EL1: 178410037SARM gem5 Developers case MISCREG_TCR_EL2: 178510037SARM gem5 Developers case MISCREG_TCR_EL3: 178611560Sandreas.sandberg@arm.com case MISCREG_SCTLR_EL2: 178710037SARM gem5 Developers case MISCREG_SCTLR_EL3: 178811435Smitch.hayenga@arm.com case MISCREG_HSCTLR: 178910037SARM gem5 Developers case MISCREG_TTBR0_EL1: 179010037SARM gem5 Developers case MISCREG_TTBR1_EL1: 179110037SARM gem5 Developers case MISCREG_TTBR0_EL2: 179210037SARM gem5 Developers case MISCREG_TTBR1_EL2: 179310037SARM gem5 Developers case MISCREG_TTBR0_EL3: 179410037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 179510037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 179610037SARM gem5 Developers break; 179710037SARM gem5 Developers case MISCREG_NZCV: 179810037SARM gem5 Developers { 179910037SARM gem5 Developers CPSR cpsr = val; 180010037SARM gem5 Developers 180110037SARM gem5 Developers tc->setCCReg(CCREG_NZ, cpsr.nz); 180210037SARM gem5 Developers tc->setCCReg(CCREG_C, cpsr.c); 180310037SARM gem5 Developers tc->setCCReg(CCREG_V, cpsr.v); 180410037SARM gem5 Developers } 180510037SARM gem5 Developers break; 180610037SARM gem5 Developers case MISCREG_DAIF: 180710037SARM gem5 Developers { 180810037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 180910037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 181011577SDylan.Johnson@ARM.com newVal = cpsr; 181111577SDylan.Johnson@ARM.com misc_reg = MISCREG_CPSR; 181211577SDylan.Johnson@ARM.com } 181311577SDylan.Johnson@ARM.com break; 181411577SDylan.Johnson@ARM.com case MISCREG_SP_EL0: 181511577SDylan.Johnson@ARM.com tc->setIntReg(INTREG_SP0, newVal); 181611577SDylan.Johnson@ARM.com break; 181711577SDylan.Johnson@ARM.com case MISCREG_SP_EL1: 181811577SDylan.Johnson@ARM.com tc->setIntReg(INTREG_SP1, newVal); 181911577SDylan.Johnson@ARM.com break; 182011577SDylan.Johnson@ARM.com case MISCREG_SP_EL2: 182111577SDylan.Johnson@ARM.com tc->setIntReg(INTREG_SP2, newVal); 182211577SDylan.Johnson@ARM.com break; 182311577SDylan.Johnson@ARM.com case MISCREG_SPSEL: 182411577SDylan.Johnson@ARM.com { 182511577SDylan.Johnson@ARM.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 182610037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 182710037SARM gem5 Developers newVal = cpsr; 182810037SARM gem5 Developers misc_reg = MISCREG_CPSR; 182910037SARM gem5 Developers } 183010037SARM gem5 Developers break; 183110037SARM gem5 Developers case MISCREG_CURRENTEL: 183210037SARM gem5 Developers { 183310037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 183410037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 183510037SARM gem5 Developers newVal = cpsr; 183610037SARM gem5 Developers misc_reg = MISCREG_CPSR; 183710037SARM gem5 Developers } 183810037SARM gem5 Developers break; 183910037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 18408549Sdaniel.johnson@arm.com case MISCREG_AT_S1E1W_Xt: 18418549Sdaniel.johnson@arm.com case MISCREG_AT_S1E0R_Xt: 18428549Sdaniel.johnson@arm.com case MISCREG_AT_S1E0W_Xt: 184310037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 184410037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 184510037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 184610844Sandreas.sandberg@arm.com case MISCREG_AT_S12E1W_Xt: 184710844Sandreas.sandberg@arm.com case MISCREG_AT_S12E0R_Xt: 184810844Sandreas.sandberg@arm.com case MISCREG_AT_S12E0W_Xt: 184910844Sandreas.sandberg@arm.com case MISCREG_AT_S1E3R_Xt: 185010844Sandreas.sandberg@arm.com case MISCREG_AT_S1E3W_Xt: 185110037SARM gem5 Developers { 18527405SAli.Saidi@ARM.com RequestPtr req = std::make_shared<Request>(); 18537405SAli.Saidi@ARM.com Request::Flags flags = 0; 18547405SAli.Saidi@ARM.com BaseTLB::Mode mode = BaseTLB::Read; 18557405SAli.Saidi@ARM.com TLB::ArmTranslationType tranType = TLB::NormalTran; 18567405SAli.Saidi@ARM.com Fault fault; 185710037SARM gem5 Developers switch(misc_reg) { 185810709SAndreas.Sandberg@ARM.com case MISCREG_AT_S1E1R_Xt: 185910709SAndreas.Sandberg@ARM.com flags = TLB::MustBeOne; 186010037SARM gem5 Developers tranType = TLB::S1E1Tran; 186110709SAndreas.Sandberg@ARM.com mode = BaseTLB::Read; 186210037SARM gem5 Developers break; 186310037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 186410037SARM gem5 Developers flags = TLB::MustBeOne; 186510037SARM gem5 Developers tranType = TLB::S1E1Tran; 186610037SARM gem5 Developers mode = BaseTLB::Write; 186710037SARM gem5 Developers break; 186810037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 186910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 187010037SARM gem5 Developers tranType = TLB::S1E0Tran; 187110037SARM gem5 Developers mode = BaseTLB::Read; 187210037SARM gem5 Developers break; 187310037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 187410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 187510037SARM gem5 Developers tranType = TLB::S1E0Tran; 187610037SARM gem5 Developers mode = BaseTLB::Write; 187710037SARM gem5 Developers break; 187810037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 187910037SARM gem5 Developers flags = TLB::MustBeOne; 188010037SARM gem5 Developers tranType = TLB::S1E2Tran; 188110037SARM gem5 Developers mode = BaseTLB::Read; 188210037SARM gem5 Developers break; 188310037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 188410037SARM gem5 Developers flags = TLB::MustBeOne; 188510037SARM gem5 Developers tranType = TLB::S1E2Tran; 188610037SARM gem5 Developers mode = BaseTLB::Write; 188710037SARM gem5 Developers break; 188810037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 188910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 189010037SARM gem5 Developers tranType = TLB::S12E0Tran; 189110037SARM gem5 Developers mode = BaseTLB::Read; 189210037SARM gem5 Developers break; 189310037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 189410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 189510037SARM gem5 Developers tranType = TLB::S12E0Tran; 189610037SARM gem5 Developers mode = BaseTLB::Write; 189710037SARM gem5 Developers break; 189810037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 189910037SARM gem5 Developers flags = TLB::MustBeOne; 190010037SARM gem5 Developers tranType = TLB::S12E1Tran; 190110037SARM gem5 Developers mode = BaseTLB::Read; 190210037SARM gem5 Developers break; 190310037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 190410037SARM gem5 Developers flags = TLB::MustBeOne; 190510037SARM gem5 Developers tranType = TLB::S12E1Tran; 190610037SARM gem5 Developers mode = BaseTLB::Write; 190710037SARM gem5 Developers break; 190810037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 190910037SARM gem5 Developers flags = TLB::MustBeOne; 191010037SARM gem5 Developers tranType = TLB::S1E3Tran; 191110037SARM gem5 Developers mode = BaseTLB::Read; 191210037SARM gem5 Developers break; 191310037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 191410037SARM gem5 Developers flags = TLB::MustBeOne; 191510037SARM gem5 Developers tranType = TLB::S1E3Tran; 191610037SARM gem5 Developers mode = BaseTLB::Write; 191710037SARM gem5 Developers break; 191810037SARM gem5 Developers } 191910037SARM gem5 Developers // If we're in timing mode then doing the translation in 192010037SARM gem5 Developers // functional mode then we're slightly distorting performance 192110037SARM gem5 Developers // results obtained from simulations. The translation should be 192210037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 192310037SARM gem5 Developers // can't be an atomic translation because that causes problems 192410037SARM gem5 Developers // with unexpected atomic snoop requests. 192510037SARM gem5 Developers warn("Translating via %s in functional mode! Fix Me!\n", 192610037SARM gem5 Developers miscRegName[misc_reg]); 192710037SARM gem5 Developers 192810037SARM gem5 Developers req->setVirt(0, val, 0, flags, Request::funcMasterId, 192910037SARM gem5 Developers tc->pcState().pc()); 193010037SARM gem5 Developers req->setContext(tc->contextId()); 193110037SARM gem5 Developers fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 193210037SARM gem5 Developers tranType); 193310037SARM gem5 Developers 193410037SARM gem5 Developers MiscReg newVal; 193510037SARM gem5 Developers if (fault == NoFault) { 193610037SARM gem5 Developers Addr paddr = req->getPaddr(); 193710037SARM gem5 Developers uint64_t attr = getDTBPtr(tc)->getAttr(); 193810037SARM gem5 Developers uint64_t attr1 = attr >> 56; 193910037SARM gem5 Developers if (!attr1 || attr1 ==0x44) { 194010037SARM gem5 Developers attr |= 0x100; 194110037SARM gem5 Developers attr &= ~ uint64_t(0x80); 194210037SARM gem5 Developers } 194310037SARM gem5 Developers newVal = (paddr & mask(47, 12)) | attr; 194410037SARM gem5 Developers DPRINTF(MiscRegs, 194510844Sandreas.sandberg@arm.com "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 194610844Sandreas.sandberg@arm.com val, newVal); 194710037SARM gem5 Developers } else { 194810844Sandreas.sandberg@arm.com ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 194910844Sandreas.sandberg@arm.com armFault->update(tc); 195010844Sandreas.sandberg@arm.com // Set fault bit and FSR 195110844Sandreas.sandberg@arm.com FSR fsr = armFault->getFsr(tc); 195210844Sandreas.sandberg@arm.com 195310844Sandreas.sandberg@arm.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 195410844Sandreas.sandberg@arm.com if (cpsr.width) { // AArch32 195510844Sandreas.sandberg@arm.com newVal = ((fsr >> 9) & 1) << 11; 195610844Sandreas.sandberg@arm.com // rearrange fault status 195710844Sandreas.sandberg@arm.com newVal |= ((fsr >> 0) & 0x3f) << 1; 195810037SARM gem5 Developers newVal |= 0x1; // F bit 195910037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 196011150Smitch.hayenga@arm.com newVal |= armFault->isStage2() ? 0x200 : 0; 196110844Sandreas.sandberg@arm.com } else { // AArch64 196210037SARM gem5 Developers newVal = 1; // F bit 196310037SARM gem5 Developers newVal |= fsr << 1; // FST 19647405SAli.Saidi@ARM.com // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 19659384SAndreas.Sandberg@arm.com newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 19669384SAndreas.Sandberg@arm.com newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 19679384SAndreas.Sandberg@arm.com newVal |= 1 << 11; // RES1 19689384SAndreas.Sandberg@arm.com } 19699384SAndreas.Sandberg@arm.com DPRINTF(MiscRegs, 19709384SAndreas.Sandberg@arm.com "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1971 val, fsr, newVal); 1972 } 1973 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1974 return; 1975 } 1976 case MISCREG_SPSR_EL3: 1977 case MISCREG_SPSR_EL2: 1978 case MISCREG_SPSR_EL1: 1979 // Force bits 23:21 to 0 1980 newVal = val & ~(0x7 << 21); 1981 break; 1982 case MISCREG_L2CTLR: 1983 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1984 miscRegName[misc_reg], uint32_t(val)); 1985 break; 1986 1987 // Generic Timer registers 1988 case MISCREG_CNTHV_CTL_EL2: 1989 case MISCREG_CNTHV_CVAL_EL2: 1990 case MISCREG_CNTHV_TVAL_EL2: 1991 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1992 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1993 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1994 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1995 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1996 break; 1997 1998 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 1999 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 2000 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); 2001 return; 2002 } 2003 } 2004 setMiscRegNoEffect(misc_reg, newVal); 2005} 2006 2007BaseISADevice & 2008ISA::getGenericTimer(ThreadContext *tc) 2009{ 2010 // We only need to create an ISA interface the first time we try 2011 // to access the timer. 2012 if (timer) 2013 return *timer.get(); 2014 2015 assert(system); 2016 GenericTimer *generic_timer(system->getGenericTimer()); 2017 if (!generic_timer) { 2018 panic("Trying to get a generic timer from a system that hasn't " 2019 "been configured to use a generic timer.\n"); 2020 } 2021 2022 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2023 timer->setThreadContext(tc); 2024 2025 return *timer.get(); 2026} 2027 2028BaseISADevice & 2029ISA::getGICv3CPUInterface(ThreadContext *tc) 2030{ 2031 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); 2032 return *gicv3CpuInterface.get(); 2033} 2034 2035} 2036 2037ArmISA::ISA * 2038ArmISAParams::create() 2039{ 2040 return new ArmISA::ISA(this); 2041} 2042