isa.cc revision 13499
1360SN/A/* 21458SN/A * Copyright (c) 2010-2018 ARM Limited 3360SN/A * All rights reserved 4360SN/A * 5360SN/A * The license below extends only to copyright in the software and shall 6360SN/A * not be construed as granting a license to any other intellectual 7360SN/A * property including but not limited to intellectual property relating 8360SN/A * to a hardware implementation of the functionality of the software 9360SN/A * licensed hereunder. You may use the software subject to the license 10360SN/A * terms below provided that you ensure that this notice is replicated 11360SN/A * unmodified and in its entirety in all distributions of the software, 12360SN/A * modified or unmodified, in source code or in binary form. 13360SN/A * 14360SN/A * Redistribution and use in source and binary forms, with or without 15360SN/A * modification, are permitted provided that the following conditions are 16360SN/A * met: redistributions of source code must retain the above copyright 17360SN/A * notice, this list of conditions and the following disclaimer; 18360SN/A * redistributions in binary form must reproduce the above copyright 19360SN/A * notice, this list of conditions and the following disclaimer in the 20360SN/A * documentation and/or other materials provided with the distribution; 21360SN/A * neither the name of the copyright holders nor the names of its 22360SN/A * contributors may be used to endorse or promote products derived from 23360SN/A * this software without specific prior written permission. 24360SN/A * 25360SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26360SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30360SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31360SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 321354SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 331354SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34360SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352764Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362764Sstever@eecs.umich.edu * 372064SN/A * Authors: Gabe Black 38360SN/A * Ali Saidi 39360SN/A */ 40360SN/A 41360SN/A#include "arch/arm/isa.hh" 42360SN/A#include "arch/arm/pmu.hh" 43360SN/A#include "arch/arm/system.hh" 441354SN/A#include "arch/arm/tlb.hh" 45360SN/A#include "arch/arm/tlbi_op.hh" 461809SN/A#include "cpu/base.hh" 471809SN/A#include "cpu/checker/cpu.hh" 481809SN/A#include "debug/Arm.hh" 493113Sgblack@eecs.umich.edu#include "debug/MiscRegs.hh" 503113Sgblack@eecs.umich.edu#include "dev/arm/generic_timer.hh" 511999SN/A#include "params/ArmISA.hh" 52360SN/A#include "sim/faults.hh" 533113Sgblack@eecs.umich.edu#include "sim/stat_control.hh" 542474SN/A#include "sim/system.hh" 55360SN/A 562462SN/Anamespace ArmISA 571354SN/A{ 582474SN/A 592680Sktlim@umich.eduISA::ISA(Params *p) 602474SN/A : SimObject(p), 612474SN/A system(NULL), 621354SN/A _decoderFlavour(p->decoderFlavour), 63360SN/A _vecRegRenameMode(p->vecRegRenameMode), 64360SN/A pmu(p->pmu), 65360SN/A impdefAsNop(p->impdef_nop) 66360SN/A{ 67360SN/A miscRegs[MISCREG_SCTLR_RST] = 0; 68360SN/A 69360SN/A // Hook up a dummy device if we haven't been configured with a 70360SN/A // real PMU. By using a dummy device, we don't need to check that 71378SN/A // the PMU exist every time we try to access a PMU register. 721450SN/A if (!pmu) 733114Sgblack@eecs.umich.edu pmu = &dummyDevice; 74360SN/A 75360SN/A // Give all ISA devices a pointer to this ISA 76360SN/A pmu->setISA(this); 77360SN/A 78360SN/A system = dynamic_cast<ArmSystem *>(p->system); 79360SN/A 80360SN/A // Cache system-level properties 81360SN/A if (FullSystem && system) { 82360SN/A highestELIs64 = system->highestELIs64(); 832680Sktlim@umich.edu haveSecurity = system->haveSecurity(); 84360SN/A haveLPAE = system->haveLPAE(); 85360SN/A haveCrypto = system->haveCrypto(); 86360SN/A haveVirtualization = system->haveVirtualization(); 87360SN/A haveLargeAsid64 = system->haveLargeAsid64(); 88360SN/A physAddrRange = system->physAddrRange(); 89360SN/A } else { 90360SN/A highestELIs64 = true; // ArmSystem::highestELIs64 does the same 91360SN/A haveSecurity = haveLPAE = haveVirtualization = false; 92360SN/A haveCrypto = true; 93360SN/A haveLargeAsid64 = false; 94360SN/A physAddrRange = 32; // dummy value 953114Sgblack@eecs.umich.edu } 96360SN/A 97360SN/A initializeMiscRegMetadata(); 98360SN/A preUnflattenMiscReg(); 99360SN/A 100360SN/A clear(); 101360SN/A} 102360SN/A 103360SN/Astd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 104360SN/A 105360SN/Aconst ArmISAParams * 106360SN/AISA::params() const 107360SN/A{ 108360SN/A return dynamic_cast<const Params *>(_params); 109360SN/A} 110360SN/A 111360SN/Avoid 112360SN/AISA::clear() 113360SN/A{ 114360SN/A const Params *p(params()); 115360SN/A 116360SN/A SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 1172400SN/A memset(miscRegs, 0, sizeof(miscRegs)); 118360SN/A 1192461SN/A initID32(p); 120360SN/A 121360SN/A // We always initialize AArch64 ID registers even 122360SN/A // if we are in AArch32. This is done since if we 123360SN/A // are in SE mode we don't know if our ArmProcess is 124360SN/A // AArch32 or AArch64 125360SN/A initID64(p); 1262400SN/A 127360SN/A // Start with an event in the mailbox 1282461SN/A miscRegs[MISCREG_SEV_MAILBOX] = 1; 129360SN/A 130360SN/A // Separate Instruction and Data TLBs 131360SN/A miscRegs[MISCREG_TLBTR] = 1; 132360SN/A 133360SN/A MVFR0 mvfr0 = 0; 134360SN/A mvfr0.advSimdRegisters = 2; 135360SN/A mvfr0.singlePrecision = 2; 136360SN/A mvfr0.doublePrecision = 2; 137360SN/A mvfr0.vfpExceptionTrapping = 0; 138360SN/A mvfr0.divide = 1; 139360SN/A mvfr0.squareRoot = 1; 140360SN/A mvfr0.shortVectors = 1; 141360SN/A mvfr0.roundingModes = 1; 142360SN/A miscRegs[MISCREG_MVFR0] = mvfr0; 143360SN/A 144360SN/A MVFR1 mvfr1 = 0; 145360SN/A mvfr1.flushToZero = 1; 146360SN/A mvfr1.defaultNaN = 1; 147360SN/A mvfr1.advSimdLoadStore = 1; 148360SN/A mvfr1.advSimdInteger = 1; 149360SN/A mvfr1.advSimdSinglePrecision = 1; 150360SN/A mvfr1.advSimdHalfPrecision = 1; 151360SN/A mvfr1.vfpHalfPrecision = 1; 152360SN/A miscRegs[MISCREG_MVFR1] = mvfr1; 153360SN/A 154360SN/A // Reset values of PRRR and NMRR are implementation dependent 155360SN/A 156360SN/A // @todo: PRRR and NMRR in secure state? 157360SN/A miscRegs[MISCREG_PRRR_NS] = 158360SN/A (1 << 19) | // 19 159360SN/A (0 << 18) | // 18 160360SN/A (0 << 17) | // 17 161502SN/A (1 << 16) | // 16 162360SN/A (2 << 14) | // 15:14 163502SN/A (0 << 12) | // 13:12 164360SN/A (2 << 10) | // 11:10 165360SN/A (2 << 8) | // 9:8 166360SN/A (2 << 6) | // 7:6 167360SN/A (2 << 4) | // 5:4 168360SN/A (1 << 2) | // 3:2 169360SN/A 0; // 1:0 170360SN/A 171360SN/A miscRegs[MISCREG_NMRR_NS] = 172360SN/A (1 << 30) | // 31:30 173360SN/A (0 << 26) | // 27:26 174360SN/A (0 << 24) | // 25:24 175378SN/A (3 << 22) | // 23:22 1761706SN/A (2 << 20) | // 21:20 1773114Sgblack@eecs.umich.edu (0 << 18) | // 19:18 178378SN/A (0 << 16) | // 17:16 179378SN/A (1 << 14) | // 15:14 180378SN/A (0 << 12) | // 13:12 181378SN/A (2 << 10) | // 11:10 182378SN/A (0 << 8) | // 9:8 1831706SN/A (3 << 6) | // 7:6 1843114Sgblack@eecs.umich.edu (2 << 4) | // 5:4 185360SN/A (0 << 2) | // 3:2 186378SN/A 0; // 1:0 1871706SN/A 1883114Sgblack@eecs.umich.edu if (FullSystem && system->highestELIs64()) { 189378SN/A // Initialize AArch64 state 190378SN/A clear64(p); 1911706SN/A return; 1923114Sgblack@eecs.umich.edu } 193378SN/A 194378SN/A // Initialize AArch32 state... 1951706SN/A clear32(p, sctlr_rst); 1963114Sgblack@eecs.umich.edu} 197378SN/A 198378SN/Avoid 1991706SN/AISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 2003114Sgblack@eecs.umich.edu{ 201378SN/A CPSR cpsr = 0; 202378SN/A cpsr.mode = MODE_USER; 2031706SN/A 2043114Sgblack@eecs.umich.edu if (FullSystem) { 205378SN/A miscRegs[MISCREG_MVBAR] = system->resetAddr(); 206378SN/A } 2071706SN/A 2083114Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 209378SN/A updateRegMap(cpsr); 210378SN/A 2111706SN/A SCTLR sctlr = 0; 2123114Sgblack@eecs.umich.edu sctlr.te = (bool) sctlr_rst.te; 213378SN/A sctlr.nmfi = (bool) sctlr_rst.nmfi; 214378SN/A sctlr.v = (bool) sctlr_rst.v; 2151706SN/A sctlr.u = 1; 2163114Sgblack@eecs.umich.edu sctlr.xp = 1; 217378SN/A sctlr.rao2 = 1; 218378SN/A sctlr.rao3 = 1; 2191706SN/A sctlr.rao4 = 0xf; // SCTLR[6:3] 2203114Sgblack@eecs.umich.edu sctlr.uci = 1; 221360SN/A sctlr.dze = 1; 222511SN/A miscRegs[MISCREG_SCTLR_NS] = sctlr; 2231706SN/A miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 2243114Sgblack@eecs.umich.edu miscRegs[MISCREG_HCPTR] = 0; 225511SN/A 226511SN/A miscRegs[MISCREG_CPACR] = 0; 2271706SN/A 2283114Sgblack@eecs.umich.edu miscRegs[MISCREG_FPSID] = p->fpsid; 2291706SN/A 2301706SN/A if (haveLPAE) { 2311706SN/A TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 2321706SN/A ttbcr.eae = 0; 2333114Sgblack@eecs.umich.edu miscRegs[MISCREG_TTBCR_NS] = ttbcr; 2341706SN/A // Enforce consistency with system-level settings 2351706SN/A miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 2361706SN/A } 2371706SN/A 2383114Sgblack@eecs.umich.edu if (haveSecurity) { 2391706SN/A miscRegs[MISCREG_SCTLR_S] = sctlr; 240511SN/A miscRegs[MISCREG_SCR] = 0; 2411999SN/A miscRegs[MISCREG_VBAR_S] = 0; 2421999SN/A } else { 2433114Sgblack@eecs.umich.edu // we're always non-secure 2441999SN/A miscRegs[MISCREG_SCR] = 1; 2451999SN/A } 2461999SN/A 2471999SN/A //XXX We need to initialize the rest of the state. 2483114Sgblack@eecs.umich.edu} 2491999SN/A 2503079Sstever@eecs.umich.eduvoid 2513079Sstever@eecs.umich.eduISA::clear64(const ArmISAParams *p) 2523114Sgblack@eecs.umich.edu{ 2533079Sstever@eecs.umich.edu CPSR cpsr = 0; 2542093SN/A Addr rvbar = system->resetAddr(); 2552093SN/A switch (system->highestEL()) { 2563114Sgblack@eecs.umich.edu // Set initial EL to highest implemented EL using associated stack 2572093SN/A // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 2582687Sksewell@umich.edu // value 2592687Sksewell@umich.edu case EL3: 2603114Sgblack@eecs.umich.edu cpsr.mode = MODE_EL3H; 2612687Sksewell@umich.edu miscRegs[MISCREG_RVBAR_EL3] = rvbar; 2622238SN/A break; 2632238SN/A case EL2: 2643114Sgblack@eecs.umich.edu cpsr.mode = MODE_EL2H; 2652238SN/A miscRegs[MISCREG_RVBAR_EL2] = rvbar; 2662238SN/A break; 2672238SN/A case EL1: 2683114Sgblack@eecs.umich.edu cpsr.mode = MODE_EL1H; 2692238SN/A miscRegs[MISCREG_RVBAR_EL1] = rvbar; 2702238SN/A break; 2712238SN/A default: 2723114Sgblack@eecs.umich.edu panic("Invalid highest implemented exception level"); 2732238SN/A break; 2742238SN/A } 2752238SN/A 2763114Sgblack@eecs.umich.edu // Initialize rest of CPSR 2772238SN/A cpsr.daif = 0xf; // Mask all interrupts 2782238SN/A cpsr.ss = 0; 2792238SN/A cpsr.il = 0; 2803114Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 2812238SN/A updateRegMap(cpsr); 2822238SN/A 2832238SN/A // Initialize other control registers 2843114Sgblack@eecs.umich.edu miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 2852238SN/A if (haveSecurity) { 2862238SN/A miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 2872238SN/A miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 2883114Sgblack@eecs.umich.edu } else if (haveVirtualization) { 2892238SN/A // also MISCREG_SCTLR_EL2 (by mapping) 2902238SN/A miscRegs[MISCREG_HSCTLR] = 0x30c50830; 2912238SN/A } else { 2922238SN/A // also MISCREG_SCTLR_EL1 (by mapping) 2932238SN/A miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 2942238SN/A // Always non-secure 2953114Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR_EL3] = 1; 2962238SN/A } 2972238SN/A} 2982238SN/A 2993114Sgblack@eecs.umich.eduvoid 3002238SN/AISA::initID32(const ArmISAParams *p) 3012238SN/A{ 3022238SN/A // Initialize configurable default values 3033114Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR] = p->midr; 3042238SN/A miscRegs[MISCREG_MIDR_EL1] = p->midr; 3052238SN/A miscRegs[MISCREG_VPIDR] = p->midr; 3062238SN/A 3073114Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 3082238SN/A miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 3092238SN/A miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 3101354SN/A miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 3111354SN/A miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 3121354SN/A miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 3131354SN/A 3141354SN/A miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 3151354SN/A miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 3161354SN/A miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 3171354SN/A miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 3181354SN/A 3191354SN/A miscRegs[MISCREG_ID_ISAR5] = insertBits( 3201354SN/A miscRegs[MISCREG_ID_ISAR5], 19, 4, 3211354SN/A haveCrypto ? 0x1112 : 0x0); 3221354SN/A} 3231354SN/A 3241609SN/Avoid 3251354SN/AISA::initID64(const ArmISAParams *p) 3261354SN/A{ 3271354SN/A // Initialize configurable id registers 3281354SN/A miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 329360SN/A miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 330360SN/A miscRegs[MISCREG_ID_AA64DFR0_EL1] = 331360SN/A (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 332360SN/A (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 333360SN/A 334360SN/A miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 335360SN/A miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 3363113Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 3373113Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 3383113Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 3393113Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 3403113Sgblack@eecs.umich.edu 3413113Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_DFR0_EL1] = 3423113Sgblack@eecs.umich.edu (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 3433113Sgblack@eecs.umich.edu 3443113Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 3453113Sgblack@eecs.umich.edu 3463113Sgblack@eecs.umich.edu // Enforce consistency with system-level settings... 3473113Sgblack@eecs.umich.edu 3483113Sgblack@eecs.umich.edu // EL3 3493113Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 3503113Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 3513113Sgblack@eecs.umich.edu haveSecurity ? 0x2 : 0x0); 3523113Sgblack@eecs.umich.edu // EL2 3533113Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 3543113Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 3553113Sgblack@eecs.umich.edu haveVirtualization ? 0x2 : 0x0); 3563113Sgblack@eecs.umich.edu // Large ASID support 3573113Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 3583113Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 3593277Sgblack@eecs.umich.edu haveLargeAsid64 ? 0x2 : 0x0); 3603277Sgblack@eecs.umich.edu // Physical address size 3613277Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 3623277Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 3633277Sgblack@eecs.umich.edu encodePhysAddrRange64(physAddrRange)); 3643277Sgblack@eecs.umich.edu // Crypto 3653277Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 3663277Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 3673113Sgblack@eecs.umich.edu haveCrypto ? 0x1112 : 0x0); 3683113Sgblack@eecs.umich.edu} 3693113Sgblack@eecs.umich.edu 3703113Sgblack@eecs.umich.eduvoid 3713113Sgblack@eecs.umich.eduISA::startup(ThreadContext *tc) 3723113Sgblack@eecs.umich.edu{ 3733113Sgblack@eecs.umich.edu pmu->setThreadContext(tc); 3743114Sgblack@eecs.umich.edu 3753113Sgblack@eecs.umich.edu} 3763114Sgblack@eecs.umich.edu 3773113Sgblack@eecs.umich.edu 3783114Sgblack@eecs.umich.eduMiscReg 3793113Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int misc_reg) const 3803113Sgblack@eecs.umich.edu{ 3813113Sgblack@eecs.umich.edu assert(misc_reg < NumMiscRegs); 3823113Sgblack@eecs.umich.edu 3833113Sgblack@eecs.umich.edu const auto ® = lookUpMiscReg[misc_reg]; // bit masks 3843113Sgblack@eecs.umich.edu const auto &map = getMiscIndices(misc_reg); 3853113Sgblack@eecs.umich.edu int lower = map.first, upper = map.second; 3863113Sgblack@eecs.umich.edu // NB!: apply architectural masks according to desired register, 3873113Sgblack@eecs.umich.edu // despite possibly getting value from different (mapped) register. 3883113Sgblack@eecs.umich.edu auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 3893113Sgblack@eecs.umich.edu |(miscRegs[upper] << 32)); 3903113Sgblack@eecs.umich.edu if (val & reg.res0()) { 3913113Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 3923113Sgblack@eecs.umich.edu miscRegName[misc_reg], val & reg.res0()); 3933113Sgblack@eecs.umich.edu } 3943113Sgblack@eecs.umich.edu if ((val & reg.res1()) != reg.res1()) { 3953113Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 3963113Sgblack@eecs.umich.edu miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 3973113Sgblack@eecs.umich.edu } 3983113Sgblack@eecs.umich.edu return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 3993113Sgblack@eecs.umich.edu} 4003113Sgblack@eecs.umich.edu 4013113Sgblack@eecs.umich.edu 4023113Sgblack@eecs.umich.eduMiscReg 4033113Sgblack@eecs.umich.eduISA::readMiscReg(int misc_reg, ThreadContext *tc) 4043113Sgblack@eecs.umich.edu{ 4053113Sgblack@eecs.umich.edu CPSR cpsr = 0; 4063113Sgblack@eecs.umich.edu PCState pc = 0; 4073113Sgblack@eecs.umich.edu SCR scr = 0; 4083113Sgblack@eecs.umich.edu 4093113Sgblack@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 4103113Sgblack@eecs.umich.edu cpsr = miscRegs[misc_reg]; 4113113Sgblack@eecs.umich.edu pc = tc->pcState(); 4123113Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 4133113Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 4143113Sgblack@eecs.umich.edu return cpsr; 4153113Sgblack@eecs.umich.edu } 4163113Sgblack@eecs.umich.edu 4173113Sgblack@eecs.umich.edu#ifndef NDEBUG 4183113Sgblack@eecs.umich.edu if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 4193113Sgblack@eecs.umich.edu if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 4203113Sgblack@eecs.umich.edu warn("Unimplemented system register %s read.\n", 4213113Sgblack@eecs.umich.edu miscRegName[misc_reg]); 4223113Sgblack@eecs.umich.edu else 4233113Sgblack@eecs.umich.edu panic("Unimplemented system register %s read.\n", 4243113Sgblack@eecs.umich.edu miscRegName[misc_reg]); 4253113Sgblack@eecs.umich.edu } 4263113Sgblack@eecs.umich.edu#endif 4273113Sgblack@eecs.umich.edu 4283113Sgblack@eecs.umich.edu switch (unflattenMiscReg(misc_reg)) { 4293113Sgblack@eecs.umich.edu case MISCREG_HCR: 430378SN/A { 431378SN/A if (!haveVirtualization) 432378SN/A return 0; 433360SN/A else 4341450SN/A return readMiscRegNoEffect(MISCREG_HCR); 4353114Sgblack@eecs.umich.edu } 4362680Sktlim@umich.edu case MISCREG_CPACR: 437360SN/A { 4382680Sktlim@umich.edu const uint32_t ones = (uint32_t)(-1); 4392680Sktlim@umich.edu CPACR cpacrMask = 0; 440360SN/A // Only cp10, cp11, and ase are implemented, nothing else should 4411969SN/A // be readable? (straight copy from the write code) 442360SN/A cpacrMask.cp10 = ones; 443360SN/A cpacrMask.cp11 = ones; 444360SN/A cpacrMask.asedis = ones; 4451458SN/A 446360SN/A // Security Extensions may limit the readability of CPACR 447360SN/A if (haveSecurity) { 448360SN/A scr = readMiscRegNoEffect(MISCREG_SCR); 4492553SN/A cpsr = readMiscRegNoEffect(MISCREG_CPSR); 4502553SN/A if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 4512553SN/A NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 4522553SN/A // NB: Skipping the full loop, here 4532553SN/A if (!nsacr.cp10) cpacrMask.cp10 = 0; 4542553SN/A if (!nsacr.cp11) cpacrMask.cp11 = 0; 4552553SN/A } 4562553SN/A } 4571458SN/A MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 458360SN/A val &= cpacrMask; 459360SN/A DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 4601706SN/A miscRegName[misc_reg], val); 4612680Sktlim@umich.edu return val; 462360SN/A } 463360SN/A case MISCREG_MPIDR: 464360SN/A cpsr = readMiscRegNoEffect(MISCREG_CPSR); 465378SN/A scr = readMiscRegNoEffect(MISCREG_SCR); 466360SN/A if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 4671450SN/A return getMPIDR(system, tc); 4683114Sgblack@eecs.umich.edu } else { 4692680Sktlim@umich.edu return readMiscReg(MISCREG_VMPIDR, tc); 470360SN/A } 471360SN/A break; 472360SN/A case MISCREG_MPIDR_EL1: 4732680Sktlim@umich.edu // @todo in the absence of v8 virtualization support just return MPIDR_EL1 4741458SN/A return getMPIDR(system, tc) & 0xffffffff; 475360SN/A case MISCREG_VMPIDR: 476360SN/A // top bit defined as RES1 477360SN/A return readMiscRegNoEffect(misc_reg) | 0x80000000; 478360SN/A case MISCREG_ID_AFR0: // not implemented, so alias MIDR 4791706SN/A case MISCREG_REVIDR: // not implemented, so alias MIDR 4801458SN/A case MISCREG_MIDR: 481360SN/A cpsr = readMiscRegNoEffect(MISCREG_CPSR); 482360SN/A scr = readMiscRegNoEffect(MISCREG_SCR); 4832680Sktlim@umich.edu if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 4842680Sktlim@umich.edu return readMiscRegNoEffect(misc_reg); 485360SN/A } else { 486360SN/A return readMiscRegNoEffect(MISCREG_VPIDR); 487360SN/A } 488360SN/A break; 489360SN/A case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 490360SN/A case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 491360SN/A case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 492360SN/A case MISCREG_AIDR: // AUX ID set to 0 493360SN/A case MISCREG_TCMTR: // No TCM's 494360SN/A return 0; 495360SN/A 496360SN/A case MISCREG_CLIDR: 4971706SN/A warn_once("The clidr register always reports 0 caches.\n"); 498360SN/A warn_once("clidr LoUIS field of 0b001 to match current " 499360SN/A "ARM implementations.\n"); 500360SN/A return 0x00200000; 501360SN/A case MISCREG_CCSIDR: 502360SN/A warn_once("The ccsidr register isn't implemented and " 5031706SN/A "always reads as 0.\n"); 5041706SN/A break; 505360SN/A case MISCREG_CTR: // AArch32, ARMv7, top bit set 506360SN/A case MISCREG_CTR_EL0: // AArch64 507360SN/A { 5081970SN/A //all caches have the same line size in gem5 509360SN/A //4 byte words in ARM 510360SN/A unsigned lineSizeWords = 511360SN/A tc->getSystemPtr()->cacheLineSize() / 4; 5121999SN/A unsigned log2LineSizeWords = 0; 5131999SN/A 5141999SN/A while (lineSizeWords >>= 1) { 5153114Sgblack@eecs.umich.edu ++log2LineSizeWords; 5162680Sktlim@umich.edu } 5171999SN/A 5181999SN/A CTR ctr = 0; 5191999SN/A //log2 of minimun i-cache line size (words) 5202680Sktlim@umich.edu ctr.iCacheLineSize = log2LineSizeWords; 5211999SN/A //b11 - gem5 uses pipt 5221999SN/A ctr.l1IndexPolicy = 0x3; 5232680Sktlim@umich.edu //log2 of minimum d-cache line size (words) 5241999SN/A ctr.dCacheLineSize = log2LineSizeWords; 5251999SN/A //log2 of max reservation size (words) 5261999SN/A ctr.erg = log2LineSizeWords; 5271999SN/A //log2 of max writeback size (words) 5281999SN/A ctr.cwg = log2LineSizeWords; 5291999SN/A //b100 - gem5 format is ARMv7 5301999SN/A ctr.format = 0x4; 5311999SN/A 5322218SN/A return ctr; 5331999SN/A } 5341999SN/A case MISCREG_ACTLR: 5351999SN/A warn("Not doing anything for miscreg ACTLR\n"); 5361999SN/A break; 5371999SN/A 5381999SN/A case MISCREG_PMXEVTYPER_PMCCFILTR: 5391999SN/A case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 5401999SN/A case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 5413114Sgblack@eecs.umich.edu case MISCREG_PMCR ... MISCREG_PMOVSSET: 5422680Sktlim@umich.edu return pmu->readMiscReg(misc_reg); 5431999SN/A 5442680Sktlim@umich.edu case MISCREG_CPSR_Q: 5451999SN/A panic("shouldn't be reading this register seperately\n"); 5461999SN/A case MISCREG_FPSCR_QC: 5471999SN/A return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 5481999SN/A case MISCREG_FPSCR_EXC: 5491999SN/A return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 5502680Sktlim@umich.edu case MISCREG_FPSR: 5511999SN/A { 5521999SN/A const uint32_t ones = (uint32_t)(-1); 5531999SN/A FPSCR fpscrMask = 0; 5541999SN/A fpscrMask.ioc = ones; 5551999SN/A fpscrMask.dzc = ones; 5561999SN/A fpscrMask.ofc = ones; 5571999SN/A fpscrMask.ufc = ones; 5581999SN/A fpscrMask.ixc = ones; 5592218SN/A fpscrMask.idc = ones; 5601999SN/A fpscrMask.qc = ones; 5611999SN/A fpscrMask.v = ones; 5621999SN/A fpscrMask.c = ones; 5631999SN/A fpscrMask.z = ones; 5641999SN/A fpscrMask.n = ones; 565378SN/A return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 566360SN/A } 5671450SN/A case MISCREG_FPCR: 5683114Sgblack@eecs.umich.edu { 5692680Sktlim@umich.edu const uint32_t ones = (uint32_t)(-1); 570360SN/A FPSCR fpscrMask = 0; 571360SN/A fpscrMask.len = ones; 572360SN/A fpscrMask.stride = ones; 5732680Sktlim@umich.edu fpscrMask.rMode = ones; 5742400SN/A fpscrMask.fz = ones; 575360SN/A fpscrMask.dn = ones; 576360SN/A fpscrMask.ahp = ones; 577360SN/A return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 578360SN/A } 579360SN/A case MISCREG_NZCV: 5802218SN/A { 581360SN/A CPSR cpsr = 0; 5823113Sgblack@eecs.umich.edu cpsr.nz = tc->readCCReg(CCREG_NZ); 583360SN/A cpsr.c = tc->readCCReg(CCREG_C); 5841458SN/A cpsr.v = tc->readCCReg(CCREG_V); 585360SN/A return cpsr; 586360SN/A } 587360SN/A case MISCREG_DAIF: 5881999SN/A { 5891999SN/A CPSR cpsr = 0; 5901999SN/A cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 5913114Sgblack@eecs.umich.edu return cpsr; 5922680Sktlim@umich.edu } 5931999SN/A case MISCREG_SP_EL0: 5942680Sktlim@umich.edu { 5951999SN/A return tc->readIntReg(INTREG_SP0); 5961999SN/A } 5971999SN/A case MISCREG_SP_EL1: 5981999SN/A { 5991999SN/A return tc->readIntReg(INTREG_SP1); 6002764Sstever@eecs.umich.edu } 6012064SN/A case MISCREG_SP_EL2: 6022064SN/A { 6032064SN/A return tc->readIntReg(INTREG_SP2); 6042064SN/A } 6051999SN/A case MISCREG_SPSEL: 6062064SN/A { 6071999SN/A return miscRegs[MISCREG_CPSR] & 0x1; 6081999SN/A } 6092218SN/A case MISCREG_CURRENTEL: 6101999SN/A { 6113114Sgblack@eecs.umich.edu return miscRegs[MISCREG_CPSR] & 0xc; 6123114Sgblack@eecs.umich.edu } 6131999SN/A case MISCREG_L2CTLR: 6141999SN/A { 6151999SN/A // mostly unimplemented, just set NumCPUs field from sim and return 6161999SN/A L2CTLR l2ctlr = 0; 6171999SN/A // b00:1CPU to b11:4CPUs 618378SN/A l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 619360SN/A return l2ctlr; 6201450SN/A } 6213114Sgblack@eecs.umich.edu case MISCREG_DBGDIDR: 6222680Sktlim@umich.edu /* For now just implement the version number. 623360SN/A * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 624360SN/A */ 625360SN/A return 0x5 << 16; 6262680Sktlim@umich.edu case MISCREG_DBGDSCRint: 6272400SN/A return 0; 628360SN/A case MISCREG_ISR: 629360SN/A return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 630360SN/A readMiscRegNoEffect(MISCREG_HCR), 631360SN/A readMiscRegNoEffect(MISCREG_CPSR), 632360SN/A readMiscRegNoEffect(MISCREG_SCR)); 6331458SN/A case MISCREG_ISR_EL1: 634360SN/A return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 6353113Sgblack@eecs.umich.edu readMiscRegNoEffect(MISCREG_HCR_EL2), 636360SN/A readMiscRegNoEffect(MISCREG_CPSR), 6371458SN/A readMiscRegNoEffect(MISCREG_SCR_EL3)); 638360SN/A case MISCREG_DCZID_EL0: 639360SN/A return 0x04; // DC ZVA clear 64-byte chunks 6401999SN/A case MISCREG_HCPTR: 6411999SN/A { 6421999SN/A MiscReg val = readMiscRegNoEffect(misc_reg); 6433114Sgblack@eecs.umich.edu // The trap bit associated with CP14 is defined as RAZ 6442680Sktlim@umich.edu val &= ~(1 << 14); 6451999SN/A // If a CP bit in NSACR is 0 then the corresponding bit in 6461999SN/A // HCPTR is RAO/WI 6471999SN/A bool secure_lookup = haveSecurity && 6482680Sktlim@umich.edu inSecureState(readMiscRegNoEffect(MISCREG_SCR), 6492400SN/A readMiscRegNoEffect(MISCREG_CPSR)); 6501999SN/A if (!secure_lookup) { 6512764Sstever@eecs.umich.edu MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 6522064SN/A val |= (mask ^ 0x7FFF) & 0xBFFF; 6532064SN/A } 6542064SN/A // Set the bits for unimplemented coprocessors to RAO/WI 6551999SN/A val |= 0x33FF; 6561999SN/A return (val); 6572064SN/A } 6581999SN/A case MISCREG_HDFAR: // alias for secure DFAR 6591999SN/A return readMiscRegNoEffect(MISCREG_DFAR_S); 6601999SN/A case MISCREG_HIFAR: // alias for secure IFAR 6611999SN/A return readMiscRegNoEffect(MISCREG_IFAR_S); 6623114Sgblack@eecs.umich.edu case MISCREG_HVBAR: // bottom bits reserved 6631999SN/A return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 6641999SN/A case MISCREG_SCTLR: 6651999SN/A return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 6661999SN/A case MISCREG_SCTLR_EL1: 667378SN/A return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 668360SN/A case MISCREG_SCTLR_EL2: 6691450SN/A case MISCREG_SCTLR_EL3: 6703114Sgblack@eecs.umich.edu case MISCREG_HSCTLR: 6712680Sktlim@umich.edu return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 672360SN/A 6732680Sktlim@umich.edu case MISCREG_ID_PFR0: 674360SN/A // !ThumbEE | !Jazelle | Thumb | ARM 6751969SN/A return 0x00000031; 676360SN/A case MISCREG_ID_PFR1: 677360SN/A { // Timer | Virti | !M Profile | TrustZone | ARMv4 6781458SN/A bool haveTimer = (system->getGenericTimer() != NULL); 679360SN/A return 0x00000001 680360SN/A | (haveSecurity ? 0x00000010 : 0x0) 681360SN/A | (haveVirtualization ? 0x00001000 : 0x0) 682360SN/A | (haveTimer ? 0x00010000 : 0x0); 683360SN/A } 6841458SN/A case MISCREG_ID_AA64PFR0_EL1: 685360SN/A return 0x0000000000000002 // AArch{64,32} supported at EL0 6863114Sgblack@eecs.umich.edu | 0x0000000000000020 // EL1 6873114Sgblack@eecs.umich.edu | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 6882021SN/A | (haveSecurity ? 0x0000000000002000 : 0); // EL3 6891458SN/A case MISCREG_ID_AA64PFR1_EL1: 690360SN/A return 0; // bits [63:0] RES0 (reserved for future use) 691360SN/A 692360SN/A // Generic Timer registers 6931706SN/A case MISCREG_CNTHV_CTL_EL2: 6941706SN/A case MISCREG_CNTHV_CVAL_EL2: 6951706SN/A case MISCREG_CNTHV_TVAL_EL2: 6963114Sgblack@eecs.umich.edu case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 6972680Sktlim@umich.edu case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 6981706SN/A case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 6991706SN/A case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 7001706SN/A return getGenericTimer(tc).readMiscReg(misc_reg); 7012680Sktlim@umich.edu 7022400SN/A default: 7031706SN/A break; 7041706SN/A 7051706SN/A } 7061706SN/A return readMiscRegNoEffect(misc_reg); 7071706SN/A} 7082218SN/A 7091706SN/Avoid 7103114Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 7113114Sgblack@eecs.umich.edu{ 7121706SN/A assert(misc_reg < NumMiscRegs); 7131706SN/A 7141706SN/A const auto ® = lookUpMiscReg[misc_reg]; // bit masks 7151706SN/A const auto &map = getMiscIndices(misc_reg); 7161706SN/A int lower = map.first, upper = map.second; 7171706SN/A 7181706SN/A auto v = (val & ~reg.wi()) | reg.rao(); 7191706SN/A if (upper > 0) { 7203114Sgblack@eecs.umich.edu miscRegs[lower] = bits(v, 31, 0); 7212680Sktlim@umich.edu miscRegs[upper] = bits(v, 63, 32); 7221706SN/A DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 7232680Sktlim@umich.edu misc_reg, lower, upper, v); 7241706SN/A } else { 7251706SN/A miscRegs[lower] = v; 7261706SN/A DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 7271706SN/A misc_reg, lower, v); 7281706SN/A } 7291706SN/A} 7301706SN/A 7311706SN/Avoid 7322218SN/AISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 7331706SN/A{ 7343114Sgblack@eecs.umich.edu 7353114Sgblack@eecs.umich.edu MiscReg newVal = val; 7361706SN/A bool secure_lookup; 7371706SN/A SCR scr; 7381706SN/A 7391706SN/A if (misc_reg == MISCREG_CPSR) { 7401706SN/A updateRegMap(val); 7411999SN/A 7421999SN/A 7431999SN/A CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 7443114Sgblack@eecs.umich.edu int old_mode = old_cpsr.mode; 7452680Sktlim@umich.edu CPSR cpsr = val; 7461999SN/A if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 7472680Sktlim@umich.edu getITBPtr(tc)->invalidateMiscReg(); 7481999SN/A getDTBPtr(tc)->invalidateMiscReg(); 7491999SN/A } 7501999SN/A 7511999SN/A DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 7521999SN/A miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 7532680Sktlim@umich.edu PCState pc = tc->pcState(); 7542680Sktlim@umich.edu pc.nextThumb(cpsr.t); 7552680Sktlim@umich.edu pc.nextJazelle(cpsr.j); 7561999SN/A pc.illegalExec(cpsr.il == 1); 7571999SN/A 7581999SN/A // Follow slightly different semantics if a CheckerCPU object 7591999SN/A // is connected 7602461SN/A CheckerCPU *checker = tc->getCheckerCpuPtr(); 7612461SN/A if (checker) { 7622461SN/A tc->pcStateNoRecord(pc); 7632091SN/A } else { 7641999SN/A tc->pcState(pc); 7652461SN/A } 7662461SN/A } else { 7671999SN/A#ifndef NDEBUG 7681999SN/A if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 7691999SN/A if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 7701999SN/A warn("Unimplemented system register %s write with %#x.\n", 7711999SN/A miscRegName[misc_reg], val); 7721999SN/A else 7731999SN/A panic("Unimplemented system register %s write with %#x.\n", 7741999SN/A miscRegName[misc_reg], val); 7751999SN/A } 7761999SN/A#endif 7772218SN/A switch (unflattenMiscReg(misc_reg)) { 7781999SN/A case MISCREG_CPACR: 7791999SN/A { 7801999SN/A 7811999SN/A const uint32_t ones = (uint32_t)(-1); 7821999SN/A CPACR cpacrMask = 0; 783378SN/A // Only cp10, cp11, and ase are implemented, nothing else should 784378SN/A // be writable 785378SN/A cpacrMask.cp10 = ones; 786378SN/A cpacrMask.cp11 = ones; 787378SN/A cpacrMask.asedis = ones; 788378SN/A 789378SN/A // Security Extensions may limit the writability of CPACR 790378SN/A if (haveSecurity) { 791360SN/A scr = readMiscRegNoEffect(MISCREG_SCR); 792378SN/A CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 793378SN/A if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 794378SN/A NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 795360SN/A // NB: Skipping the full loop, here 7961450SN/A if (!nsacr.cp10) cpacrMask.cp10 = 0; 7973114Sgblack@eecs.umich.edu if (!nsacr.cp11) cpacrMask.cp11 = 0; 798360SN/A } 7992680Sktlim@umich.edu } 8002680Sktlim@umich.edu 8012680Sktlim@umich.edu MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 8022680Sktlim@umich.edu newVal &= cpacrMask; 8032680Sktlim@umich.edu newVal |= old_val & ~cpacrMask; 8042680Sktlim@umich.edu DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 805360SN/A miscRegName[misc_reg], newVal); 8062544SN/A } 8072544SN/A break; 8082544SN/A case MISCREG_CPTR_EL2: 8092544SN/A { 8102544SN/A const uint32_t ones = (uint32_t)(-1); 8112544SN/A CPTR cptrMask = 0; 812360SN/A cptrMask.tcpac = ones; 813360SN/A cptrMask.tta = ones; 8142544SN/A cptrMask.tfp = ones; 8152544SN/A newVal &= cptrMask; 8162544SN/A cptrMask = 0; 8172544SN/A cptrMask.res1_13_12_el2 = ones; 8182544SN/A cptrMask.res1_9_0_el2 = ones; 8192544SN/A newVal |= cptrMask; 8202544SN/A DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 8212544SN/A miscRegName[misc_reg], newVal); 8222544SN/A } 8232544SN/A break; 8242553SN/A case MISCREG_CPTR_EL3: 8251969SN/A { 8262680Sktlim@umich.edu const uint32_t ones = (uint32_t)(-1); 827360SN/A CPTR cptrMask = 0; 828360SN/A cptrMask.tcpac = ones; 8291458SN/A cptrMask.tta = ones; 830360SN/A cptrMask.tfp = ones; 831360SN/A newVal &= cptrMask; 832378SN/A DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 833360SN/A miscRegName[misc_reg], newVal); 8341450SN/A } 8353114Sgblack@eecs.umich.edu break; 8362680Sktlim@umich.edu case MISCREG_CSSELR: 837360SN/A warn_once("The csselr register isn't implemented.\n"); 8382680Sktlim@umich.edu return; 8392680Sktlim@umich.edu 840360SN/A case MISCREG_DC_ZVA_Xt: 841360SN/A warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 8422064SN/A return; 8432064SN/A 8442064SN/A case MISCREG_FPSCR: 8452091SN/A { 8462091SN/A const uint32_t ones = (uint32_t)(-1); 8472064SN/A FPSCR fpscrMask = 0; 848360SN/A fpscrMask.ioc = ones; 8492064SN/A fpscrMask.dzc = ones; 8502064SN/A fpscrMask.ofc = ones; 8512064SN/A fpscrMask.ufc = ones; 8522064SN/A fpscrMask.ixc = ones; 8532064SN/A fpscrMask.idc = ones; 854360SN/A fpscrMask.ioe = ones; 855360SN/A fpscrMask.dze = ones; 8562680Sktlim@umich.edu fpscrMask.ofe = ones; 8571458SN/A fpscrMask.ufe = ones; 858360SN/A fpscrMask.ixe = ones; 859360SN/A fpscrMask.ide = ones; 860378SN/A fpscrMask.len = ones; 861360SN/A fpscrMask.stride = ones; 8621450SN/A fpscrMask.rMode = ones; 8633114Sgblack@eecs.umich.edu fpscrMask.fz = ones; 8642680Sktlim@umich.edu fpscrMask.dn = ones; 865360SN/A fpscrMask.ahp = ones; 8662680Sktlim@umich.edu fpscrMask.qc = ones; 867360SN/A fpscrMask.v = ones; 868360SN/A fpscrMask.c = ones; 869360SN/A fpscrMask.z = ones; 8702091SN/A fpscrMask.n = ones; 8712091SN/A newVal = (newVal & (uint32_t)fpscrMask) | 872360SN/A (readMiscRegNoEffect(MISCREG_FPSCR) & 8732680Sktlim@umich.edu ~(uint32_t)fpscrMask); 874360SN/A tc->getDecoderPtr()->setContext(newVal); 8751458SN/A } 876360SN/A break; 877360SN/A case MISCREG_FPSR: 878360SN/A { 8791999SN/A const uint32_t ones = (uint32_t)(-1); 8801999SN/A FPSCR fpscrMask = 0; 8811999SN/A fpscrMask.ioc = ones; 8823114Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 8832680Sktlim@umich.edu fpscrMask.ofc = ones; 8841999SN/A fpscrMask.ufc = ones; 8851999SN/A fpscrMask.ixc = ones; 8861999SN/A fpscrMask.idc = ones; 8872680Sktlim@umich.edu fpscrMask.qc = ones; 8882400SN/A fpscrMask.v = ones; 8891999SN/A fpscrMask.c = ones; 8902680Sktlim@umich.edu fpscrMask.z = ones; 8912680Sktlim@umich.edu fpscrMask.n = ones; 8921999SN/A newVal = (newVal & (uint32_t)fpscrMask) | 8931999SN/A (readMiscRegNoEffect(MISCREG_FPSCR) & 8941999SN/A ~(uint32_t)fpscrMask); 8951999SN/A misc_reg = MISCREG_FPSCR; 8962091SN/A } 8972091SN/A break; 8981999SN/A case MISCREG_FPCR: 8991999SN/A { 9001999SN/A const uint32_t ones = (uint32_t)(-1); 9011999SN/A FPSCR fpscrMask = 0; 9021999SN/A fpscrMask.len = ones; 9031999SN/A fpscrMask.stride = ones; 9041999SN/A fpscrMask.rMode = ones; 9051999SN/A fpscrMask.fz = ones; 906378SN/A fpscrMask.dn = ones; 907360SN/A fpscrMask.ahp = ones; 9081450SN/A newVal = (newVal & (uint32_t)fpscrMask) | 9093114Sgblack@eecs.umich.edu (readMiscRegNoEffect(MISCREG_FPSCR) & 9102680Sktlim@umich.edu ~(uint32_t)fpscrMask); 911360SN/A misc_reg = MISCREG_FPSCR; 9122680Sktlim@umich.edu } 9132680Sktlim@umich.edu break; 914360SN/A case MISCREG_CPSR_Q: 9152553SN/A { 916360SN/A assert(!(newVal & ~CpsrMaskQ)); 917360SN/A newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 9181969SN/A misc_reg = MISCREG_CPSR; 9191969SN/A } 920360SN/A break; 921360SN/A case MISCREG_FPSCR_QC: 922360SN/A { 9232091SN/A newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 9242091SN/A (newVal & FpscrQcMask); 9252091SN/A misc_reg = MISCREG_FPSCR; 926360SN/A } 927360SN/A break; 928360SN/A case MISCREG_FPSCR_EXC: 929360SN/A { 930360SN/A newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 931360SN/A (newVal & FpscrExcMask); 932360SN/A misc_reg = MISCREG_FPSCR; 933360SN/A } 934360SN/A break; 935360SN/A case MISCREG_FPEXC: 936360SN/A { 937360SN/A // vfpv3 architecture, section B.6.1 of DDI04068 938360SN/A // bit 29 - valid only if fpexc[31] is 0 939360SN/A const uint32_t fpexcMask = 0x60000000; 940360SN/A newVal = (newVal & fpexcMask) | 941360SN/A (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 942360SN/A } 9432680Sktlim@umich.edu break; 944360SN/A case MISCREG_HCR: 9451458SN/A { 946360SN/A if (!haveVirtualization) 947360SN/A return; 9482553SN/A } 9492553SN/A break; 9502553SN/A case MISCREG_IFSR: 9511354SN/A { 952 // ARM ARM (ARM DDI 0406C.b) B4.1.96 953 const uint32_t ifsrMask = 954 mask(31, 13) | mask(11, 11) | mask(8, 6); 955 newVal = newVal & ~ifsrMask; 956 } 957 break; 958 case MISCREG_DFSR: 959 { 960 // ARM ARM (ARM DDI 0406C.b) B4.1.52 961 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 962 newVal = newVal & ~dfsrMask; 963 } 964 break; 965 case MISCREG_AMAIR0: 966 case MISCREG_AMAIR1: 967 { 968 // ARM ARM (ARM DDI 0406C.b) B4.1.5 969 // Valid only with LPAE 970 if (!haveLPAE) 971 return; 972 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 973 } 974 break; 975 case MISCREG_SCR: 976 getITBPtr(tc)->invalidateMiscReg(); 977 getDTBPtr(tc)->invalidateMiscReg(); 978 break; 979 case MISCREG_SCTLR: 980 { 981 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 982 scr = readMiscRegNoEffect(MISCREG_SCR); 983 984 MiscRegIndex sctlr_idx; 985 if (haveSecurity && !highestELIs64 && !scr.ns) { 986 sctlr_idx = MISCREG_SCTLR_S; 987 } else { 988 sctlr_idx = MISCREG_SCTLR_NS; 989 } 990 991 SCTLR sctlr = miscRegs[sctlr_idx]; 992 SCTLR new_sctlr = newVal; 993 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 994 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 995 getITBPtr(tc)->invalidateMiscReg(); 996 getDTBPtr(tc)->invalidateMiscReg(); 997 } 998 case MISCREG_MIDR: 999 case MISCREG_ID_PFR0: 1000 case MISCREG_ID_PFR1: 1001 case MISCREG_ID_DFR0: 1002 case MISCREG_ID_MMFR0: 1003 case MISCREG_ID_MMFR1: 1004 case MISCREG_ID_MMFR2: 1005 case MISCREG_ID_MMFR3: 1006 case MISCREG_ID_ISAR0: 1007 case MISCREG_ID_ISAR1: 1008 case MISCREG_ID_ISAR2: 1009 case MISCREG_ID_ISAR3: 1010 case MISCREG_ID_ISAR4: 1011 case MISCREG_ID_ISAR5: 1012 1013 case MISCREG_MPIDR: 1014 case MISCREG_FPSID: 1015 case MISCREG_TLBTR: 1016 case MISCREG_MVFR0: 1017 case MISCREG_MVFR1: 1018 1019 case MISCREG_ID_AA64AFR0_EL1: 1020 case MISCREG_ID_AA64AFR1_EL1: 1021 case MISCREG_ID_AA64DFR0_EL1: 1022 case MISCREG_ID_AA64DFR1_EL1: 1023 case MISCREG_ID_AA64ISAR0_EL1: 1024 case MISCREG_ID_AA64ISAR1_EL1: 1025 case MISCREG_ID_AA64MMFR0_EL1: 1026 case MISCREG_ID_AA64MMFR1_EL1: 1027 case MISCREG_ID_AA64MMFR2_EL1: 1028 case MISCREG_ID_AA64PFR0_EL1: 1029 case MISCREG_ID_AA64PFR1_EL1: 1030 // ID registers are constants. 1031 return; 1032 1033 // TLB Invalidate All 1034 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1035 { 1036 assert32(tc); 1037 scr = readMiscReg(MISCREG_SCR, tc); 1038 1039 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1040 tlbiOp(tc); 1041 return; 1042 } 1043 // TLB Invalidate All, Inner Shareable 1044 case MISCREG_TLBIALLIS: 1045 { 1046 assert32(tc); 1047 scr = readMiscReg(MISCREG_SCR, tc); 1048 1049 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1050 tlbiOp.broadcast(tc); 1051 return; 1052 } 1053 // Instruction TLB Invalidate All 1054 case MISCREG_ITLBIALL: 1055 { 1056 assert32(tc); 1057 scr = readMiscReg(MISCREG_SCR, tc); 1058 1059 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1060 tlbiOp(tc); 1061 return; 1062 } 1063 // Data TLB Invalidate All 1064 case MISCREG_DTLBIALL: 1065 { 1066 assert32(tc); 1067 scr = readMiscReg(MISCREG_SCR, tc); 1068 1069 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1070 tlbiOp(tc); 1071 return; 1072 } 1073 // TLB Invalidate by VA 1074 // mcr tlbimval(is) is invalidating all matching entries 1075 // regardless of the level of lookup, since in gem5 we cache 1076 // in the tlb the last level of lookup only. 1077 case MISCREG_TLBIMVA: 1078 case MISCREG_TLBIMVAL: 1079 { 1080 assert32(tc); 1081 scr = readMiscReg(MISCREG_SCR, tc); 1082 1083 TLBIMVA tlbiOp(EL1, 1084 haveSecurity && !scr.ns, 1085 mbits(newVal, 31, 12), 1086 bits(newVal, 7,0)); 1087 1088 tlbiOp(tc); 1089 return; 1090 } 1091 // TLB Invalidate by VA, Inner Shareable 1092 case MISCREG_TLBIMVAIS: 1093 case MISCREG_TLBIMVALIS: 1094 { 1095 assert32(tc); 1096 scr = readMiscReg(MISCREG_SCR, tc); 1097 1098 TLBIMVA tlbiOp(EL1, 1099 haveSecurity && !scr.ns, 1100 mbits(newVal, 31, 12), 1101 bits(newVal, 7,0)); 1102 1103 tlbiOp.broadcast(tc); 1104 return; 1105 } 1106 // TLB Invalidate by ASID match 1107 case MISCREG_TLBIASID: 1108 { 1109 assert32(tc); 1110 scr = readMiscReg(MISCREG_SCR, tc); 1111 1112 TLBIASID tlbiOp(EL1, 1113 haveSecurity && !scr.ns, 1114 bits(newVal, 7,0)); 1115 1116 tlbiOp(tc); 1117 return; 1118 } 1119 // TLB Invalidate by ASID match, Inner Shareable 1120 case MISCREG_TLBIASIDIS: 1121 { 1122 assert32(tc); 1123 scr = readMiscReg(MISCREG_SCR, tc); 1124 1125 TLBIASID tlbiOp(EL1, 1126 haveSecurity && !scr.ns, 1127 bits(newVal, 7,0)); 1128 1129 tlbiOp.broadcast(tc); 1130 return; 1131 } 1132 // mcr tlbimvaal(is) is invalidating all matching entries 1133 // regardless of the level of lookup, since in gem5 we cache 1134 // in the tlb the last level of lookup only. 1135 // TLB Invalidate by VA, All ASID 1136 case MISCREG_TLBIMVAA: 1137 case MISCREG_TLBIMVAAL: 1138 { 1139 assert32(tc); 1140 scr = readMiscReg(MISCREG_SCR, tc); 1141 1142 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1143 mbits(newVal, 31,12), false); 1144 1145 tlbiOp(tc); 1146 return; 1147 } 1148 // TLB Invalidate by VA, All ASID, Inner Shareable 1149 case MISCREG_TLBIMVAAIS: 1150 case MISCREG_TLBIMVAALIS: 1151 { 1152 assert32(tc); 1153 scr = readMiscReg(MISCREG_SCR, tc); 1154 1155 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1156 mbits(newVal, 31,12), false); 1157 1158 tlbiOp.broadcast(tc); 1159 return; 1160 } 1161 // mcr tlbimvalh(is) is invalidating all matching entries 1162 // regardless of the level of lookup, since in gem5 we cache 1163 // in the tlb the last level of lookup only. 1164 // TLB Invalidate by VA, Hyp mode 1165 case MISCREG_TLBIMVAH: 1166 case MISCREG_TLBIMVALH: 1167 { 1168 assert32(tc); 1169 scr = readMiscReg(MISCREG_SCR, tc); 1170 1171 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1172 mbits(newVal, 31,12), true); 1173 1174 tlbiOp(tc); 1175 return; 1176 } 1177 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1178 case MISCREG_TLBIMVAHIS: 1179 case MISCREG_TLBIMVALHIS: 1180 { 1181 assert32(tc); 1182 scr = readMiscReg(MISCREG_SCR, tc); 1183 1184 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1185 mbits(newVal, 31,12), true); 1186 1187 tlbiOp.broadcast(tc); 1188 return; 1189 } 1190 // mcr tlbiipas2l(is) is invalidating all matching entries 1191 // regardless of the level of lookup, since in gem5 we cache 1192 // in the tlb the last level of lookup only. 1193 // TLB Invalidate by Intermediate Physical Address, Stage 2 1194 case MISCREG_TLBIIPAS2: 1195 case MISCREG_TLBIIPAS2L: 1196 { 1197 assert32(tc); 1198 scr = readMiscReg(MISCREG_SCR, tc); 1199 1200 TLBIIPA tlbiOp(EL1, 1201 haveSecurity && !scr.ns, 1202 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1203 1204 tlbiOp(tc); 1205 return; 1206 } 1207 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1208 // Inner Shareable 1209 case MISCREG_TLBIIPAS2IS: 1210 case MISCREG_TLBIIPAS2LIS: 1211 { 1212 assert32(tc); 1213 scr = readMiscReg(MISCREG_SCR, tc); 1214 1215 TLBIIPA tlbiOp(EL1, 1216 haveSecurity && !scr.ns, 1217 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1218 1219 tlbiOp.broadcast(tc); 1220 return; 1221 } 1222 // Instruction TLB Invalidate by VA 1223 case MISCREG_ITLBIMVA: 1224 { 1225 assert32(tc); 1226 scr = readMiscReg(MISCREG_SCR, tc); 1227 1228 ITLBIMVA tlbiOp(EL1, 1229 haveSecurity && !scr.ns, 1230 mbits(newVal, 31, 12), 1231 bits(newVal, 7,0)); 1232 1233 tlbiOp(tc); 1234 return; 1235 } 1236 // Data TLB Invalidate by VA 1237 case MISCREG_DTLBIMVA: 1238 { 1239 assert32(tc); 1240 scr = readMiscReg(MISCREG_SCR, tc); 1241 1242 DTLBIMVA tlbiOp(EL1, 1243 haveSecurity && !scr.ns, 1244 mbits(newVal, 31, 12), 1245 bits(newVal, 7,0)); 1246 1247 tlbiOp(tc); 1248 return; 1249 } 1250 // Instruction TLB Invalidate by ASID match 1251 case MISCREG_ITLBIASID: 1252 { 1253 assert32(tc); 1254 scr = readMiscReg(MISCREG_SCR, tc); 1255 1256 ITLBIASID tlbiOp(EL1, 1257 haveSecurity && !scr.ns, 1258 bits(newVal, 7,0)); 1259 1260 tlbiOp(tc); 1261 return; 1262 } 1263 // Data TLB Invalidate by ASID match 1264 case MISCREG_DTLBIASID: 1265 { 1266 assert32(tc); 1267 scr = readMiscReg(MISCREG_SCR, tc); 1268 1269 DTLBIASID tlbiOp(EL1, 1270 haveSecurity && !scr.ns, 1271 bits(newVal, 7,0)); 1272 1273 tlbiOp(tc); 1274 return; 1275 } 1276 // TLB Invalidate All, Non-Secure Non-Hyp 1277 case MISCREG_TLBIALLNSNH: 1278 { 1279 assert32(tc); 1280 1281 TLBIALLN tlbiOp(EL1, false); 1282 tlbiOp(tc); 1283 return; 1284 } 1285 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1286 case MISCREG_TLBIALLNSNHIS: 1287 { 1288 assert32(tc); 1289 1290 TLBIALLN tlbiOp(EL1, false); 1291 tlbiOp.broadcast(tc); 1292 return; 1293 } 1294 // TLB Invalidate All, Hyp mode 1295 case MISCREG_TLBIALLH: 1296 { 1297 assert32(tc); 1298 1299 TLBIALLN tlbiOp(EL1, true); 1300 tlbiOp(tc); 1301 return; 1302 } 1303 // TLB Invalidate All, Hyp mode, Inner Shareable 1304 case MISCREG_TLBIALLHIS: 1305 { 1306 assert32(tc); 1307 1308 TLBIALLN tlbiOp(EL1, true); 1309 tlbiOp.broadcast(tc); 1310 return; 1311 } 1312 // AArch64 TLB Invalidate All, EL3 1313 case MISCREG_TLBI_ALLE3: 1314 { 1315 assert64(tc); 1316 1317 TLBIALL tlbiOp(EL3, true); 1318 tlbiOp(tc); 1319 return; 1320 } 1321 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1322 case MISCREG_TLBI_ALLE3IS: 1323 { 1324 assert64(tc); 1325 1326 TLBIALL tlbiOp(EL3, true); 1327 tlbiOp.broadcast(tc); 1328 return; 1329 } 1330 // @todo: uncomment this to enable Virtualization 1331 // case MISCREG_TLBI_ALLE2IS: 1332 // case MISCREG_TLBI_ALLE2: 1333 // AArch64 TLB Invalidate All, EL1 1334 case MISCREG_TLBI_ALLE1: 1335 case MISCREG_TLBI_VMALLE1: 1336 case MISCREG_TLBI_VMALLS12E1: 1337 // @todo: handle VMID and stage 2 to enable Virtualization 1338 { 1339 assert64(tc); 1340 scr = readMiscReg(MISCREG_SCR, tc); 1341 1342 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1343 tlbiOp(tc); 1344 return; 1345 } 1346 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1347 case MISCREG_TLBI_ALLE1IS: 1348 case MISCREG_TLBI_VMALLE1IS: 1349 case MISCREG_TLBI_VMALLS12E1IS: 1350 // @todo: handle VMID and stage 2 to enable Virtualization 1351 { 1352 assert64(tc); 1353 scr = readMiscReg(MISCREG_SCR, tc); 1354 1355 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1356 tlbiOp.broadcast(tc); 1357 return; 1358 } 1359 // VAEx(IS) and VALEx(IS) are the same because TLBs 1360 // only store entries 1361 // from the last level of translation table walks 1362 // @todo: handle VMID to enable Virtualization 1363 // AArch64 TLB Invalidate by VA, EL3 1364 case MISCREG_TLBI_VAE3_Xt: 1365 case MISCREG_TLBI_VALE3_Xt: 1366 { 1367 assert64(tc); 1368 1369 TLBIMVA tlbiOp(EL3, true, 1370 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1371 0xbeef); 1372 tlbiOp(tc); 1373 return; 1374 } 1375 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1376 case MISCREG_TLBI_VAE3IS_Xt: 1377 case MISCREG_TLBI_VALE3IS_Xt: 1378 { 1379 assert64(tc); 1380 1381 TLBIMVA tlbiOp(EL3, true, 1382 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1383 0xbeef); 1384 1385 tlbiOp.broadcast(tc); 1386 return; 1387 } 1388 // AArch64 TLB Invalidate by VA, EL2 1389 case MISCREG_TLBI_VAE2_Xt: 1390 case MISCREG_TLBI_VALE2_Xt: 1391 { 1392 assert64(tc); 1393 scr = readMiscReg(MISCREG_SCR, tc); 1394 1395 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1396 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1397 0xbeef); 1398 tlbiOp(tc); 1399 return; 1400 } 1401 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1402 case MISCREG_TLBI_VAE2IS_Xt: 1403 case MISCREG_TLBI_VALE2IS_Xt: 1404 { 1405 assert64(tc); 1406 scr = readMiscReg(MISCREG_SCR, tc); 1407 1408 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1409 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1410 0xbeef); 1411 1412 tlbiOp.broadcast(tc); 1413 return; 1414 } 1415 // AArch64 TLB Invalidate by VA, EL1 1416 case MISCREG_TLBI_VAE1_Xt: 1417 case MISCREG_TLBI_VALE1_Xt: 1418 { 1419 assert64(tc); 1420 scr = readMiscReg(MISCREG_SCR, tc); 1421 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1422 bits(newVal, 55, 48); 1423 1424 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1425 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1426 asid); 1427 1428 tlbiOp(tc); 1429 return; 1430 } 1431 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1432 case MISCREG_TLBI_VAE1IS_Xt: 1433 case MISCREG_TLBI_VALE1IS_Xt: 1434 { 1435 assert64(tc); 1436 scr = readMiscReg(MISCREG_SCR, tc); 1437 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1438 bits(newVal, 55, 48); 1439 1440 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1441 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1442 asid); 1443 1444 tlbiOp.broadcast(tc); 1445 return; 1446 } 1447 // AArch64 TLB Invalidate by ASID, EL1 1448 // @todo: handle VMID to enable Virtualization 1449 case MISCREG_TLBI_ASIDE1_Xt: 1450 { 1451 assert64(tc); 1452 scr = readMiscReg(MISCREG_SCR, tc); 1453 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1454 bits(newVal, 55, 48); 1455 1456 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1457 tlbiOp(tc); 1458 return; 1459 } 1460 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1461 case MISCREG_TLBI_ASIDE1IS_Xt: 1462 { 1463 assert64(tc); 1464 scr = readMiscReg(MISCREG_SCR, tc); 1465 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1466 bits(newVal, 55, 48); 1467 1468 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1469 tlbiOp.broadcast(tc); 1470 return; 1471 } 1472 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1473 // entries from the last level of translation table walks 1474 // AArch64 TLB Invalidate by VA, All ASID, EL1 1475 case MISCREG_TLBI_VAAE1_Xt: 1476 case MISCREG_TLBI_VAALE1_Xt: 1477 { 1478 assert64(tc); 1479 scr = readMiscReg(MISCREG_SCR, tc); 1480 1481 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1482 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1483 1484 tlbiOp(tc); 1485 return; 1486 } 1487 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1488 case MISCREG_TLBI_VAAE1IS_Xt: 1489 case MISCREG_TLBI_VAALE1IS_Xt: 1490 { 1491 assert64(tc); 1492 scr = readMiscReg(MISCREG_SCR, tc); 1493 1494 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1495 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1496 1497 tlbiOp.broadcast(tc); 1498 return; 1499 } 1500 // AArch64 TLB Invalidate by Intermediate Physical Address, 1501 // Stage 2, EL1 1502 case MISCREG_TLBI_IPAS2E1_Xt: 1503 case MISCREG_TLBI_IPAS2LE1_Xt: 1504 { 1505 assert64(tc); 1506 scr = readMiscReg(MISCREG_SCR, tc); 1507 1508 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1509 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1510 1511 tlbiOp(tc); 1512 return; 1513 } 1514 // AArch64 TLB Invalidate by Intermediate Physical Address, 1515 // Stage 2, EL1, Inner Shareable 1516 case MISCREG_TLBI_IPAS2E1IS_Xt: 1517 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1518 { 1519 assert64(tc); 1520 scr = readMiscReg(MISCREG_SCR, tc); 1521 1522 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1523 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1524 1525 tlbiOp.broadcast(tc); 1526 return; 1527 } 1528 case MISCREG_ACTLR: 1529 warn("Not doing anything for write of miscreg ACTLR\n"); 1530 break; 1531 1532 case MISCREG_PMXEVTYPER_PMCCFILTR: 1533 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1534 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1535 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1536 pmu->setMiscReg(misc_reg, newVal); 1537 break; 1538 1539 1540 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1541 { 1542 HSTR hstrMask = 0; 1543 hstrMask.tjdbx = 1; 1544 newVal &= ~((uint32_t) hstrMask); 1545 break; 1546 } 1547 case MISCREG_HCPTR: 1548 { 1549 // If a CP bit in NSACR is 0 then the corresponding bit in 1550 // HCPTR is RAO/WI. Same applies to NSASEDIS 1551 secure_lookup = haveSecurity && 1552 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1553 readMiscRegNoEffect(MISCREG_CPSR)); 1554 if (!secure_lookup) { 1555 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1556 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1557 newVal = (newVal & ~mask) | (oldValue & mask); 1558 } 1559 break; 1560 } 1561 case MISCREG_HDFAR: // alias for secure DFAR 1562 misc_reg = MISCREG_DFAR_S; 1563 break; 1564 case MISCREG_HIFAR: // alias for secure IFAR 1565 misc_reg = MISCREG_IFAR_S; 1566 break; 1567 case MISCREG_ATS1CPR: 1568 case MISCREG_ATS1CPW: 1569 case MISCREG_ATS1CUR: 1570 case MISCREG_ATS1CUW: 1571 case MISCREG_ATS12NSOPR: 1572 case MISCREG_ATS12NSOPW: 1573 case MISCREG_ATS12NSOUR: 1574 case MISCREG_ATS12NSOUW: 1575 case MISCREG_ATS1HR: 1576 case MISCREG_ATS1HW: 1577 { 1578 Request::Flags flags = 0; 1579 BaseTLB::Mode mode = BaseTLB::Read; 1580 TLB::ArmTranslationType tranType = TLB::NormalTran; 1581 Fault fault; 1582 switch(misc_reg) { 1583 case MISCREG_ATS1CPR: 1584 flags = TLB::MustBeOne; 1585 tranType = TLB::S1CTran; 1586 mode = BaseTLB::Read; 1587 break; 1588 case MISCREG_ATS1CPW: 1589 flags = TLB::MustBeOne; 1590 tranType = TLB::S1CTran; 1591 mode = BaseTLB::Write; 1592 break; 1593 case MISCREG_ATS1CUR: 1594 flags = TLB::MustBeOne | TLB::UserMode; 1595 tranType = TLB::S1CTran; 1596 mode = BaseTLB::Read; 1597 break; 1598 case MISCREG_ATS1CUW: 1599 flags = TLB::MustBeOne | TLB::UserMode; 1600 tranType = TLB::S1CTran; 1601 mode = BaseTLB::Write; 1602 break; 1603 case MISCREG_ATS12NSOPR: 1604 if (!haveSecurity) 1605 panic("Security Extensions required for ATS12NSOPR"); 1606 flags = TLB::MustBeOne; 1607 tranType = TLB::S1S2NsTran; 1608 mode = BaseTLB::Read; 1609 break; 1610 case MISCREG_ATS12NSOPW: 1611 if (!haveSecurity) 1612 panic("Security Extensions required for ATS12NSOPW"); 1613 flags = TLB::MustBeOne; 1614 tranType = TLB::S1S2NsTran; 1615 mode = BaseTLB::Write; 1616 break; 1617 case MISCREG_ATS12NSOUR: 1618 if (!haveSecurity) 1619 panic("Security Extensions required for ATS12NSOUR"); 1620 flags = TLB::MustBeOne | TLB::UserMode; 1621 tranType = TLB::S1S2NsTran; 1622 mode = BaseTLB::Read; 1623 break; 1624 case MISCREG_ATS12NSOUW: 1625 if (!haveSecurity) 1626 panic("Security Extensions required for ATS12NSOUW"); 1627 flags = TLB::MustBeOne | TLB::UserMode; 1628 tranType = TLB::S1S2NsTran; 1629 mode = BaseTLB::Write; 1630 break; 1631 case MISCREG_ATS1HR: // only really useful from secure mode. 1632 flags = TLB::MustBeOne; 1633 tranType = TLB::HypMode; 1634 mode = BaseTLB::Read; 1635 break; 1636 case MISCREG_ATS1HW: 1637 flags = TLB::MustBeOne; 1638 tranType = TLB::HypMode; 1639 mode = BaseTLB::Write; 1640 break; 1641 } 1642 // If we're in timing mode then doing the translation in 1643 // functional mode then we're slightly distorting performance 1644 // results obtained from simulations. The translation should be 1645 // done in the same mode the core is running in. NOTE: This 1646 // can't be an atomic translation because that causes problems 1647 // with unexpected atomic snoop requests. 1648 warn("Translating via %s in functional mode! Fix Me!\n", 1649 miscRegName[misc_reg]); 1650 1651 auto req = std::make_shared<Request>( 1652 0, val, 0, flags, Request::funcMasterId, 1653 tc->pcState().pc(), tc->contextId()); 1654 1655 fault = getDTBPtr(tc)->translateFunctional( 1656 req, tc, mode, tranType); 1657 1658 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1659 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1660 1661 MiscReg newVal; 1662 if (fault == NoFault) { 1663 Addr paddr = req->getPaddr(); 1664 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1665 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1666 newVal = (paddr & mask(39, 12)) | 1667 (getDTBPtr(tc)->getAttr()); 1668 } else { 1669 newVal = (paddr & 0xfffff000) | 1670 (getDTBPtr(tc)->getAttr()); 1671 } 1672 DPRINTF(MiscRegs, 1673 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1674 val, newVal); 1675 } else { 1676 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1677 armFault->update(tc); 1678 // Set fault bit and FSR 1679 FSR fsr = armFault->getFsr(tc); 1680 1681 newVal = ((fsr >> 9) & 1) << 11; 1682 if (newVal) { 1683 // LPAE - rearange fault status 1684 newVal |= ((fsr >> 0) & 0x3f) << 1; 1685 } else { 1686 // VMSA - rearange fault status 1687 newVal |= ((fsr >> 0) & 0xf) << 1; 1688 newVal |= ((fsr >> 10) & 0x1) << 5; 1689 newVal |= ((fsr >> 12) & 0x1) << 6; 1690 } 1691 newVal |= 0x1; // F bit 1692 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1693 newVal |= armFault->isStage2() ? 0x200 : 0; 1694 DPRINTF(MiscRegs, 1695 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1696 val, fsr, newVal); 1697 } 1698 setMiscRegNoEffect(MISCREG_PAR, newVal); 1699 return; 1700 } 1701 case MISCREG_TTBCR: 1702 { 1703 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1704 const uint32_t ones = (uint32_t)(-1); 1705 TTBCR ttbcrMask = 0; 1706 TTBCR ttbcrNew = newVal; 1707 1708 // ARM DDI 0406C.b, ARMv7-32 1709 ttbcrMask.n = ones; // T0SZ 1710 if (haveSecurity) { 1711 ttbcrMask.pd0 = ones; 1712 ttbcrMask.pd1 = ones; 1713 } 1714 ttbcrMask.epd0 = ones; 1715 ttbcrMask.irgn0 = ones; 1716 ttbcrMask.orgn0 = ones; 1717 ttbcrMask.sh0 = ones; 1718 ttbcrMask.ps = ones; // T1SZ 1719 ttbcrMask.a1 = ones; 1720 ttbcrMask.epd1 = ones; 1721 ttbcrMask.irgn1 = ones; 1722 ttbcrMask.orgn1 = ones; 1723 ttbcrMask.sh1 = ones; 1724 if (haveLPAE) 1725 ttbcrMask.eae = ones; 1726 1727 if (haveLPAE && ttbcrNew.eae) { 1728 newVal = newVal & ttbcrMask; 1729 } else { 1730 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1731 } 1732 // Invalidate TLB MiscReg 1733 getITBPtr(tc)->invalidateMiscReg(); 1734 getDTBPtr(tc)->invalidateMiscReg(); 1735 break; 1736 } 1737 case MISCREG_TTBR0: 1738 case MISCREG_TTBR1: 1739 { 1740 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1741 if (haveLPAE) { 1742 if (ttbcr.eae) { 1743 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1744 // ARMv8 AArch32 bit 63-56 only 1745 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1746 newVal = (newVal & (~ttbrMask)); 1747 } 1748 } 1749 // Invalidate TLB MiscReg 1750 getITBPtr(tc)->invalidateMiscReg(); 1751 getDTBPtr(tc)->invalidateMiscReg(); 1752 break; 1753 } 1754 case MISCREG_SCTLR_EL1: 1755 case MISCREG_CONTEXTIDR: 1756 case MISCREG_PRRR: 1757 case MISCREG_NMRR: 1758 case MISCREG_MAIR0: 1759 case MISCREG_MAIR1: 1760 case MISCREG_DACR: 1761 case MISCREG_VTTBR: 1762 case MISCREG_SCR_EL3: 1763 case MISCREG_HCR_EL2: 1764 case MISCREG_TCR_EL1: 1765 case MISCREG_TCR_EL2: 1766 case MISCREG_TCR_EL3: 1767 case MISCREG_SCTLR_EL2: 1768 case MISCREG_SCTLR_EL3: 1769 case MISCREG_HSCTLR: 1770 case MISCREG_TTBR0_EL1: 1771 case MISCREG_TTBR1_EL1: 1772 case MISCREG_TTBR0_EL2: 1773 case MISCREG_TTBR1_EL2: 1774 case MISCREG_TTBR0_EL3: 1775 getITBPtr(tc)->invalidateMiscReg(); 1776 getDTBPtr(tc)->invalidateMiscReg(); 1777 break; 1778 case MISCREG_NZCV: 1779 { 1780 CPSR cpsr = val; 1781 1782 tc->setCCReg(CCREG_NZ, cpsr.nz); 1783 tc->setCCReg(CCREG_C, cpsr.c); 1784 tc->setCCReg(CCREG_V, cpsr.v); 1785 } 1786 break; 1787 case MISCREG_DAIF: 1788 { 1789 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1790 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1791 newVal = cpsr; 1792 misc_reg = MISCREG_CPSR; 1793 } 1794 break; 1795 case MISCREG_SP_EL0: 1796 tc->setIntReg(INTREG_SP0, newVal); 1797 break; 1798 case MISCREG_SP_EL1: 1799 tc->setIntReg(INTREG_SP1, newVal); 1800 break; 1801 case MISCREG_SP_EL2: 1802 tc->setIntReg(INTREG_SP2, newVal); 1803 break; 1804 case MISCREG_SPSEL: 1805 { 1806 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1807 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1808 newVal = cpsr; 1809 misc_reg = MISCREG_CPSR; 1810 } 1811 break; 1812 case MISCREG_CURRENTEL: 1813 { 1814 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1815 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1816 newVal = cpsr; 1817 misc_reg = MISCREG_CPSR; 1818 } 1819 break; 1820 case MISCREG_AT_S1E1R_Xt: 1821 case MISCREG_AT_S1E1W_Xt: 1822 case MISCREG_AT_S1E0R_Xt: 1823 case MISCREG_AT_S1E0W_Xt: 1824 case MISCREG_AT_S1E2R_Xt: 1825 case MISCREG_AT_S1E2W_Xt: 1826 case MISCREG_AT_S12E1R_Xt: 1827 case MISCREG_AT_S12E1W_Xt: 1828 case MISCREG_AT_S12E0R_Xt: 1829 case MISCREG_AT_S12E0W_Xt: 1830 case MISCREG_AT_S1E3R_Xt: 1831 case MISCREG_AT_S1E3W_Xt: 1832 { 1833 RequestPtr req = std::make_shared<Request>(); 1834 Request::Flags flags = 0; 1835 BaseTLB::Mode mode = BaseTLB::Read; 1836 TLB::ArmTranslationType tranType = TLB::NormalTran; 1837 Fault fault; 1838 switch(misc_reg) { 1839 case MISCREG_AT_S1E1R_Xt: 1840 flags = TLB::MustBeOne; 1841 tranType = TLB::S1E1Tran; 1842 mode = BaseTLB::Read; 1843 break; 1844 case MISCREG_AT_S1E1W_Xt: 1845 flags = TLB::MustBeOne; 1846 tranType = TLB::S1E1Tran; 1847 mode = BaseTLB::Write; 1848 break; 1849 case MISCREG_AT_S1E0R_Xt: 1850 flags = TLB::MustBeOne | TLB::UserMode; 1851 tranType = TLB::S1E0Tran; 1852 mode = BaseTLB::Read; 1853 break; 1854 case MISCREG_AT_S1E0W_Xt: 1855 flags = TLB::MustBeOne | TLB::UserMode; 1856 tranType = TLB::S1E0Tran; 1857 mode = BaseTLB::Write; 1858 break; 1859 case MISCREG_AT_S1E2R_Xt: 1860 flags = TLB::MustBeOne; 1861 tranType = TLB::S1E2Tran; 1862 mode = BaseTLB::Read; 1863 break; 1864 case MISCREG_AT_S1E2W_Xt: 1865 flags = TLB::MustBeOne; 1866 tranType = TLB::S1E2Tran; 1867 mode = BaseTLB::Write; 1868 break; 1869 case MISCREG_AT_S12E0R_Xt: 1870 flags = TLB::MustBeOne | TLB::UserMode; 1871 tranType = TLB::S12E0Tran; 1872 mode = BaseTLB::Read; 1873 break; 1874 case MISCREG_AT_S12E0W_Xt: 1875 flags = TLB::MustBeOne | TLB::UserMode; 1876 tranType = TLB::S12E0Tran; 1877 mode = BaseTLB::Write; 1878 break; 1879 case MISCREG_AT_S12E1R_Xt: 1880 flags = TLB::MustBeOne; 1881 tranType = TLB::S12E1Tran; 1882 mode = BaseTLB::Read; 1883 break; 1884 case MISCREG_AT_S12E1W_Xt: 1885 flags = TLB::MustBeOne; 1886 tranType = TLB::S12E1Tran; 1887 mode = BaseTLB::Write; 1888 break; 1889 case MISCREG_AT_S1E3R_Xt: 1890 flags = TLB::MustBeOne; 1891 tranType = TLB::S1E3Tran; 1892 mode = BaseTLB::Read; 1893 break; 1894 case MISCREG_AT_S1E3W_Xt: 1895 flags = TLB::MustBeOne; 1896 tranType = TLB::S1E3Tran; 1897 mode = BaseTLB::Write; 1898 break; 1899 } 1900 // If we're in timing mode then doing the translation in 1901 // functional mode then we're slightly distorting performance 1902 // results obtained from simulations. The translation should be 1903 // done in the same mode the core is running in. NOTE: This 1904 // can't be an atomic translation because that causes problems 1905 // with unexpected atomic snoop requests. 1906 warn("Translating via %s in functional mode! Fix Me!\n", 1907 miscRegName[misc_reg]); 1908 1909 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1910 tc->pcState().pc()); 1911 req->setContext(tc->contextId()); 1912 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1913 tranType); 1914 1915 MiscReg newVal; 1916 if (fault == NoFault) { 1917 Addr paddr = req->getPaddr(); 1918 uint64_t attr = getDTBPtr(tc)->getAttr(); 1919 uint64_t attr1 = attr >> 56; 1920 if (!attr1 || attr1 ==0x44) { 1921 attr |= 0x100; 1922 attr &= ~ uint64_t(0x80); 1923 } 1924 newVal = (paddr & mask(47, 12)) | attr; 1925 DPRINTF(MiscRegs, 1926 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1927 val, newVal); 1928 } else { 1929 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1930 armFault->update(tc); 1931 // Set fault bit and FSR 1932 FSR fsr = armFault->getFsr(tc); 1933 1934 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1935 if (cpsr.width) { // AArch32 1936 newVal = ((fsr >> 9) & 1) << 11; 1937 // rearrange fault status 1938 newVal |= ((fsr >> 0) & 0x3f) << 1; 1939 newVal |= 0x1; // F bit 1940 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1941 newVal |= armFault->isStage2() ? 0x200 : 0; 1942 } else { // AArch64 1943 newVal = 1; // F bit 1944 newVal |= fsr << 1; // FST 1945 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1946 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1947 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1948 newVal |= 1 << 11; // RES1 1949 } 1950 DPRINTF(MiscRegs, 1951 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1952 val, fsr, newVal); 1953 } 1954 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1955 return; 1956 } 1957 case MISCREG_SPSR_EL3: 1958 case MISCREG_SPSR_EL2: 1959 case MISCREG_SPSR_EL1: 1960 // Force bits 23:21 to 0 1961 newVal = val & ~(0x7 << 21); 1962 break; 1963 case MISCREG_L2CTLR: 1964 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1965 miscRegName[misc_reg], uint32_t(val)); 1966 break; 1967 1968 // Generic Timer registers 1969 case MISCREG_CNTHV_CTL_EL2: 1970 case MISCREG_CNTHV_CVAL_EL2: 1971 case MISCREG_CNTHV_TVAL_EL2: 1972 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1973 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1974 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1975 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1976 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1977 break; 1978 } 1979 } 1980 setMiscRegNoEffect(misc_reg, newVal); 1981} 1982 1983BaseISADevice & 1984ISA::getGenericTimer(ThreadContext *tc) 1985{ 1986 // We only need to create an ISA interface the first time we try 1987 // to access the timer. 1988 if (timer) 1989 return *timer.get(); 1990 1991 assert(system); 1992 GenericTimer *generic_timer(system->getGenericTimer()); 1993 if (!generic_timer) { 1994 panic("Trying to get a generic timer from a system that hasn't " 1995 "been configured to use a generic timer.\n"); 1996 } 1997 1998 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1999 timer->setThreadContext(tc); 2000 2001 return *timer.get(); 2002} 2003 2004} 2005 2006ArmISA::ISA * 2007ArmISAParams::create() 2008{ 2009 return new ArmISA::ISA(this); 2010} 2011