isa.cc revision 13393
17405SAli.Saidi@ARM.com/* 212667Schuan.zhu@arm.com * Copyright (c) 2010-2018 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 439050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 4412406Sgabeblack@google.com#include "arch/arm/tlb.hh" 4512605Sgiacomo.travaglini@arm.com#include "arch/arm/tlbi_op.hh" 4611793Sbrandon.potter@amd.com#include "cpu/base.hh" 478887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 488232Snate@binkert.org#include "debug/Arm.hh" 498232Snate@binkert.org#include "debug/MiscRegs.hh" 5010844Sandreas.sandberg@arm.com#include "dev/arm/generic_timer.hh" 519384SAndreas.Sandberg@arm.com#include "params/ArmISA.hh" 527678Sgblack@eecs.umich.edu#include "sim/faults.hh" 538059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 548284SAli.Saidi@ARM.com#include "sim/system.hh" 557405SAli.Saidi@ARM.com 567405SAli.Saidi@ARM.comnamespace ArmISA 577405SAli.Saidi@ARM.com{ 587405SAli.Saidi@ARM.com 599384SAndreas.Sandberg@arm.comISA::ISA(Params *p) 6010461SAndreas.Sandberg@ARM.com : SimObject(p), 6110461SAndreas.Sandberg@ARM.com system(NULL), 6211165SRekai.GonzalezAlberquilla@arm.com _decoderFlavour(p->decoderFlavour), 6312109SRekai.GonzalezAlberquilla@arm.com _vecRegRenameMode(p->vecRegRenameMode), 6412714Sgiacomo.travaglini@arm.com pmu(p->pmu), 6512714Sgiacomo.travaglini@arm.com impdefAsNop(p->impdef_nop) 669384SAndreas.Sandberg@arm.com{ 6711770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_RST] = 0; 6810037SARM gem5 Developers 6910461SAndreas.Sandberg@ARM.com // Hook up a dummy device if we haven't been configured with a 7010461SAndreas.Sandberg@ARM.com // real PMU. By using a dummy device, we don't need to check that 7110461SAndreas.Sandberg@ARM.com // the PMU exist every time we try to access a PMU register. 7210461SAndreas.Sandberg@ARM.com if (!pmu) 7310461SAndreas.Sandberg@ARM.com pmu = &dummyDevice; 7410461SAndreas.Sandberg@ARM.com 7510609Sandreas.sandberg@arm.com // Give all ISA devices a pointer to this ISA 7610609Sandreas.sandberg@arm.com pmu->setISA(this); 7710609Sandreas.sandberg@arm.com 7810037SARM gem5 Developers system = dynamic_cast<ArmSystem *>(p->system); 7910037SARM gem5 Developers 8010037SARM gem5 Developers // Cache system-level properties 8110037SARM gem5 Developers if (FullSystem && system) { 8211771SCurtis.Dunham@arm.com highestELIs64 = system->highestELIs64(); 8310037SARM gem5 Developers haveSecurity = system->haveSecurity(); 8410037SARM gem5 Developers haveLPAE = system->haveLPAE(); 8513173Sgiacomo.travaglini@arm.com haveCrypto = system->haveCrypto(); 8610037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 8710037SARM gem5 Developers haveLargeAsid64 = system->haveLargeAsid64(); 8813114Sgiacomo.travaglini@arm.com physAddrRange = system->physAddrRange(); 8910037SARM gem5 Developers } else { 9011771SCurtis.Dunham@arm.com highestELIs64 = true; // ArmSystem::highestELIs64 does the same 9110037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 9213173Sgiacomo.travaglini@arm.com haveCrypto = false; 9310037SARM gem5 Developers haveLargeAsid64 = false; 9413114Sgiacomo.travaglini@arm.com physAddrRange = 32; // dummy value 9510037SARM gem5 Developers } 9610037SARM gem5 Developers 9712477SCurtis.Dunham@arm.com initializeMiscRegMetadata(); 9810037SARM gem5 Developers preUnflattenMiscReg(); 9910037SARM gem5 Developers 1009384SAndreas.Sandberg@arm.com clear(); 1019384SAndreas.Sandberg@arm.com} 1029384SAndreas.Sandberg@arm.com 10312479SCurtis.Dunham@arm.comstd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 10412479SCurtis.Dunham@arm.com 1059384SAndreas.Sandberg@arm.comconst ArmISAParams * 1069384SAndreas.Sandberg@arm.comISA::params() const 1079384SAndreas.Sandberg@arm.com{ 1089384SAndreas.Sandberg@arm.com return dynamic_cast<const Params *>(_params); 1099384SAndreas.Sandberg@arm.com} 1109384SAndreas.Sandberg@arm.com 1117427Sgblack@eecs.umich.eduvoid 1127427Sgblack@eecs.umich.eduISA::clear() 1137427Sgblack@eecs.umich.edu{ 1149385SAndreas.Sandberg@arm.com const Params *p(params()); 1159385SAndreas.Sandberg@arm.com 1167427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 1177427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 11810037SARM gem5 Developers 11913114Sgiacomo.travaglini@arm.com initID32(p); 12010037SARM gem5 Developers 12113114Sgiacomo.travaglini@arm.com // We always initialize AArch64 ID registers even 12213114Sgiacomo.travaglini@arm.com // if we are in AArch32. This is done since if we 12313114Sgiacomo.travaglini@arm.com // are in SE mode we don't know if our ArmProcess is 12413114Sgiacomo.travaglini@arm.com // AArch32 or AArch64 12513114Sgiacomo.travaglini@arm.com initID64(p); 12612690Sgiacomo.travaglini@arm.com 12710037SARM gem5 Developers // Start with an event in the mailbox 1287427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 1297427Sgblack@eecs.umich.edu 13010037SARM gem5 Developers // Separate Instruction and Data TLBs 1317427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 1327427Sgblack@eecs.umich.edu 1337427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 1347427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 1357427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 1367427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 1377427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 1387427Sgblack@eecs.umich.edu mvfr0.divide = 1; 1397427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 1407427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 1417427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 1427427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 1437427Sgblack@eecs.umich.edu 1447427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1457427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1467427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1477427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1487427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1497427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1507427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1517427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1527427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1537427Sgblack@eecs.umich.edu 1547436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1557436Sdam.sunwoo@arm.com 15610037SARM gem5 Developers // @todo: PRRR and NMRR in secure state? 15710037SARM gem5 Developers miscRegs[MISCREG_PRRR_NS] = 1587436Sdam.sunwoo@arm.com (1 << 19) | // 19 1597436Sdam.sunwoo@arm.com (0 << 18) | // 18 1607436Sdam.sunwoo@arm.com (0 << 17) | // 17 1617436Sdam.sunwoo@arm.com (1 << 16) | // 16 1627436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1637436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1647436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1657436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1667436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1677436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1687436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1697436Sdam.sunwoo@arm.com 0; // 1:0 17013393Sgiacomo.travaglini@arm.com 17110037SARM gem5 Developers miscRegs[MISCREG_NMRR_NS] = 1727436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1737436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1747436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1757436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1767436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1777436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1787436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 1797436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 1807436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1817436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1827436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 1837436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 1847436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1857436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 1867436Sdam.sunwoo@arm.com 0; // 1:0 1877436Sdam.sunwoo@arm.com 18813393Sgiacomo.travaglini@arm.com if (FullSystem && system->highestELIs64()) { 18913393Sgiacomo.travaglini@arm.com // Initialize AArch64 state 19013393Sgiacomo.travaglini@arm.com clear64(p); 19113393Sgiacomo.travaglini@arm.com return; 19213393Sgiacomo.travaglini@arm.com } 19313393Sgiacomo.travaglini@arm.com 19413393Sgiacomo.travaglini@arm.com // Initialize AArch32 state... 19513393Sgiacomo.travaglini@arm.com clear32(p, sctlr_rst); 19613393Sgiacomo.travaglini@arm.com} 19713393Sgiacomo.travaglini@arm.com 19813393Sgiacomo.travaglini@arm.comvoid 19913393Sgiacomo.travaglini@arm.comISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 20013393Sgiacomo.travaglini@arm.com{ 20113393Sgiacomo.travaglini@arm.com CPSR cpsr = 0; 20213393Sgiacomo.travaglini@arm.com cpsr.mode = MODE_USER; 20313393Sgiacomo.travaglini@arm.com 20413393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_CPSR] = cpsr; 20513393Sgiacomo.travaglini@arm.com updateRegMap(cpsr); 20613393Sgiacomo.travaglini@arm.com 20713393Sgiacomo.travaglini@arm.com SCTLR sctlr = 0; 20813393Sgiacomo.travaglini@arm.com sctlr.te = (bool) sctlr_rst.te; 20913393Sgiacomo.travaglini@arm.com sctlr.nmfi = (bool) sctlr_rst.nmfi; 21013393Sgiacomo.travaglini@arm.com sctlr.v = (bool) sctlr_rst.v; 21113393Sgiacomo.travaglini@arm.com sctlr.u = 1; 21213393Sgiacomo.travaglini@arm.com sctlr.xp = 1; 21313393Sgiacomo.travaglini@arm.com sctlr.rao2 = 1; 21413393Sgiacomo.travaglini@arm.com sctlr.rao3 = 1; 21513393Sgiacomo.travaglini@arm.com sctlr.rao4 = 0xf; // SCTLR[6:3] 21613393Sgiacomo.travaglini@arm.com sctlr.uci = 1; 21713393Sgiacomo.travaglini@arm.com sctlr.dze = 1; 21813393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_SCTLR_NS] = sctlr; 21913393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 22013393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_HCPTR] = 0; 22113393Sgiacomo.travaglini@arm.com 2227644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 2238147SAli.Saidi@ARM.com 2249385SAndreas.Sandberg@arm.com miscRegs[MISCREG_FPSID] = p->fpsid; 2259385SAndreas.Sandberg@arm.com 22610037SARM gem5 Developers if (haveLPAE) { 22710037SARM gem5 Developers TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 22810037SARM gem5 Developers ttbcr.eae = 0; 22910037SARM gem5 Developers miscRegs[MISCREG_TTBCR_NS] = ttbcr; 23010037SARM gem5 Developers // Enforce consistency with system-level settings 23110037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 23210037SARM gem5 Developers } 23310037SARM gem5 Developers 23410037SARM gem5 Developers if (haveSecurity) { 23510037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] = sctlr; 23610037SARM gem5 Developers miscRegs[MISCREG_SCR] = 0; 23710037SARM gem5 Developers miscRegs[MISCREG_VBAR_S] = 0; 23810037SARM gem5 Developers } else { 23910037SARM gem5 Developers // we're always non-secure 24010037SARM gem5 Developers miscRegs[MISCREG_SCR] = 1; 24110037SARM gem5 Developers } 2428147SAli.Saidi@ARM.com 2437427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 2447427Sgblack@eecs.umich.edu} 2457427Sgblack@eecs.umich.edu 24610037SARM gem5 Developersvoid 24710037SARM gem5 DevelopersISA::clear64(const ArmISAParams *p) 24810037SARM gem5 Developers{ 24910037SARM gem5 Developers CPSR cpsr = 0; 25010037SARM gem5 Developers Addr rvbar = system->resetAddr64(); 25110037SARM gem5 Developers switch (system->highestEL()) { 25210037SARM gem5 Developers // Set initial EL to highest implemented EL using associated stack 25310037SARM gem5 Developers // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 25410037SARM gem5 Developers // value 25510037SARM gem5 Developers case EL3: 25610037SARM gem5 Developers cpsr.mode = MODE_EL3H; 25710037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL3] = rvbar; 25810037SARM gem5 Developers break; 25910037SARM gem5 Developers case EL2: 26010037SARM gem5 Developers cpsr.mode = MODE_EL2H; 26110037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL2] = rvbar; 26210037SARM gem5 Developers break; 26310037SARM gem5 Developers case EL1: 26410037SARM gem5 Developers cpsr.mode = MODE_EL1H; 26510037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL1] = rvbar; 26610037SARM gem5 Developers break; 26710037SARM gem5 Developers default: 26810037SARM gem5 Developers panic("Invalid highest implemented exception level"); 26910037SARM gem5 Developers break; 27010037SARM gem5 Developers } 27110037SARM gem5 Developers 27210037SARM gem5 Developers // Initialize rest of CPSR 27310037SARM gem5 Developers cpsr.daif = 0xf; // Mask all interrupts 27410037SARM gem5 Developers cpsr.ss = 0; 27510037SARM gem5 Developers cpsr.il = 0; 27610037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 27710037SARM gem5 Developers updateRegMap(cpsr); 27810037SARM gem5 Developers 27910037SARM gem5 Developers // Initialize other control registers 28010037SARM gem5 Developers miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 28110037SARM gem5 Developers if (haveSecurity) { 28211770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 28310037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 28411574SCurtis.Dunham@arm.com } else if (haveVirtualization) { 28511770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL2 (by mapping) 28611770SCurtis.Dunham@arm.com miscRegs[MISCREG_HSCTLR] = 0x30c50830; 28710037SARM gem5 Developers } else { 28811770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL1 (by mapping) 28911770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 29010037SARM gem5 Developers // Always non-secure 29110037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 1; 29210037SARM gem5 Developers } 29313114Sgiacomo.travaglini@arm.com} 29410037SARM gem5 Developers 29513114Sgiacomo.travaglini@arm.comvoid 29613114Sgiacomo.travaglini@arm.comISA::initID32(const ArmISAParams *p) 29713114Sgiacomo.travaglini@arm.com{ 29813114Sgiacomo.travaglini@arm.com // Initialize configurable default values 29913114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_MIDR] = p->midr; 30013114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_MIDR_EL1] = p->midr; 30113114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_VPIDR] = p->midr; 30213114Sgiacomo.travaglini@arm.com 30313114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 30413114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 30513114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 30613114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 30713114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 30813114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 30913114Sgiacomo.travaglini@arm.com 31013114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 31113114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 31213114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 31313114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 31413114Sgiacomo.travaglini@arm.com} 31513114Sgiacomo.travaglini@arm.com 31613114Sgiacomo.travaglini@arm.comvoid 31713114Sgiacomo.travaglini@arm.comISA::initID64(const ArmISAParams *p) 31813114Sgiacomo.travaglini@arm.com{ 31910037SARM gem5 Developers // Initialize configurable id registers 32010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 32110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 32210461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 32310461SAndreas.Sandberg@ARM.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 32410461SAndreas.Sandberg@ARM.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 32510461SAndreas.Sandberg@ARM.com 32610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 32710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 32810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 32910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 33010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 33113116Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 33210037SARM gem5 Developers 33310461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0_EL1] = 33410461SAndreas.Sandberg@ARM.com (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 33510461SAndreas.Sandberg@ARM.com 33610461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 33710461SAndreas.Sandberg@ARM.com 33810037SARM gem5 Developers // Enforce consistency with system-level settings... 33910037SARM gem5 Developers 34010037SARM gem5 Developers // EL3 34110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 34210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 34311574SCurtis.Dunham@arm.com haveSecurity ? 0x2 : 0x0); 34410037SARM gem5 Developers // EL2 34510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 34610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 34711574SCurtis.Dunham@arm.com haveVirtualization ? 0x2 : 0x0); 34810037SARM gem5 Developers // Large ASID support 34910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 35010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 35110037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 35210037SARM gem5 Developers // Physical address size 35310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 35410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 35513114Sgiacomo.travaglini@arm.com encodePhysAddrRange64(physAddrRange)); 35613173Sgiacomo.travaglini@arm.com // Crypto 35713173Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 35813173Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 35913173Sgiacomo.travaglini@arm.com haveCrypto ? 0x1112 : 0x0); 36010037SARM gem5 Developers} 36110037SARM gem5 Developers 36212972Sandreas.sandberg@arm.comvoid 36312972Sandreas.sandberg@arm.comISA::startup(ThreadContext *tc) 36412972Sandreas.sandberg@arm.com{ 36512972Sandreas.sandberg@arm.com pmu->setThreadContext(tc); 36612972Sandreas.sandberg@arm.com 36712972Sandreas.sandberg@arm.com} 36812972Sandreas.sandberg@arm.com 36912972Sandreas.sandberg@arm.com 3707405SAli.Saidi@ARM.comMiscReg 37110035Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg) const 3727405SAli.Saidi@ARM.com{ 3737405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 3747614Sminkyu.jeong@arm.com 37512478SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 37612478SCurtis.Dunham@arm.com const auto &map = getMiscIndices(misc_reg); 37712478SCurtis.Dunham@arm.com int lower = map.first, upper = map.second; 37812478SCurtis.Dunham@arm.com // NB!: apply architectural masks according to desired register, 37912478SCurtis.Dunham@arm.com // despite possibly getting value from different (mapped) register. 38012478SCurtis.Dunham@arm.com auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 38112478SCurtis.Dunham@arm.com |(miscRegs[upper] << 32)); 38212478SCurtis.Dunham@arm.com if (val & reg.res0()) { 38312478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 38412478SCurtis.Dunham@arm.com miscRegName[misc_reg], val & reg.res0()); 38512478SCurtis.Dunham@arm.com } 38612478SCurtis.Dunham@arm.com if ((val & reg.res1()) != reg.res1()) { 38712478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 38812478SCurtis.Dunham@arm.com miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 38912478SCurtis.Dunham@arm.com } 39012478SCurtis.Dunham@arm.com return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 3917405SAli.Saidi@ARM.com} 3927405SAli.Saidi@ARM.com 3937405SAli.Saidi@ARM.com 3947405SAli.Saidi@ARM.comMiscReg 3957405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 3967405SAli.Saidi@ARM.com{ 39710037SARM gem5 Developers CPSR cpsr = 0; 39810037SARM gem5 Developers PCState pc = 0; 39910037SARM gem5 Developers SCR scr = 0; 4009050Schander.sudanthi@arm.com 4017405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 40210037SARM gem5 Developers cpsr = miscRegs[misc_reg]; 40310037SARM gem5 Developers pc = tc->pcState(); 4047720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 4057720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 4067405SAli.Saidi@ARM.com return cpsr; 4077405SAli.Saidi@ARM.com } 4087757SAli.Saidi@ARM.com 40910037SARM gem5 Developers#ifndef NDEBUG 41010037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 41110037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 41210037SARM gem5 Developers warn("Unimplemented system register %s read.\n", 41310037SARM gem5 Developers miscRegName[misc_reg]); 41410037SARM gem5 Developers else 41510037SARM gem5 Developers panic("Unimplemented system register %s read.\n", 41610037SARM gem5 Developers miscRegName[misc_reg]); 41710037SARM gem5 Developers } 41810037SARM gem5 Developers#endif 41910037SARM gem5 Developers 42010037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 42110037SARM gem5 Developers case MISCREG_HCR: 42210037SARM gem5 Developers { 42310037SARM gem5 Developers if (!haveVirtualization) 42410037SARM gem5 Developers return 0; 42510037SARM gem5 Developers else 42610037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HCR); 42710037SARM gem5 Developers } 42810037SARM gem5 Developers case MISCREG_CPACR: 42910037SARM gem5 Developers { 43010037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 43110037SARM gem5 Developers CPACR cpacrMask = 0; 43210037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 43310037SARM gem5 Developers // be readable? (straight copy from the write code) 43410037SARM gem5 Developers cpacrMask.cp10 = ones; 43510037SARM gem5 Developers cpacrMask.cp11 = ones; 43610037SARM gem5 Developers cpacrMask.asedis = ones; 43710037SARM gem5 Developers 43810037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 43910037SARM gem5 Developers if (haveSecurity) { 44010037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 44110037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 44212667Schuan.zhu@arm.com if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 44310037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 44410037SARM gem5 Developers // NB: Skipping the full loop, here 44510037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 44610037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 44710037SARM gem5 Developers } 44810037SARM gem5 Developers } 44910037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 45010037SARM gem5 Developers val &= cpacrMask; 45110037SARM gem5 Developers DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 45210037SARM gem5 Developers miscRegName[misc_reg], val); 45310037SARM gem5 Developers return val; 45410037SARM gem5 Developers } 4558284SAli.Saidi@ARM.com case MISCREG_MPIDR: 45610037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 45710037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 45810037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 45910037SARM gem5 Developers return getMPIDR(system, tc); 4609050Schander.sudanthi@arm.com } else { 46110037SARM gem5 Developers return readMiscReg(MISCREG_VMPIDR, tc); 46210037SARM gem5 Developers } 46310037SARM gem5 Developers break; 46410037SARM gem5 Developers case MISCREG_MPIDR_EL1: 46510037SARM gem5 Developers // @todo in the absence of v8 virtualization support just return MPIDR_EL1 46610037SARM gem5 Developers return getMPIDR(system, tc) & 0xffffffff; 46710037SARM gem5 Developers case MISCREG_VMPIDR: 46810037SARM gem5 Developers // top bit defined as RES1 46910037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 47010037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 47110037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 47210037SARM gem5 Developers case MISCREG_MIDR: 47310037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 47410037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 47510037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 47610037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 47710037SARM gem5 Developers } else { 47810037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_VPIDR); 4799050Schander.sudanthi@arm.com } 4808284SAli.Saidi@ARM.com break; 48110037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 48210037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 48310037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 48410037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 48510037SARM gem5 Developers case MISCREG_TCMTR: // No TCM's 48610037SARM gem5 Developers return 0; 48710037SARM gem5 Developers 4887405SAli.Saidi@ARM.com case MISCREG_CLIDR: 4897731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 4908468Swade.walker@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 4918468Swade.walker@arm.com "ARM implementations.\n"); 4928468Swade.walker@arm.com return 0x00200000; 4937405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 4947731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 4957405SAli.Saidi@ARM.com "always reads as 0.\n"); 4967405SAli.Saidi@ARM.com break; 49711809Sbaz21@cam.ac.uk case MISCREG_CTR: // AArch32, ARMv7, top bit set 49811809Sbaz21@cam.ac.uk case MISCREG_CTR_EL0: // AArch64 4999130Satgutier@umich.edu { 5009130Satgutier@umich.edu //all caches have the same line size in gem5 5019130Satgutier@umich.edu //4 byte words in ARM 5029130Satgutier@umich.edu unsigned lineSizeWords = 5039814Sandreas.hansson@arm.com tc->getSystemPtr()->cacheLineSize() / 4; 5049130Satgutier@umich.edu unsigned log2LineSizeWords = 0; 5059130Satgutier@umich.edu 5069130Satgutier@umich.edu while (lineSizeWords >>= 1) { 5079130Satgutier@umich.edu ++log2LineSizeWords; 5089130Satgutier@umich.edu } 5099130Satgutier@umich.edu 5109130Satgutier@umich.edu CTR ctr = 0; 5119130Satgutier@umich.edu //log2 of minimun i-cache line size (words) 5129130Satgutier@umich.edu ctr.iCacheLineSize = log2LineSizeWords; 5139130Satgutier@umich.edu //b11 - gem5 uses pipt 5149130Satgutier@umich.edu ctr.l1IndexPolicy = 0x3; 5159130Satgutier@umich.edu //log2 of minimum d-cache line size (words) 5169130Satgutier@umich.edu ctr.dCacheLineSize = log2LineSizeWords; 5179130Satgutier@umich.edu //log2 of max reservation size (words) 5189130Satgutier@umich.edu ctr.erg = log2LineSizeWords; 5199130Satgutier@umich.edu //log2 of max writeback size (words) 5209130Satgutier@umich.edu ctr.cwg = log2LineSizeWords; 5219130Satgutier@umich.edu //b100 - gem5 format is ARMv7 5229130Satgutier@umich.edu ctr.format = 0x4; 5239130Satgutier@umich.edu 5249130Satgutier@umich.edu return ctr; 5259130Satgutier@umich.edu } 5267583SAli.Saidi@arm.com case MISCREG_ACTLR: 5277583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 5287583SAli.Saidi@arm.com break; 52910461SAndreas.Sandberg@ARM.com 53010461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 53110461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 53210461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 53310461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 53410461SAndreas.Sandberg@ARM.com return pmu->readMiscReg(misc_reg); 53510461SAndreas.Sandberg@ARM.com 5368302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 5378302SAli.Saidi@ARM.com panic("shouldn't be reading this register seperately\n"); 5387783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 5397783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 5407783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 5417783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 54210037SARM gem5 Developers case MISCREG_FPSR: 54310037SARM gem5 Developers { 54410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 54510037SARM gem5 Developers FPSCR fpscrMask = 0; 54610037SARM gem5 Developers fpscrMask.ioc = ones; 54710037SARM gem5 Developers fpscrMask.dzc = ones; 54810037SARM gem5 Developers fpscrMask.ofc = ones; 54910037SARM gem5 Developers fpscrMask.ufc = ones; 55010037SARM gem5 Developers fpscrMask.ixc = ones; 55110037SARM gem5 Developers fpscrMask.idc = ones; 55210037SARM gem5 Developers fpscrMask.qc = ones; 55310037SARM gem5 Developers fpscrMask.v = ones; 55410037SARM gem5 Developers fpscrMask.c = ones; 55510037SARM gem5 Developers fpscrMask.z = ones; 55610037SARM gem5 Developers fpscrMask.n = ones; 55710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 55810037SARM gem5 Developers } 55910037SARM gem5 Developers case MISCREG_FPCR: 56010037SARM gem5 Developers { 56110037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 56210037SARM gem5 Developers FPSCR fpscrMask = 0; 56310037SARM gem5 Developers fpscrMask.len = ones; 56410037SARM gem5 Developers fpscrMask.stride = ones; 56510037SARM gem5 Developers fpscrMask.rMode = ones; 56610037SARM gem5 Developers fpscrMask.fz = ones; 56710037SARM gem5 Developers fpscrMask.dn = ones; 56810037SARM gem5 Developers fpscrMask.ahp = ones; 56910037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 57010037SARM gem5 Developers } 57110037SARM gem5 Developers case MISCREG_NZCV: 57210037SARM gem5 Developers { 57310037SARM gem5 Developers CPSR cpsr = 0; 57410338SCurtis.Dunham@arm.com cpsr.nz = tc->readCCReg(CCREG_NZ); 57510338SCurtis.Dunham@arm.com cpsr.c = tc->readCCReg(CCREG_C); 57610338SCurtis.Dunham@arm.com cpsr.v = tc->readCCReg(CCREG_V); 57710037SARM gem5 Developers return cpsr; 57810037SARM gem5 Developers } 57910037SARM gem5 Developers case MISCREG_DAIF: 58010037SARM gem5 Developers { 58110037SARM gem5 Developers CPSR cpsr = 0; 58210037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 58310037SARM gem5 Developers return cpsr; 58410037SARM gem5 Developers } 58510037SARM gem5 Developers case MISCREG_SP_EL0: 58610037SARM gem5 Developers { 58710037SARM gem5 Developers return tc->readIntReg(INTREG_SP0); 58810037SARM gem5 Developers } 58910037SARM gem5 Developers case MISCREG_SP_EL1: 59010037SARM gem5 Developers { 59110037SARM gem5 Developers return tc->readIntReg(INTREG_SP1); 59210037SARM gem5 Developers } 59310037SARM gem5 Developers case MISCREG_SP_EL2: 59410037SARM gem5 Developers { 59510037SARM gem5 Developers return tc->readIntReg(INTREG_SP2); 59610037SARM gem5 Developers } 59710037SARM gem5 Developers case MISCREG_SPSEL: 59810037SARM gem5 Developers { 59910037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0x1; 60010037SARM gem5 Developers } 60110037SARM gem5 Developers case MISCREG_CURRENTEL: 60210037SARM gem5 Developers { 60310037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0xc; 60410037SARM gem5 Developers } 6058549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 6068868SMatt.Horsnell@arm.com { 6078868SMatt.Horsnell@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 6088868SMatt.Horsnell@arm.com L2CTLR l2ctlr = 0; 6098868SMatt.Horsnell@arm.com // b00:1CPU to b11:4CPUs 6108868SMatt.Horsnell@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 6118868SMatt.Horsnell@arm.com return l2ctlr; 6128868SMatt.Horsnell@arm.com } 6138868SMatt.Horsnell@arm.com case MISCREG_DBGDIDR: 6148868SMatt.Horsnell@arm.com /* For now just implement the version number. 61510461SAndreas.Sandberg@ARM.com * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 6168868SMatt.Horsnell@arm.com */ 61710461SAndreas.Sandberg@ARM.com return 0x5 << 16; 61810037SARM gem5 Developers case MISCREG_DBGDSCRint: 6198868SMatt.Horsnell@arm.com return 0; 62010037SARM gem5 Developers case MISCREG_ISR: 62111150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 62210037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR), 62310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 62410037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR)); 62510037SARM gem5 Developers case MISCREG_ISR_EL1: 62611150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 62710037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR_EL2), 62810037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 62910037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR_EL3)); 63010037SARM gem5 Developers case MISCREG_DCZID_EL0: 63110037SARM gem5 Developers return 0x04; // DC ZVA clear 64-byte chunks 63210037SARM gem5 Developers case MISCREG_HCPTR: 63310037SARM gem5 Developers { 63410037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(misc_reg); 63510037SARM gem5 Developers // The trap bit associated with CP14 is defined as RAZ 63610037SARM gem5 Developers val &= ~(1 << 14); 63710037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 63810037SARM gem5 Developers // HCPTR is RAO/WI 63910037SARM gem5 Developers bool secure_lookup = haveSecurity && 64010037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 64110037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 64210037SARM gem5 Developers if (!secure_lookup) { 64310037SARM gem5 Developers MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 64410037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 64510037SARM gem5 Developers } 64610037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 64710037SARM gem5 Developers val |= 0x33FF; 64810037SARM gem5 Developers return (val); 64910037SARM gem5 Developers } 65010037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 65110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 65210037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 65310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 65410037SARM gem5 Developers case MISCREG_HVBAR: // bottom bits reserved 65510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 65611769SCurtis.Dunham@arm.com case MISCREG_SCTLR: 65711769SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 65810037SARM gem5 Developers case MISCREG_SCTLR_EL1: 65911770SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 66011770SCurtis.Dunham@arm.com case MISCREG_SCTLR_EL2: 66110037SARM gem5 Developers case MISCREG_SCTLR_EL3: 66211770SCurtis.Dunham@arm.com case MISCREG_HSCTLR: 66311769SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 66410844Sandreas.sandberg@arm.com 66511772SCurtis.Dunham@arm.com case MISCREG_ID_PFR0: 66611772SCurtis.Dunham@arm.com // !ThumbEE | !Jazelle | Thumb | ARM 66711772SCurtis.Dunham@arm.com return 0x00000031; 66811772SCurtis.Dunham@arm.com case MISCREG_ID_PFR1: 66911774SCurtis.Dunham@arm.com { // Timer | Virti | !M Profile | TrustZone | ARMv4 67011774SCurtis.Dunham@arm.com bool haveTimer = (system->getGenericTimer() != NULL); 67111774SCurtis.Dunham@arm.com return 0x00000001 67211774SCurtis.Dunham@arm.com | (haveSecurity ? 0x00000010 : 0x0) 67311774SCurtis.Dunham@arm.com | (haveVirtualization ? 0x00001000 : 0x0) 67411774SCurtis.Dunham@arm.com | (haveTimer ? 0x00010000 : 0x0); 67511774SCurtis.Dunham@arm.com } 67611773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR0_EL1: 67711773SCurtis.Dunham@arm.com return 0x0000000000000002 // AArch{64,32} supported at EL0 67811773SCurtis.Dunham@arm.com | 0x0000000000000020 // EL1 67911773SCurtis.Dunham@arm.com | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 68011773SCurtis.Dunham@arm.com | (haveSecurity ? 0x0000000000002000 : 0); // EL3 68111773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR1_EL1: 68211773SCurtis.Dunham@arm.com return 0; // bits [63:0] RES0 (reserved for future use) 68311772SCurtis.Dunham@arm.com 68410037SARM gem5 Developers // Generic Timer registers 68512816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CTL_EL2: 68612816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CVAL_EL2: 68712816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_TVAL_EL2: 68810844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 68910844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 69010844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 69110844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 69210844Sandreas.sandberg@arm.com return getGenericTimer(tc).readMiscReg(misc_reg); 69310844Sandreas.sandberg@arm.com 69410188Sgeoffrey.blake@arm.com default: 69510037SARM gem5 Developers break; 69610037SARM gem5 Developers 6977405SAli.Saidi@ARM.com } 6987405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 6997405SAli.Saidi@ARM.com} 7007405SAli.Saidi@ARM.com 7017405SAli.Saidi@ARM.comvoid 7027405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 7037405SAli.Saidi@ARM.com{ 7047405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 7057614Sminkyu.jeong@arm.com 70612478SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 70712478SCurtis.Dunham@arm.com const auto &map = getMiscIndices(misc_reg); 70812478SCurtis.Dunham@arm.com int lower = map.first, upper = map.second; 70912478SCurtis.Dunham@arm.com 71012478SCurtis.Dunham@arm.com auto v = (val & ~reg.wi()) | reg.rao(); 71111771SCurtis.Dunham@arm.com if (upper > 0) { 71212478SCurtis.Dunham@arm.com miscRegs[lower] = bits(v, 31, 0); 71312478SCurtis.Dunham@arm.com miscRegs[upper] = bits(v, 63, 32); 71410037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 71512478SCurtis.Dunham@arm.com misc_reg, lower, upper, v); 71610037SARM gem5 Developers } else { 71712478SCurtis.Dunham@arm.com miscRegs[lower] = v; 71810037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 71912478SCurtis.Dunham@arm.com misc_reg, lower, v); 72010037SARM gem5 Developers } 7217405SAli.Saidi@ARM.com} 7227405SAli.Saidi@ARM.com 7237405SAli.Saidi@ARM.comvoid 7247405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 7257405SAli.Saidi@ARM.com{ 7267749SAli.Saidi@ARM.com 7277405SAli.Saidi@ARM.com MiscReg newVal = val; 72810037SARM gem5 Developers bool secure_lookup; 72910037SARM gem5 Developers SCR scr; 7308284SAli.Saidi@ARM.com 7317405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 7327405SAli.Saidi@ARM.com updateRegMap(val); 7337749SAli.Saidi@ARM.com 7347749SAli.Saidi@ARM.com 7357749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 7367749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 7377405SAli.Saidi@ARM.com CPSR cpsr = val; 73812510Sgiacomo.travaglini@arm.com if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 73912406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 74012406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 7417749SAli.Saidi@ARM.com } 7427749SAli.Saidi@ARM.com 7437614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 7447614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 7457720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 7467720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 7477720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 74812763Sgiacomo.travaglini@arm.com pc.illegalExec(cpsr.il == 1); 7498887Sgeoffrey.blake@arm.com 7508887Sgeoffrey.blake@arm.com // Follow slightly different semantics if a CheckerCPU object 7518887Sgeoffrey.blake@arm.com // is connected 7528887Sgeoffrey.blake@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 7538887Sgeoffrey.blake@arm.com if (checker) { 7548887Sgeoffrey.blake@arm.com tc->pcStateNoRecord(pc); 7558887Sgeoffrey.blake@arm.com } else { 7568887Sgeoffrey.blake@arm.com tc->pcState(pc); 7578887Sgeoffrey.blake@arm.com } 7587408Sgblack@eecs.umich.edu } else { 75910037SARM gem5 Developers#ifndef NDEBUG 76010037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 76110037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 76210037SARM gem5 Developers warn("Unimplemented system register %s write with %#x.\n", 76310037SARM gem5 Developers miscRegName[misc_reg], val); 76410037SARM gem5 Developers else 76510037SARM gem5 Developers panic("Unimplemented system register %s write with %#x.\n", 76610037SARM gem5 Developers miscRegName[misc_reg], val); 76710037SARM gem5 Developers } 76810037SARM gem5 Developers#endif 76910037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 7707408Sgblack@eecs.umich.edu case MISCREG_CPACR: 7717408Sgblack@eecs.umich.edu { 7728206SWilliam.Wang@arm.com 7738206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 7748206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 7758206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 7768206SWilliam.Wang@arm.com // be writable 7778206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 7788206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 7798206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 78010037SARM gem5 Developers 78110037SARM gem5 Developers // Security Extensions may limit the writability of CPACR 78210037SARM gem5 Developers if (haveSecurity) { 78310037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 78410037SARM gem5 Developers CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 78512667Schuan.zhu@arm.com if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 78610037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 78710037SARM gem5 Developers // NB: Skipping the full loop, here 78810037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 78910037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 79010037SARM gem5 Developers } 79110037SARM gem5 Developers } 79210037SARM gem5 Developers 79310037SARM gem5 Developers MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 7948206SWilliam.Wang@arm.com newVal &= cpacrMask; 79510037SARM gem5 Developers newVal |= old_val & ~cpacrMask; 79610037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 79710037SARM gem5 Developers miscRegName[misc_reg], newVal); 79810037SARM gem5 Developers } 79910037SARM gem5 Developers break; 80010037SARM gem5 Developers case MISCREG_CPTR_EL2: 80110037SARM gem5 Developers { 80210037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 80310037SARM gem5 Developers CPTR cptrMask = 0; 80410037SARM gem5 Developers cptrMask.tcpac = ones; 80510037SARM gem5 Developers cptrMask.tta = ones; 80610037SARM gem5 Developers cptrMask.tfp = ones; 80710037SARM gem5 Developers newVal &= cptrMask; 80810037SARM gem5 Developers cptrMask = 0; 80910037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 81010037SARM gem5 Developers cptrMask.res1_9_0_el2 = ones; 81110037SARM gem5 Developers newVal |= cptrMask; 81210037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 81310037SARM gem5 Developers miscRegName[misc_reg], newVal); 81410037SARM gem5 Developers } 81510037SARM gem5 Developers break; 81610037SARM gem5 Developers case MISCREG_CPTR_EL3: 81710037SARM gem5 Developers { 81810037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 81910037SARM gem5 Developers CPTR cptrMask = 0; 82010037SARM gem5 Developers cptrMask.tcpac = ones; 82110037SARM gem5 Developers cptrMask.tta = ones; 82210037SARM gem5 Developers cptrMask.tfp = ones; 82310037SARM gem5 Developers newVal &= cptrMask; 8248206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 8258206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 8267408Sgblack@eecs.umich.edu } 8277408Sgblack@eecs.umich.edu break; 8287408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 8297731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 8308206SWilliam.Wang@arm.com return; 83110037SARM gem5 Developers 83210037SARM gem5 Developers case MISCREG_DC_ZVA_Xt: 83310037SARM gem5 Developers warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 83410037SARM gem5 Developers return; 83510037SARM gem5 Developers 8367408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 8377408Sgblack@eecs.umich.edu { 8387408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 8397408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 8407408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 8417408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 8427408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 8437408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 8447408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 8457408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 84610037SARM gem5 Developers fpscrMask.ioe = ones; 84710037SARM gem5 Developers fpscrMask.dze = ones; 84810037SARM gem5 Developers fpscrMask.ofe = ones; 84910037SARM gem5 Developers fpscrMask.ufe = ones; 85010037SARM gem5 Developers fpscrMask.ixe = ones; 85110037SARM gem5 Developers fpscrMask.ide = ones; 8527408Sgblack@eecs.umich.edu fpscrMask.len = ones; 8537408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 8547408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 8557408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 8567408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 8577408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 8587408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 8597408Sgblack@eecs.umich.edu fpscrMask.v = ones; 8607408Sgblack@eecs.umich.edu fpscrMask.c = ones; 8617408Sgblack@eecs.umich.edu fpscrMask.z = ones; 8627408Sgblack@eecs.umich.edu fpscrMask.n = ones; 8637408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 86410037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 86510037SARM gem5 Developers ~(uint32_t)fpscrMask); 8669377Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(newVal); 8677408Sgblack@eecs.umich.edu } 8687408Sgblack@eecs.umich.edu break; 86910037SARM gem5 Developers case MISCREG_FPSR: 87010037SARM gem5 Developers { 87110037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 87210037SARM gem5 Developers FPSCR fpscrMask = 0; 87310037SARM gem5 Developers fpscrMask.ioc = ones; 87410037SARM gem5 Developers fpscrMask.dzc = ones; 87510037SARM gem5 Developers fpscrMask.ofc = ones; 87610037SARM gem5 Developers fpscrMask.ufc = ones; 87710037SARM gem5 Developers fpscrMask.ixc = ones; 87810037SARM gem5 Developers fpscrMask.idc = ones; 87910037SARM gem5 Developers fpscrMask.qc = ones; 88010037SARM gem5 Developers fpscrMask.v = ones; 88110037SARM gem5 Developers fpscrMask.c = ones; 88210037SARM gem5 Developers fpscrMask.z = ones; 88310037SARM gem5 Developers fpscrMask.n = ones; 88410037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 88510037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 88610037SARM gem5 Developers ~(uint32_t)fpscrMask); 88710037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 88810037SARM gem5 Developers } 88910037SARM gem5 Developers break; 89010037SARM gem5 Developers case MISCREG_FPCR: 89110037SARM gem5 Developers { 89210037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 89310037SARM gem5 Developers FPSCR fpscrMask = 0; 89410037SARM gem5 Developers fpscrMask.len = ones; 89510037SARM gem5 Developers fpscrMask.stride = ones; 89610037SARM gem5 Developers fpscrMask.rMode = ones; 89710037SARM gem5 Developers fpscrMask.fz = ones; 89810037SARM gem5 Developers fpscrMask.dn = ones; 89910037SARM gem5 Developers fpscrMask.ahp = ones; 90010037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 90110037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 90210037SARM gem5 Developers ~(uint32_t)fpscrMask); 90310037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 90410037SARM gem5 Developers } 90510037SARM gem5 Developers break; 9068302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 9078302SAli.Saidi@ARM.com { 9088302SAli.Saidi@ARM.com assert(!(newVal & ~CpsrMaskQ)); 90910037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 9108302SAli.Saidi@ARM.com misc_reg = MISCREG_CPSR; 9118302SAli.Saidi@ARM.com } 9128302SAli.Saidi@ARM.com break; 9137783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 9147783SGiacomo.Gabrielli@arm.com { 91510037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 91610037SARM gem5 Developers (newVal & FpscrQcMask); 9177783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 9187783SGiacomo.Gabrielli@arm.com } 9197783SGiacomo.Gabrielli@arm.com break; 9207783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 9217783SGiacomo.Gabrielli@arm.com { 92210037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 92310037SARM gem5 Developers (newVal & FpscrExcMask); 9247783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 9257783SGiacomo.Gabrielli@arm.com } 9267783SGiacomo.Gabrielli@arm.com break; 9277408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 9287408Sgblack@eecs.umich.edu { 9298206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 9308206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 9317408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 9327408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 93310037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 9347408Sgblack@eecs.umich.edu } 9357408Sgblack@eecs.umich.edu break; 93610037SARM gem5 Developers case MISCREG_HCR: 93710037SARM gem5 Developers { 93810037SARM gem5 Developers if (!haveVirtualization) 93910037SARM gem5 Developers return; 94010037SARM gem5 Developers } 94110037SARM gem5 Developers break; 94210037SARM gem5 Developers case MISCREG_IFSR: 94310037SARM gem5 Developers { 94410037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.96 94510037SARM gem5 Developers const uint32_t ifsrMask = 94610037SARM gem5 Developers mask(31, 13) | mask(11, 11) | mask(8, 6); 94710037SARM gem5 Developers newVal = newVal & ~ifsrMask; 94810037SARM gem5 Developers } 94910037SARM gem5 Developers break; 95010037SARM gem5 Developers case MISCREG_DFSR: 95110037SARM gem5 Developers { 95210037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.52 95310037SARM gem5 Developers const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 95410037SARM gem5 Developers newVal = newVal & ~dfsrMask; 95510037SARM gem5 Developers } 95610037SARM gem5 Developers break; 95710037SARM gem5 Developers case MISCREG_AMAIR0: 95810037SARM gem5 Developers case MISCREG_AMAIR1: 95910037SARM gem5 Developers { 96010037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 96110037SARM gem5 Developers // Valid only with LPAE 96210037SARM gem5 Developers if (!haveLPAE) 96310037SARM gem5 Developers return; 96410037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 96510037SARM gem5 Developers } 96610037SARM gem5 Developers break; 96710037SARM gem5 Developers case MISCREG_SCR: 96812406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 96912406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 97010037SARM gem5 Developers break; 9717408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 9727408Sgblack@eecs.umich.edu { 9737408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 97410037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 97512639Sgiacomo.travaglini@arm.com 97612639Sgiacomo.travaglini@arm.com MiscRegIndex sctlr_idx; 97712639Sgiacomo.travaglini@arm.com if (haveSecurity && !highestELIs64 && !scr.ns) { 97812639Sgiacomo.travaglini@arm.com sctlr_idx = MISCREG_SCTLR_S; 97912639Sgiacomo.travaglini@arm.com } else { 98012639Sgiacomo.travaglini@arm.com sctlr_idx = MISCREG_SCTLR_NS; 98112639Sgiacomo.travaglini@arm.com } 98212639Sgiacomo.travaglini@arm.com 98310037SARM gem5 Developers SCTLR sctlr = miscRegs[sctlr_idx]; 9847408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 98510037SARM gem5 Developers new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 98610037SARM gem5 Developers miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 98712406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 98812406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 9897408Sgblack@eecs.umich.edu } 9909385SAndreas.Sandberg@arm.com case MISCREG_MIDR: 9919385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR0: 9929385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR1: 99310461SAndreas.Sandberg@ARM.com case MISCREG_ID_DFR0: 9949385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR0: 9959385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR1: 9969385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR2: 9979385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR3: 9989385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR0: 9999385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR1: 10009385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR2: 10019385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR3: 10029385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR4: 10039385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR5: 10049385SAndreas.Sandberg@arm.com 10059385SAndreas.Sandberg@arm.com case MISCREG_MPIDR: 10069385SAndreas.Sandberg@arm.com case MISCREG_FPSID: 10077408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 10087408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 10097408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 101010037SARM gem5 Developers 101110037SARM gem5 Developers case MISCREG_ID_AA64AFR0_EL1: 101210037SARM gem5 Developers case MISCREG_ID_AA64AFR1_EL1: 101310037SARM gem5 Developers case MISCREG_ID_AA64DFR0_EL1: 101410037SARM gem5 Developers case MISCREG_ID_AA64DFR1_EL1: 101510037SARM gem5 Developers case MISCREG_ID_AA64ISAR0_EL1: 101610037SARM gem5 Developers case MISCREG_ID_AA64ISAR1_EL1: 101710037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 101810037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 101913116Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64MMFR2_EL1: 102010037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 102110037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 10229385SAndreas.Sandberg@arm.com // ID registers are constants. 10237408Sgblack@eecs.umich.edu return; 10249385SAndreas.Sandberg@arm.com 102512605Sgiacomo.travaglini@arm.com // TLB Invalidate All 102612605Sgiacomo.travaglini@arm.com case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 102712605Sgiacomo.travaglini@arm.com { 102812605Sgiacomo.travaglini@arm.com assert32(tc); 102912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 103012605Sgiacomo.travaglini@arm.com 103112605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 103212605Sgiacomo.travaglini@arm.com tlbiOp(tc); 103312605Sgiacomo.travaglini@arm.com return; 103412605Sgiacomo.travaglini@arm.com } 103512605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Inner Shareable 10367408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 103712605Sgiacomo.travaglini@arm.com { 103812605Sgiacomo.travaglini@arm.com assert32(tc); 103912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 104012605Sgiacomo.travaglini@arm.com 104112605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 104212605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 104312605Sgiacomo.travaglini@arm.com return; 104412605Sgiacomo.travaglini@arm.com } 104512605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate All 10467408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 104712605Sgiacomo.travaglini@arm.com { 104812605Sgiacomo.travaglini@arm.com assert32(tc); 104912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 105012605Sgiacomo.travaglini@arm.com 105112605Sgiacomo.travaglini@arm.com ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 105212605Sgiacomo.travaglini@arm.com tlbiOp(tc); 105312605Sgiacomo.travaglini@arm.com return; 105412605Sgiacomo.travaglini@arm.com } 105512605Sgiacomo.travaglini@arm.com // Data TLB Invalidate All 10567408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 105712605Sgiacomo.travaglini@arm.com { 105812605Sgiacomo.travaglini@arm.com assert32(tc); 105912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 106012605Sgiacomo.travaglini@arm.com 106112605Sgiacomo.travaglini@arm.com DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 106212605Sgiacomo.travaglini@arm.com tlbiOp(tc); 106312605Sgiacomo.travaglini@arm.com return; 106412605Sgiacomo.travaglini@arm.com } 106512605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA 106612605Sgiacomo.travaglini@arm.com // mcr tlbimval(is) is invalidating all matching entries 106712605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 106812605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 106912605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVA: 107012576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAL: 107112605Sgiacomo.travaglini@arm.com { 107212605Sgiacomo.travaglini@arm.com assert32(tc); 107312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 107412605Sgiacomo.travaglini@arm.com 107512605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, 107612605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 107712605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 107812605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 107912605Sgiacomo.travaglini@arm.com 108012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 108112605Sgiacomo.travaglini@arm.com return; 108212605Sgiacomo.travaglini@arm.com } 108312605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Inner Shareable 108412605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAIS: 108512576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALIS: 108612605Sgiacomo.travaglini@arm.com { 108712605Sgiacomo.travaglini@arm.com assert32(tc); 108812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 108912605Sgiacomo.travaglini@arm.com 109012605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, 109112605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 109212605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 109312605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 109412605Sgiacomo.travaglini@arm.com 109512605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 109612605Sgiacomo.travaglini@arm.com return; 109712605Sgiacomo.travaglini@arm.com } 109812605Sgiacomo.travaglini@arm.com // TLB Invalidate by ASID match 109912605Sgiacomo.travaglini@arm.com case MISCREG_TLBIASID: 110012605Sgiacomo.travaglini@arm.com { 110112605Sgiacomo.travaglini@arm.com assert32(tc); 110212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 110312605Sgiacomo.travaglini@arm.com 110412605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, 110512605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 110612605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 110712605Sgiacomo.travaglini@arm.com 110812605Sgiacomo.travaglini@arm.com tlbiOp(tc); 110912605Sgiacomo.travaglini@arm.com return; 111012605Sgiacomo.travaglini@arm.com } 111112605Sgiacomo.travaglini@arm.com // TLB Invalidate by ASID match, Inner Shareable 11127408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 111312605Sgiacomo.travaglini@arm.com { 111412605Sgiacomo.travaglini@arm.com assert32(tc); 111512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 111612605Sgiacomo.travaglini@arm.com 111712605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, 111812605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 111912605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 112012605Sgiacomo.travaglini@arm.com 112112605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 112212605Sgiacomo.travaglini@arm.com return; 112312605Sgiacomo.travaglini@arm.com } 112412605Sgiacomo.travaglini@arm.com // mcr tlbimvaal(is) is invalidating all matching entries 112512605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 112612605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 112712605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, All ASID 112812605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAA: 112912576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAAL: 113012605Sgiacomo.travaglini@arm.com { 113112605Sgiacomo.travaglini@arm.com assert32(tc); 113212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 113312605Sgiacomo.travaglini@arm.com 113412605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 113512605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), false); 113612605Sgiacomo.travaglini@arm.com 113712605Sgiacomo.travaglini@arm.com tlbiOp(tc); 113812605Sgiacomo.travaglini@arm.com return; 113912605Sgiacomo.travaglini@arm.com } 114012605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, All ASID, Inner Shareable 114112605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAAIS: 114212576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAALIS: 114312605Sgiacomo.travaglini@arm.com { 114412605Sgiacomo.travaglini@arm.com assert32(tc); 114512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 114612605Sgiacomo.travaglini@arm.com 114712605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 114812605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), false); 114912605Sgiacomo.travaglini@arm.com 115012605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 115112605Sgiacomo.travaglini@arm.com return; 115212605Sgiacomo.travaglini@arm.com } 115312605Sgiacomo.travaglini@arm.com // mcr tlbimvalh(is) is invalidating all matching entries 115412605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 115512605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 115612605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Hyp mode 115712605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAH: 115812576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALH: 115912605Sgiacomo.travaglini@arm.com { 116012605Sgiacomo.travaglini@arm.com assert32(tc); 116112605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 116212605Sgiacomo.travaglini@arm.com 116312605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 116412605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), true); 116512605Sgiacomo.travaglini@arm.com 116612605Sgiacomo.travaglini@arm.com tlbiOp(tc); 116712605Sgiacomo.travaglini@arm.com return; 116812605Sgiacomo.travaglini@arm.com } 116912605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Hyp mode, Inner Shareable 117012605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAHIS: 117112576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALHIS: 117212605Sgiacomo.travaglini@arm.com { 117312605Sgiacomo.travaglini@arm.com assert32(tc); 117412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 117512605Sgiacomo.travaglini@arm.com 117612605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 117712605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), true); 117812605Sgiacomo.travaglini@arm.com 117912605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 118012605Sgiacomo.travaglini@arm.com return; 118112605Sgiacomo.travaglini@arm.com } 118212605Sgiacomo.travaglini@arm.com // mcr tlbiipas2l(is) is invalidating all matching entries 118312605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 118412605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 118512605Sgiacomo.travaglini@arm.com // TLB Invalidate by Intermediate Physical Address, Stage 2 118612605Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2: 118712577Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2L: 118812605Sgiacomo.travaglini@arm.com { 118912605Sgiacomo.travaglini@arm.com assert32(tc); 119012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 119112605Sgiacomo.travaglini@arm.com 119212605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, 119312605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 119412605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 119512605Sgiacomo.travaglini@arm.com 119612605Sgiacomo.travaglini@arm.com tlbiOp(tc); 119712605Sgiacomo.travaglini@arm.com return; 119812605Sgiacomo.travaglini@arm.com } 119912605Sgiacomo.travaglini@arm.com // TLB Invalidate by Intermediate Physical Address, Stage 2, 120012605Sgiacomo.travaglini@arm.com // Inner Shareable 120112605Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2IS: 120212577Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2LIS: 120312605Sgiacomo.travaglini@arm.com { 120412605Sgiacomo.travaglini@arm.com assert32(tc); 120512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 120612605Sgiacomo.travaglini@arm.com 120712605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, 120812605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 120912605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 121012605Sgiacomo.travaglini@arm.com 121112605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 121212605Sgiacomo.travaglini@arm.com return; 121312605Sgiacomo.travaglini@arm.com } 121412605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate by VA 121510037SARM gem5 Developers case MISCREG_ITLBIMVA: 121612605Sgiacomo.travaglini@arm.com { 121712605Sgiacomo.travaglini@arm.com assert32(tc); 121812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 121912605Sgiacomo.travaglini@arm.com 122012605Sgiacomo.travaglini@arm.com ITLBIMVA tlbiOp(EL1, 122112605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 122212605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 122312605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 122412605Sgiacomo.travaglini@arm.com 122512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 122612605Sgiacomo.travaglini@arm.com return; 122712605Sgiacomo.travaglini@arm.com } 122812605Sgiacomo.travaglini@arm.com // Data TLB Invalidate by VA 122910037SARM gem5 Developers case MISCREG_DTLBIMVA: 123012605Sgiacomo.travaglini@arm.com { 123112605Sgiacomo.travaglini@arm.com assert32(tc); 123212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 123312605Sgiacomo.travaglini@arm.com 123412605Sgiacomo.travaglini@arm.com DTLBIMVA tlbiOp(EL1, 123512605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 123612605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 123712605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 123812605Sgiacomo.travaglini@arm.com 123912605Sgiacomo.travaglini@arm.com tlbiOp(tc); 124012605Sgiacomo.travaglini@arm.com return; 124112605Sgiacomo.travaglini@arm.com } 124212605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate by ASID match 124310037SARM gem5 Developers case MISCREG_ITLBIASID: 124412605Sgiacomo.travaglini@arm.com { 124512605Sgiacomo.travaglini@arm.com assert32(tc); 124612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 124712605Sgiacomo.travaglini@arm.com 124812605Sgiacomo.travaglini@arm.com ITLBIASID tlbiOp(EL1, 124912605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 125012605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 125112605Sgiacomo.travaglini@arm.com 125212605Sgiacomo.travaglini@arm.com tlbiOp(tc); 125312605Sgiacomo.travaglini@arm.com return; 125412605Sgiacomo.travaglini@arm.com } 125512605Sgiacomo.travaglini@arm.com // Data TLB Invalidate by ASID match 125610037SARM gem5 Developers case MISCREG_DTLBIASID: 125712605Sgiacomo.travaglini@arm.com { 125812605Sgiacomo.travaglini@arm.com assert32(tc); 125912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 126012605Sgiacomo.travaglini@arm.com 126112605Sgiacomo.travaglini@arm.com DTLBIASID tlbiOp(EL1, 126212605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 126312605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 126412605Sgiacomo.travaglini@arm.com 126512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 126612605Sgiacomo.travaglini@arm.com return; 126712605Sgiacomo.travaglini@arm.com } 126812605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Non-Secure Non-Hyp 126910037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 127012605Sgiacomo.travaglini@arm.com { 127112605Sgiacomo.travaglini@arm.com assert32(tc); 127212605Sgiacomo.travaglini@arm.com 127312605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, false); 127412605Sgiacomo.travaglini@arm.com tlbiOp(tc); 127512605Sgiacomo.travaglini@arm.com return; 127612605Sgiacomo.travaglini@arm.com } 127712605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 127810037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 127912605Sgiacomo.travaglini@arm.com { 128012605Sgiacomo.travaglini@arm.com assert32(tc); 128112605Sgiacomo.travaglini@arm.com 128212605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, false); 128312605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 128412605Sgiacomo.travaglini@arm.com return; 128512605Sgiacomo.travaglini@arm.com } 128612605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Hyp mode 128710037SARM gem5 Developers case MISCREG_TLBIALLH: 128812605Sgiacomo.travaglini@arm.com { 128912605Sgiacomo.travaglini@arm.com assert32(tc); 129012605Sgiacomo.travaglini@arm.com 129112605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, true); 129212605Sgiacomo.travaglini@arm.com tlbiOp(tc); 129312605Sgiacomo.travaglini@arm.com return; 129412605Sgiacomo.travaglini@arm.com } 129512605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Hyp mode, Inner Shareable 129610037SARM gem5 Developers case MISCREG_TLBIALLHIS: 129712605Sgiacomo.travaglini@arm.com { 129812605Sgiacomo.travaglini@arm.com assert32(tc); 129912605Sgiacomo.travaglini@arm.com 130012605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, true); 130112605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 130212605Sgiacomo.travaglini@arm.com return; 130312605Sgiacomo.travaglini@arm.com } 130412605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL3 130512605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ALLE3: 130612605Sgiacomo.travaglini@arm.com { 130712605Sgiacomo.travaglini@arm.com assert64(tc); 130812605Sgiacomo.travaglini@arm.com 130912605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL3, true); 131012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 131112605Sgiacomo.travaglini@arm.com return; 131212605Sgiacomo.travaglini@arm.com } 131312605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL3, Inner Shareable 131410037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 131512605Sgiacomo.travaglini@arm.com { 131612605Sgiacomo.travaglini@arm.com assert64(tc); 131712605Sgiacomo.travaglini@arm.com 131812605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL3, true); 131912605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 132012605Sgiacomo.travaglini@arm.com return; 132112605Sgiacomo.travaglini@arm.com } 132210037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 132310037SARM gem5 Developers // case MISCREG_TLBI_ALLE2IS: 132410037SARM gem5 Developers // case MISCREG_TLBI_ALLE2: 132512605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL1 132610037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 132710037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 132810037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 132910037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 133012605Sgiacomo.travaglini@arm.com { 133112605Sgiacomo.travaglini@arm.com assert64(tc); 133212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 133312605Sgiacomo.travaglini@arm.com 133412605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 133512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 133612605Sgiacomo.travaglini@arm.com return; 133712605Sgiacomo.travaglini@arm.com } 133812605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL1, Inner Shareable 133912605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ALLE1IS: 134012605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLE1IS: 134112605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLS12E1IS: 134212605Sgiacomo.travaglini@arm.com // @todo: handle VMID and stage 2 to enable Virtualization 134312605Sgiacomo.travaglini@arm.com { 134412605Sgiacomo.travaglini@arm.com assert64(tc); 134512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 134612605Sgiacomo.travaglini@arm.com 134712605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 134812605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 134912605Sgiacomo.travaglini@arm.com return; 135012605Sgiacomo.travaglini@arm.com } 135112605Sgiacomo.travaglini@arm.com // VAEx(IS) and VALEx(IS) are the same because TLBs 135212605Sgiacomo.travaglini@arm.com // only store entries 135310037SARM gem5 Developers // from the last level of translation table walks 135410037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 135512605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL3 135612605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE3_Xt: 135712605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE3_Xt: 135812605Sgiacomo.travaglini@arm.com { 135912605Sgiacomo.travaglini@arm.com assert64(tc); 136012605Sgiacomo.travaglini@arm.com 136112605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL3, true, 136212605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 136312605Sgiacomo.travaglini@arm.com 0xbeef); 136412605Sgiacomo.travaglini@arm.com tlbiOp(tc); 136512605Sgiacomo.travaglini@arm.com return; 136612605Sgiacomo.travaglini@arm.com } 136712605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 136810037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 136910037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 137012605Sgiacomo.travaglini@arm.com { 137112605Sgiacomo.travaglini@arm.com assert64(tc); 137212605Sgiacomo.travaglini@arm.com 137312605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL3, true, 137412605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 137512605Sgiacomo.travaglini@arm.com 0xbeef); 137612605Sgiacomo.travaglini@arm.com 137712605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 137812605Sgiacomo.travaglini@arm.com return; 137912605Sgiacomo.travaglini@arm.com } 138012605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL2 138112605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE2_Xt: 138212605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE2_Xt: 138312605Sgiacomo.travaglini@arm.com { 138412605Sgiacomo.travaglini@arm.com assert64(tc); 138512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 138612605Sgiacomo.travaglini@arm.com 138712605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 138812605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 138912605Sgiacomo.travaglini@arm.com 0xbeef); 139012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 139112605Sgiacomo.travaglini@arm.com return; 139212605Sgiacomo.travaglini@arm.com } 139312605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 139410037SARM gem5 Developers case MISCREG_TLBI_VAE2IS_Xt: 139510037SARM gem5 Developers case MISCREG_TLBI_VALE2IS_Xt: 139612605Sgiacomo.travaglini@arm.com { 139712605Sgiacomo.travaglini@arm.com assert64(tc); 139812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 139912605Sgiacomo.travaglini@arm.com 140012605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 140112605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 140212605Sgiacomo.travaglini@arm.com 0xbeef); 140312605Sgiacomo.travaglini@arm.com 140412605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 140512605Sgiacomo.travaglini@arm.com return; 140612605Sgiacomo.travaglini@arm.com } 140712605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL1 140812605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE1_Xt: 140912605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE1_Xt: 141012605Sgiacomo.travaglini@arm.com { 141112605Sgiacomo.travaglini@arm.com assert64(tc); 141212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 141312605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 141412605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 141512605Sgiacomo.travaglini@arm.com 141612605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 141712605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 141812605Sgiacomo.travaglini@arm.com asid); 141912605Sgiacomo.travaglini@arm.com 142012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 142112605Sgiacomo.travaglini@arm.com return; 142212605Sgiacomo.travaglini@arm.com } 142312605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 142410037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 142510037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 142612605Sgiacomo.travaglini@arm.com { 142712605Sgiacomo.travaglini@arm.com assert64(tc); 142812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 142912605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 143012605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 143112605Sgiacomo.travaglini@arm.com 143212605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 143312605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 143412605Sgiacomo.travaglini@arm.com asid); 143512605Sgiacomo.travaglini@arm.com 143612605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 143712605Sgiacomo.travaglini@arm.com return; 143812605Sgiacomo.travaglini@arm.com } 143912605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by ASID, EL1 144010037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 144112605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ASIDE1_Xt: 144212605Sgiacomo.travaglini@arm.com { 144312605Sgiacomo.travaglini@arm.com assert64(tc); 144412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 144512605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 144612605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 144712605Sgiacomo.travaglini@arm.com 144812605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 144912605Sgiacomo.travaglini@arm.com tlbiOp(tc); 145012605Sgiacomo.travaglini@arm.com return; 145112605Sgiacomo.travaglini@arm.com } 145212605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 145310037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 145412605Sgiacomo.travaglini@arm.com { 145512605Sgiacomo.travaglini@arm.com assert64(tc); 145612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 145712605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 145812605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 145912605Sgiacomo.travaglini@arm.com 146012605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 146112605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 146212605Sgiacomo.travaglini@arm.com return; 146312605Sgiacomo.travaglini@arm.com } 146410037SARM gem5 Developers // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 146510037SARM gem5 Developers // entries from the last level of translation table walks 146612605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, All ASID, EL1 146712605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAAE1_Xt: 146812605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAALE1_Xt: 146912605Sgiacomo.travaglini@arm.com { 147012605Sgiacomo.travaglini@arm.com assert64(tc); 147112605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 147212605Sgiacomo.travaglini@arm.com 147312605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 147412605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 147512605Sgiacomo.travaglini@arm.com 147612605Sgiacomo.travaglini@arm.com tlbiOp(tc); 147712605Sgiacomo.travaglini@arm.com return; 147812605Sgiacomo.travaglini@arm.com } 147912605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 148010037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 148110037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 148212605Sgiacomo.travaglini@arm.com { 148312605Sgiacomo.travaglini@arm.com assert64(tc); 148412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 148512605Sgiacomo.travaglini@arm.com 148612605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 148712605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 148812605Sgiacomo.travaglini@arm.com 148912605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 149012605Sgiacomo.travaglini@arm.com return; 149112605Sgiacomo.travaglini@arm.com } 149212605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by Intermediate Physical Address, 149312605Sgiacomo.travaglini@arm.com // Stage 2, EL1 149412605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2E1_Xt: 149512605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2LE1_Xt: 149612605Sgiacomo.travaglini@arm.com { 149712605Sgiacomo.travaglini@arm.com assert64(tc); 149812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 149912605Sgiacomo.travaglini@arm.com 150012605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 150112605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 150212605Sgiacomo.travaglini@arm.com 150312605Sgiacomo.travaglini@arm.com tlbiOp(tc); 150412605Sgiacomo.travaglini@arm.com return; 150512605Sgiacomo.travaglini@arm.com } 150612605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by Intermediate Physical Address, 150712605Sgiacomo.travaglini@arm.com // Stage 2, EL1, Inner Shareable 150812605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2E1IS_Xt: 150910037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1IS_Xt: 151012605Sgiacomo.travaglini@arm.com { 151112605Sgiacomo.travaglini@arm.com assert64(tc); 151212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 151312605Sgiacomo.travaglini@arm.com 151412605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 151512605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 151612605Sgiacomo.travaglini@arm.com 151712605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 151812605Sgiacomo.travaglini@arm.com return; 151912605Sgiacomo.travaglini@arm.com } 15207583SAli.Saidi@arm.com case MISCREG_ACTLR: 15217583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 15227583SAli.Saidi@arm.com break; 152310461SAndreas.Sandberg@ARM.com 152410461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 152510461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 152610461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 152710461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 152810461SAndreas.Sandberg@ARM.com pmu->setMiscReg(misc_reg, newVal); 15297583SAli.Saidi@arm.com break; 153010461SAndreas.Sandberg@ARM.com 153110461SAndreas.Sandberg@ARM.com 153210037SARM gem5 Developers case MISCREG_HSTR: // TJDBX, now redifined to be RES0 153310037SARM gem5 Developers { 153410037SARM gem5 Developers HSTR hstrMask = 0; 153510037SARM gem5 Developers hstrMask.tjdbx = 1; 153610037SARM gem5 Developers newVal &= ~((uint32_t) hstrMask); 153710037SARM gem5 Developers break; 153810037SARM gem5 Developers } 153910037SARM gem5 Developers case MISCREG_HCPTR: 154010037SARM gem5 Developers { 154110037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 154210037SARM gem5 Developers // HCPTR is RAO/WI. Same applies to NSASEDIS 154310037SARM gem5 Developers secure_lookup = haveSecurity && 154410037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 154510037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 154610037SARM gem5 Developers if (!secure_lookup) { 154710037SARM gem5 Developers MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 154810037SARM gem5 Developers MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 154910037SARM gem5 Developers newVal = (newVal & ~mask) | (oldValue & mask); 155010037SARM gem5 Developers } 155110037SARM gem5 Developers break; 155210037SARM gem5 Developers } 155310037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 155410037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 155510037SARM gem5 Developers break; 155610037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 155710037SARM gem5 Developers misc_reg = MISCREG_IFAR_S; 155810037SARM gem5 Developers break; 155910037SARM gem5 Developers case MISCREG_ATS1CPR: 156010037SARM gem5 Developers case MISCREG_ATS1CPW: 156110037SARM gem5 Developers case MISCREG_ATS1CUR: 156210037SARM gem5 Developers case MISCREG_ATS1CUW: 156310037SARM gem5 Developers case MISCREG_ATS12NSOPR: 156410037SARM gem5 Developers case MISCREG_ATS12NSOPW: 156510037SARM gem5 Developers case MISCREG_ATS12NSOUR: 156610037SARM gem5 Developers case MISCREG_ATS12NSOUW: 156710037SARM gem5 Developers case MISCREG_ATS1HR: 156810037SARM gem5 Developers case MISCREG_ATS1HW: 15697436Sdam.sunwoo@arm.com { 157011608Snikos.nikoleris@arm.com Request::Flags flags = 0; 157110037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 157210037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 15737436Sdam.sunwoo@arm.com Fault fault; 15747436Sdam.sunwoo@arm.com switch(misc_reg) { 157510037SARM gem5 Developers case MISCREG_ATS1CPR: 157610037SARM gem5 Developers flags = TLB::MustBeOne; 157710037SARM gem5 Developers tranType = TLB::S1CTran; 157810037SARM gem5 Developers mode = BaseTLB::Read; 157910037SARM gem5 Developers break; 158010037SARM gem5 Developers case MISCREG_ATS1CPW: 158110037SARM gem5 Developers flags = TLB::MustBeOne; 158210037SARM gem5 Developers tranType = TLB::S1CTran; 158310037SARM gem5 Developers mode = BaseTLB::Write; 158410037SARM gem5 Developers break; 158510037SARM gem5 Developers case MISCREG_ATS1CUR: 158610037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 158710037SARM gem5 Developers tranType = TLB::S1CTran; 158810037SARM gem5 Developers mode = BaseTLB::Read; 158910037SARM gem5 Developers break; 159010037SARM gem5 Developers case MISCREG_ATS1CUW: 159110037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 159210037SARM gem5 Developers tranType = TLB::S1CTran; 159310037SARM gem5 Developers mode = BaseTLB::Write; 159410037SARM gem5 Developers break; 159510037SARM gem5 Developers case MISCREG_ATS12NSOPR: 159610037SARM gem5 Developers if (!haveSecurity) 159710037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 159810037SARM gem5 Developers flags = TLB::MustBeOne; 159910037SARM gem5 Developers tranType = TLB::S1S2NsTran; 160010037SARM gem5 Developers mode = BaseTLB::Read; 160110037SARM gem5 Developers break; 160210037SARM gem5 Developers case MISCREG_ATS12NSOPW: 160310037SARM gem5 Developers if (!haveSecurity) 160410037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPW"); 160510037SARM gem5 Developers flags = TLB::MustBeOne; 160610037SARM gem5 Developers tranType = TLB::S1S2NsTran; 160710037SARM gem5 Developers mode = BaseTLB::Write; 160810037SARM gem5 Developers break; 160910037SARM gem5 Developers case MISCREG_ATS12NSOUR: 161010037SARM gem5 Developers if (!haveSecurity) 161110037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 161210037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 161310037SARM gem5 Developers tranType = TLB::S1S2NsTran; 161410037SARM gem5 Developers mode = BaseTLB::Read; 161510037SARM gem5 Developers break; 161610037SARM gem5 Developers case MISCREG_ATS12NSOUW: 161710037SARM gem5 Developers if (!haveSecurity) 161810037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 161910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 162010037SARM gem5 Developers tranType = TLB::S1S2NsTran; 162110037SARM gem5 Developers mode = BaseTLB::Write; 162210037SARM gem5 Developers break; 162310037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 162410037SARM gem5 Developers flags = TLB::MustBeOne; 162510037SARM gem5 Developers tranType = TLB::HypMode; 162610037SARM gem5 Developers mode = BaseTLB::Read; 162710037SARM gem5 Developers break; 162810037SARM gem5 Developers case MISCREG_ATS1HW: 162910037SARM gem5 Developers flags = TLB::MustBeOne; 163010037SARM gem5 Developers tranType = TLB::HypMode; 163110037SARM gem5 Developers mode = BaseTLB::Write; 163210037SARM gem5 Developers break; 16337436Sdam.sunwoo@arm.com } 163410037SARM gem5 Developers // If we're in timing mode then doing the translation in 163510037SARM gem5 Developers // functional mode then we're slightly distorting performance 163610037SARM gem5 Developers // results obtained from simulations. The translation should be 163710037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 163810037SARM gem5 Developers // can't be an atomic translation because that causes problems 163910037SARM gem5 Developers // with unexpected atomic snoop requests. 164010037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 164112749Sgiacomo.travaglini@arm.com 164212749Sgiacomo.travaglini@arm.com auto req = std::make_shared<Request>( 164312749Sgiacomo.travaglini@arm.com 0, val, 0, flags, Request::funcMasterId, 164412749Sgiacomo.travaglini@arm.com tc->pcState().pc(), tc->contextId()); 164512749Sgiacomo.travaglini@arm.com 164612406Sgabeblack@google.com fault = getDTBPtr(tc)->translateFunctional( 164712749Sgiacomo.travaglini@arm.com req, tc, mode, tranType); 164812749Sgiacomo.travaglini@arm.com 164910037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 165010037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 165110037SARM gem5 Developers 165210037SARM gem5 Developers MiscReg newVal; 16537436Sdam.sunwoo@arm.com if (fault == NoFault) { 165412749Sgiacomo.travaglini@arm.com Addr paddr = req->getPaddr(); 165510037SARM gem5 Developers if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 165610037SARM gem5 Developers ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 165710037SARM gem5 Developers newVal = (paddr & mask(39, 12)) | 165812406Sgabeblack@google.com (getDTBPtr(tc)->getAttr()); 165910037SARM gem5 Developers } else { 166010037SARM gem5 Developers newVal = (paddr & 0xfffff000) | 166112406Sgabeblack@google.com (getDTBPtr(tc)->getAttr()); 166210037SARM gem5 Developers } 16637436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 16647436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 166510037SARM gem5 Developers val, newVal); 166610037SARM gem5 Developers } else { 166712524Sgiacomo.travaglini@arm.com ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 166812570Sgiacomo.travaglini@arm.com armFault->update(tc); 166910037SARM gem5 Developers // Set fault bit and FSR 167010037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 167110037SARM gem5 Developers 167210037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 167310037SARM gem5 Developers if (newVal) { 167410037SARM gem5 Developers // LPAE - rearange fault status 167510037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 167610037SARM gem5 Developers } else { 167710037SARM gem5 Developers // VMSA - rearange fault status 167810037SARM gem5 Developers newVal |= ((fsr >> 0) & 0xf) << 1; 167910037SARM gem5 Developers newVal |= ((fsr >> 10) & 0x1) << 5; 168010037SARM gem5 Developers newVal |= ((fsr >> 12) & 0x1) << 6; 168110037SARM gem5 Developers } 168210037SARM gem5 Developers newVal |= 0x1; // F bit 168310037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 168410037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 168510037SARM gem5 Developers DPRINTF(MiscRegs, 168610037SARM gem5 Developers "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 168710037SARM gem5 Developers val, fsr, newVal); 16887436Sdam.sunwoo@arm.com } 168910037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 16907436Sdam.sunwoo@arm.com return; 16917436Sdam.sunwoo@arm.com } 169210037SARM gem5 Developers case MISCREG_TTBCR: 169310037SARM gem5 Developers { 169410037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 169510037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 169610037SARM gem5 Developers TTBCR ttbcrMask = 0; 169710037SARM gem5 Developers TTBCR ttbcrNew = newVal; 169810037SARM gem5 Developers 169910037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 170010037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 170110037SARM gem5 Developers if (haveSecurity) { 170210037SARM gem5 Developers ttbcrMask.pd0 = ones; 170310037SARM gem5 Developers ttbcrMask.pd1 = ones; 170410037SARM gem5 Developers } 170510037SARM gem5 Developers ttbcrMask.epd0 = ones; 170610037SARM gem5 Developers ttbcrMask.irgn0 = ones; 170710037SARM gem5 Developers ttbcrMask.orgn0 = ones; 170810037SARM gem5 Developers ttbcrMask.sh0 = ones; 170910037SARM gem5 Developers ttbcrMask.ps = ones; // T1SZ 171010037SARM gem5 Developers ttbcrMask.a1 = ones; 171110037SARM gem5 Developers ttbcrMask.epd1 = ones; 171210037SARM gem5 Developers ttbcrMask.irgn1 = ones; 171310037SARM gem5 Developers ttbcrMask.orgn1 = ones; 171410037SARM gem5 Developers ttbcrMask.sh1 = ones; 171510037SARM gem5 Developers if (haveLPAE) 171610037SARM gem5 Developers ttbcrMask.eae = ones; 171710037SARM gem5 Developers 171810037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 171910037SARM gem5 Developers newVal = newVal & ttbcrMask; 172010037SARM gem5 Developers } else { 172110037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 172210037SARM gem5 Developers } 172312666Sgiacomo.travaglini@arm.com // Invalidate TLB MiscReg 172412666Sgiacomo.travaglini@arm.com getITBPtr(tc)->invalidateMiscReg(); 172512666Sgiacomo.travaglini@arm.com getDTBPtr(tc)->invalidateMiscReg(); 172612666Sgiacomo.travaglini@arm.com break; 172710037SARM gem5 Developers } 172810037SARM gem5 Developers case MISCREG_TTBR0: 172910037SARM gem5 Developers case MISCREG_TTBR1: 173010037SARM gem5 Developers { 173110037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 173210037SARM gem5 Developers if (haveLPAE) { 173310037SARM gem5 Developers if (ttbcr.eae) { 173410037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 173510037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 173610037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 173710037SARM gem5 Developers newVal = (newVal & (~ttbrMask)); 173810037SARM gem5 Developers } 173910037SARM gem5 Developers } 174012666Sgiacomo.travaglini@arm.com // Invalidate TLB MiscReg 174112406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 174212406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 174312666Sgiacomo.travaglini@arm.com break; 174410508SAli.Saidi@ARM.com } 174512666Sgiacomo.travaglini@arm.com case MISCREG_SCTLR_EL1: 17467749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 17477749SAli.Saidi@ARM.com case MISCREG_PRRR: 17487749SAli.Saidi@ARM.com case MISCREG_NMRR: 174910037SARM gem5 Developers case MISCREG_MAIR0: 175010037SARM gem5 Developers case MISCREG_MAIR1: 17517749SAli.Saidi@ARM.com case MISCREG_DACR: 175210037SARM gem5 Developers case MISCREG_VTTBR: 175310037SARM gem5 Developers case MISCREG_SCR_EL3: 175411575SDylan.Johnson@ARM.com case MISCREG_HCR_EL2: 175510037SARM gem5 Developers case MISCREG_TCR_EL1: 175610037SARM gem5 Developers case MISCREG_TCR_EL2: 175710037SARM gem5 Developers case MISCREG_TCR_EL3: 175810508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL2: 175910508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL3: 176011573SDylan.Johnson@ARM.com case MISCREG_HSCTLR: 176110037SARM gem5 Developers case MISCREG_TTBR0_EL1: 176210037SARM gem5 Developers case MISCREG_TTBR1_EL1: 176310037SARM gem5 Developers case MISCREG_TTBR0_EL2: 176412675Sgiacomo.travaglini@arm.com case MISCREG_TTBR1_EL2: 176510037SARM gem5 Developers case MISCREG_TTBR0_EL3: 176612406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 176712406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 17687749SAli.Saidi@ARM.com break; 176910037SARM gem5 Developers case MISCREG_NZCV: 177010037SARM gem5 Developers { 177110037SARM gem5 Developers CPSR cpsr = val; 177210037SARM gem5 Developers 177310338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_NZ, cpsr.nz); 177410338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_C, cpsr.c); 177510338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_V, cpsr.v); 177610037SARM gem5 Developers } 177710037SARM gem5 Developers break; 177810037SARM gem5 Developers case MISCREG_DAIF: 177910037SARM gem5 Developers { 178010037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 178110037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 178210037SARM gem5 Developers newVal = cpsr; 178310037SARM gem5 Developers misc_reg = MISCREG_CPSR; 178410037SARM gem5 Developers } 178510037SARM gem5 Developers break; 178610037SARM gem5 Developers case MISCREG_SP_EL0: 178710037SARM gem5 Developers tc->setIntReg(INTREG_SP0, newVal); 178810037SARM gem5 Developers break; 178910037SARM gem5 Developers case MISCREG_SP_EL1: 179010037SARM gem5 Developers tc->setIntReg(INTREG_SP1, newVal); 179110037SARM gem5 Developers break; 179210037SARM gem5 Developers case MISCREG_SP_EL2: 179310037SARM gem5 Developers tc->setIntReg(INTREG_SP2, newVal); 179410037SARM gem5 Developers break; 179510037SARM gem5 Developers case MISCREG_SPSEL: 179610037SARM gem5 Developers { 179710037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 179810037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 179910037SARM gem5 Developers newVal = cpsr; 180010037SARM gem5 Developers misc_reg = MISCREG_CPSR; 180110037SARM gem5 Developers } 180210037SARM gem5 Developers break; 180310037SARM gem5 Developers case MISCREG_CURRENTEL: 180410037SARM gem5 Developers { 180510037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 180610037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 180710037SARM gem5 Developers newVal = cpsr; 180810037SARM gem5 Developers misc_reg = MISCREG_CPSR; 180910037SARM gem5 Developers } 181010037SARM gem5 Developers break; 181110037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 181210037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 181310037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 181410037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 181510037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 181610037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 181710037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 181810037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 181910037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 182010037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 182110037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 182210037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 182310037SARM gem5 Developers { 182412749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>(); 182511608Snikos.nikoleris@arm.com Request::Flags flags = 0; 182610037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 182710037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 182810037SARM gem5 Developers Fault fault; 182910037SARM gem5 Developers switch(misc_reg) { 183010037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 183110037SARM gem5 Developers flags = TLB::MustBeOne; 183211577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 183310037SARM gem5 Developers mode = BaseTLB::Read; 183410037SARM gem5 Developers break; 183510037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 183610037SARM gem5 Developers flags = TLB::MustBeOne; 183711577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 183810037SARM gem5 Developers mode = BaseTLB::Write; 183910037SARM gem5 Developers break; 184010037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 184110037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 184211577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 184310037SARM gem5 Developers mode = BaseTLB::Read; 184410037SARM gem5 Developers break; 184510037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 184610037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 184711577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 184810037SARM gem5 Developers mode = BaseTLB::Write; 184910037SARM gem5 Developers break; 185010037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 185110037SARM gem5 Developers flags = TLB::MustBeOne; 185211577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 185310037SARM gem5 Developers mode = BaseTLB::Read; 185410037SARM gem5 Developers break; 185510037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 185610037SARM gem5 Developers flags = TLB::MustBeOne; 185711577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 185810037SARM gem5 Developers mode = BaseTLB::Write; 185910037SARM gem5 Developers break; 186010037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 186110037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 186211577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 186310037SARM gem5 Developers mode = BaseTLB::Read; 186410037SARM gem5 Developers break; 186510037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 186610037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 186711577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 186810037SARM gem5 Developers mode = BaseTLB::Write; 186910037SARM gem5 Developers break; 187010037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 187110037SARM gem5 Developers flags = TLB::MustBeOne; 187211577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 187310037SARM gem5 Developers mode = BaseTLB::Read; 187410037SARM gem5 Developers break; 187510037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 187610037SARM gem5 Developers flags = TLB::MustBeOne; 187711577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 187810037SARM gem5 Developers mode = BaseTLB::Write; 187910037SARM gem5 Developers break; 188010037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 188110037SARM gem5 Developers flags = TLB::MustBeOne; 188211577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 188310037SARM gem5 Developers mode = BaseTLB::Read; 188410037SARM gem5 Developers break; 188510037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 188610037SARM gem5 Developers flags = TLB::MustBeOne; 188711577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 188810037SARM gem5 Developers mode = BaseTLB::Write; 188910037SARM gem5 Developers break; 189010037SARM gem5 Developers } 189110037SARM gem5 Developers // If we're in timing mode then doing the translation in 189210037SARM gem5 Developers // functional mode then we're slightly distorting performance 189310037SARM gem5 Developers // results obtained from simulations. The translation should be 189410037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 189510037SARM gem5 Developers // can't be an atomic translation because that causes problems 189610037SARM gem5 Developers // with unexpected atomic snoop requests. 189710037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 189811560Sandreas.sandberg@arm.com req->setVirt(0, val, 0, flags, Request::funcMasterId, 189910037SARM gem5 Developers tc->pcState().pc()); 190011435Smitch.hayenga@arm.com req->setContext(tc->contextId()); 190112406Sgabeblack@google.com fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 190212406Sgabeblack@google.com tranType); 190310037SARM gem5 Developers 190410037SARM gem5 Developers MiscReg newVal; 190510037SARM gem5 Developers if (fault == NoFault) { 190610037SARM gem5 Developers Addr paddr = req->getPaddr(); 190712406Sgabeblack@google.com uint64_t attr = getDTBPtr(tc)->getAttr(); 190810037SARM gem5 Developers uint64_t attr1 = attr >> 56; 190910037SARM gem5 Developers if (!attr1 || attr1 ==0x44) { 191010037SARM gem5 Developers attr |= 0x100; 191110037SARM gem5 Developers attr &= ~ uint64_t(0x80); 191210037SARM gem5 Developers } 191310037SARM gem5 Developers newVal = (paddr & mask(47, 12)) | attr; 191410037SARM gem5 Developers DPRINTF(MiscRegs, 191510037SARM gem5 Developers "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 191610037SARM gem5 Developers val, newVal); 191710037SARM gem5 Developers } else { 191812524Sgiacomo.travaglini@arm.com ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 191912570Sgiacomo.travaglini@arm.com armFault->update(tc); 192010037SARM gem5 Developers // Set fault bit and FSR 192110037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 192210037SARM gem5 Developers 192311577SDylan.Johnson@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 192411577SDylan.Johnson@ARM.com if (cpsr.width) { // AArch32 192511577SDylan.Johnson@ARM.com newVal = ((fsr >> 9) & 1) << 11; 192611577SDylan.Johnson@ARM.com // rearrange fault status 192711577SDylan.Johnson@ARM.com newVal |= ((fsr >> 0) & 0x3f) << 1; 192811577SDylan.Johnson@ARM.com newVal |= 0x1; // F bit 192911577SDylan.Johnson@ARM.com newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 193011577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 0x200 : 0; 193111577SDylan.Johnson@ARM.com } else { // AArch64 193211577SDylan.Johnson@ARM.com newVal = 1; // F bit 193311577SDylan.Johnson@ARM.com newVal |= fsr << 1; // FST 193411577SDylan.Johnson@ARM.com // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 193511577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 193611577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 193711577SDylan.Johnson@ARM.com newVal |= 1 << 11; // RES1 193811577SDylan.Johnson@ARM.com } 193910037SARM gem5 Developers DPRINTF(MiscRegs, 194010037SARM gem5 Developers "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 194110037SARM gem5 Developers val, fsr, newVal); 194210037SARM gem5 Developers } 194310037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 194410037SARM gem5 Developers return; 194510037SARM gem5 Developers } 194610037SARM gem5 Developers case MISCREG_SPSR_EL3: 194710037SARM gem5 Developers case MISCREG_SPSR_EL2: 194810037SARM gem5 Developers case MISCREG_SPSR_EL1: 194910037SARM gem5 Developers // Force bits 23:21 to 0 195010037SARM gem5 Developers newVal = val & ~(0x7 << 21); 195110037SARM gem5 Developers break; 19528549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 19538549Sdaniel.johnson@arm.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 19548549Sdaniel.johnson@arm.com miscRegName[misc_reg], uint32_t(val)); 195510037SARM gem5 Developers break; 195610037SARM gem5 Developers 195710037SARM gem5 Developers // Generic Timer registers 195812816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CTL_EL2: 195912816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CVAL_EL2: 196012816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_TVAL_EL2: 196110844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 196210844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 196310844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 196410844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 196510844Sandreas.sandberg@arm.com getGenericTimer(tc).setMiscReg(misc_reg, newVal); 196610037SARM gem5 Developers break; 19677405SAli.Saidi@ARM.com } 19687405SAli.Saidi@ARM.com } 19697405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 19707405SAli.Saidi@ARM.com} 19717405SAli.Saidi@ARM.com 197210844Sandreas.sandberg@arm.comBaseISADevice & 197310844Sandreas.sandberg@arm.comISA::getGenericTimer(ThreadContext *tc) 197410037SARM gem5 Developers{ 197510844Sandreas.sandberg@arm.com // We only need to create an ISA interface the first time we try 197610844Sandreas.sandberg@arm.com // to access the timer. 197710844Sandreas.sandberg@arm.com if (timer) 197810844Sandreas.sandberg@arm.com return *timer.get(); 197910844Sandreas.sandberg@arm.com 198010844Sandreas.sandberg@arm.com assert(system); 198110844Sandreas.sandberg@arm.com GenericTimer *generic_timer(system->getGenericTimer()); 198210844Sandreas.sandberg@arm.com if (!generic_timer) { 198310844Sandreas.sandberg@arm.com panic("Trying to get a generic timer from a system that hasn't " 198410844Sandreas.sandberg@arm.com "been configured to use a generic timer.\n"); 198510037SARM gem5 Developers } 198610037SARM gem5 Developers 198711150Smitch.hayenga@arm.com timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 198812972Sandreas.sandberg@arm.com timer->setThreadContext(tc); 198912972Sandreas.sandberg@arm.com 199010844Sandreas.sandberg@arm.com return *timer.get(); 199110037SARM gem5 Developers} 199210037SARM gem5 Developers 19937405SAli.Saidi@ARM.com} 19949384SAndreas.Sandberg@arm.com 19959384SAndreas.Sandberg@arm.comArmISA::ISA * 19969384SAndreas.Sandberg@arm.comArmISAParams::create() 19979384SAndreas.Sandberg@arm.com{ 19989384SAndreas.Sandberg@arm.com return new ArmISA::ISA(this); 19999384SAndreas.Sandberg@arm.com} 2000