isa.cc revision 12763
12221SN/A/* 22221SN/A * Copyright (c) 2010-2018 ARM Limited 32221SN/A * All rights reserved 42221SN/A * 52221SN/A * The license below extends only to copyright in the software and shall 62221SN/A * not be construed as granting a license to any other intellectual 72221SN/A * property including but not limited to intellectual property relating 82221SN/A * to a hardware implementation of the functionality of the software 92221SN/A * licensed hereunder. You may use the software subject to the license 102221SN/A * terms below provided that you ensure that this notice is replicated 112221SN/A * unmodified and in its entirety in all distributions of the software, 122221SN/A * modified or unmodified, in source code or in binary form. 132221SN/A * 142221SN/A * Redistribution and use in source and binary forms, with or without 152221SN/A * modification, are permitted provided that the following conditions are 162221SN/A * met: redistributions of source code must retain the above copyright 172221SN/A * notice, this list of conditions and the following disclaimer; 182221SN/A * redistributions in binary form must reproduce the above copyright 192221SN/A * notice, this list of conditions and the following disclaimer in the 202221SN/A * documentation and/or other materials provided with the distribution; 212221SN/A * neither the name of the copyright holders nor the names of its 222221SN/A * contributors may be used to endorse or promote products derived from 232221SN/A * this software without specific prior written permission. 242221SN/A * 252221SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262221SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302221SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312221SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3211793Sbrandon.potter@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3311793Sbrandon.potter@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 343415Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 353415Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 363415Sgblack@eecs.umich.edu * 378778Sgblack@eecs.umich.edu * Authors: Gabe Black 383578Sgblack@eecs.umich.edu * Ali Saidi 393415Sgblack@eecs.umich.edu */ 403415Sgblack@eecs.umich.edu 413415Sgblack@eecs.umich.edu#include "arch/arm/isa.hh" 422680Sktlim@umich.edu#include "arch/arm/pmu.hh" 433415Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 4411793Sbrandon.potter@amd.com#include "arch/arm/tlb.hh" 452800Ssaidi@eecs.umich.edu#include "arch/arm/tlbi_op.hh" 462221SN/A#include "cpu/base.hh" 473415Sgblack@eecs.umich.edu#include "cpu/checker/cpu.hh" 483415Sgblack@eecs.umich.edu#include "debug/Arm.hh" 492223SN/A#include "debug/MiscRegs.hh" 502221SN/A#include "dev/arm/generic_timer.hh" 512221SN/A#include "params/ArmISA.hh" 523573Sgblack@eecs.umich.edu#include "sim/faults.hh" 533576Sgblack@eecs.umich.edu#include "sim/stat_control.hh" 549551Sandreas.hansson@arm.com#include "sim/system.hh" 552221SN/A 563573Sgblack@eecs.umich.edunamespace ArmISA 573576Sgblack@eecs.umich.edu{ 589551Sandreas.hansson@arm.com 592221SN/AISA::ISA(Params *p) 603573Sgblack@eecs.umich.edu : SimObject(p), 613576Sgblack@eecs.umich.edu system(NULL), 629551Sandreas.hansson@arm.com _decoderFlavour(p->decoderFlavour), 632221SN/A _vecRegRenameMode(p->vecRegRenameMode), 643573Sgblack@eecs.umich.edu pmu(p->pmu), 653576Sgblack@eecs.umich.edu impdefAsNop(p->impdef_nop) 669551Sandreas.hansson@arm.com{ 672221SN/A miscRegs[MISCREG_SCTLR_RST] = 0; 683573Sgblack@eecs.umich.edu 693576Sgblack@eecs.umich.edu // Hook up a dummy device if we haven't been configured with a 709551Sandreas.hansson@arm.com // real PMU. By using a dummy device, we don't need to check that 712221SN/A // the PMU exist every time we try to access a PMU register. 723573Sgblack@eecs.umich.edu if (!pmu) 733576Sgblack@eecs.umich.edu pmu = &dummyDevice; 749551Sandreas.hansson@arm.com 752221SN/A // Give all ISA devices a pointer to this ISA 763573Sgblack@eecs.umich.edu pmu->setISA(this); 773576Sgblack@eecs.umich.edu 789551Sandreas.hansson@arm.com system = dynamic_cast<ArmSystem *>(p->system); 793576Sgblack@eecs.umich.edu 803576Sgblack@eecs.umich.edu // Cache system-level properties 813576Sgblack@eecs.umich.edu if (FullSystem && system) { 823576Sgblack@eecs.umich.edu highestELIs64 = system->highestELIs64(); 833576Sgblack@eecs.umich.edu haveSecurity = system->haveSecurity(); 842221SN/A haveLPAE = system->haveLPAE(); 853573Sgblack@eecs.umich.edu haveVirtualization = system->haveVirtualization(); 863576Sgblack@eecs.umich.edu haveLargeAsid64 = system->haveLargeAsid64(); 879551Sandreas.hansson@arm.com physAddrRange64 = system->physAddrRange64(); 882221SN/A } else { 893573Sgblack@eecs.umich.edu highestELIs64 = true; // ArmSystem::highestELIs64 does the same 903576Sgblack@eecs.umich.edu haveSecurity = haveLPAE = haveVirtualization = false; 919551Sandreas.hansson@arm.com haveLargeAsid64 = false; 922221SN/A physAddrRange64 = 32; // dummy value 933573Sgblack@eecs.umich.edu } 943576Sgblack@eecs.umich.edu 959551Sandreas.hansson@arm.com initializeMiscRegMetadata(); 963576Sgblack@eecs.umich.edu preUnflattenMiscReg(); 973576Sgblack@eecs.umich.edu 983576Sgblack@eecs.umich.edu clear(); 993576Sgblack@eecs.umich.edu} 1003576Sgblack@eecs.umich.edu 1013576Sgblack@eecs.umich.edustd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 1023576Sgblack@eecs.umich.edu 1033576Sgblack@eecs.umich.educonst ArmISAParams * 1043576Sgblack@eecs.umich.eduISA::params() const 1053576Sgblack@eecs.umich.edu{ 1062221SN/A return dynamic_cast<const Params *>(_params); 1073573Sgblack@eecs.umich.edu} 1083576Sgblack@eecs.umich.edu 1099551Sandreas.hansson@arm.comvoid 1102221SN/AISA::clear() 1113573Sgblack@eecs.umich.edu{ 1123576Sgblack@eecs.umich.edu const Params *p(params()); 1139551Sandreas.hansson@arm.com 1142221SN/A SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 1153573Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 1163576Sgblack@eecs.umich.edu 1179551Sandreas.hansson@arm.com // Initialize configurable default values 1182221SN/A miscRegs[MISCREG_MIDR] = p->midr; 1193573Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR_EL1] = p->midr; 1203576Sgblack@eecs.umich.edu miscRegs[MISCREG_VPIDR] = p->midr; 1219551Sandreas.hansson@arm.com 1222221SN/A miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 1233573Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 1243576Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 1259551Sandreas.hansson@arm.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 1262221SN/A miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 1273573Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 1283576Sgblack@eecs.umich.edu 1299551Sandreas.hansson@arm.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 1302223SN/A miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 1313573Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 1323576Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 1339551Sandreas.hansson@arm.com 1342223SN/A if (FullSystem && system->highestELIs64()) { 1353573Sgblack@eecs.umich.edu // Initialize AArch64 state 1363576Sgblack@eecs.umich.edu clear64(p); 1379551Sandreas.hansson@arm.com return; 1382223SN/A } 1393573Sgblack@eecs.umich.edu 1403576Sgblack@eecs.umich.edu // Initialize AArch32 state... 1419551Sandreas.hansson@arm.com 1422223SN/A CPSR cpsr = 0; 1433573Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 1443576Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 1459551Sandreas.hansson@arm.com updateRegMap(cpsr); 1463576Sgblack@eecs.umich.edu 1473576Sgblack@eecs.umich.edu SCTLR sctlr = 0; 1483576Sgblack@eecs.umich.edu sctlr.te = (bool) sctlr_rst.te; 1493576Sgblack@eecs.umich.edu sctlr.nmfi = (bool) sctlr_rst.nmfi; 1503576Sgblack@eecs.umich.edu sctlr.v = (bool) sctlr_rst.v; 1512223SN/A sctlr.u = 1; 1523573Sgblack@eecs.umich.edu sctlr.xp = 1; 1533576Sgblack@eecs.umich.edu sctlr.rao2 = 1; 1549551Sandreas.hansson@arm.com sctlr.rao3 = 1; 1552223SN/A sctlr.rao4 = 0xf; // SCTLR[6:3] 1563573Sgblack@eecs.umich.edu sctlr.uci = 1; 1573576Sgblack@eecs.umich.edu sctlr.dze = 1; 1589551Sandreas.hansson@arm.com miscRegs[MISCREG_SCTLR_NS] = sctlr; 1592223SN/A miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 1603573Sgblack@eecs.umich.edu miscRegs[MISCREG_HCPTR] = 0; 1613576Sgblack@eecs.umich.edu 1629551Sandreas.hansson@arm.com // Start with an event in the mailbox 1632223SN/A miscRegs[MISCREG_SEV_MAILBOX] = 1; 1643573Sgblack@eecs.umich.edu 1653576Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs 1669551Sandreas.hansson@arm.com miscRegs[MISCREG_TLBTR] = 1; 1672223SN/A 1683573Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 1693576Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 1709551Sandreas.hansson@arm.com mvfr0.singlePrecision = 2; 1712223SN/A mvfr0.doublePrecision = 2; 1723573Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 1733576Sgblack@eecs.umich.edu mvfr0.divide = 1; 1749551Sandreas.hansson@arm.com mvfr0.squareRoot = 1; 1752223SN/A mvfr0.shortVectors = 1; 1763573Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 1773576Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 1789551Sandreas.hansson@arm.com 1792223SN/A MVFR1 mvfr1 = 0; 1803573Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1813576Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1829551Sandreas.hansson@arm.com mvfr1.advSimdLoadStore = 1; 1832223SN/A mvfr1.advSimdInteger = 1; 1843573Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1853576Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1869551Sandreas.hansson@arm.com mvfr1.vfpHalfPrecision = 1; 1872223SN/A miscRegs[MISCREG_MVFR1] = mvfr1; 1883573Sgblack@eecs.umich.edu 1893576Sgblack@eecs.umich.edu // Reset values of PRRR and NMRR are implementation dependent 1909551Sandreas.hansson@arm.com 1912223SN/A // @todo: PRRR and NMRR in secure state? 1923576Sgblack@eecs.umich.edu miscRegs[MISCREG_PRRR_NS] = 1933576Sgblack@eecs.umich.edu (1 << 19) | // 19 1943576Sgblack@eecs.umich.edu (0 << 18) | // 18 1953576Sgblack@eecs.umich.edu (0 << 17) | // 17 1962527SN/A (1 << 16) | // 16 1973573Sgblack@eecs.umich.edu (2 << 14) | // 15:14 1983576Sgblack@eecs.umich.edu (0 << 12) | // 13:12 1999551Sandreas.hansson@arm.com (2 << 10) | // 11:10 2002223SN/A (2 << 8) | // 9:8 2013573Sgblack@eecs.umich.edu (2 << 6) | // 7:6 2023576Sgblack@eecs.umich.edu (2 << 4) | // 5:4 2039551Sandreas.hansson@arm.com (1 << 2) | // 3:2 2042223SN/A 0; // 1:0 2053573Sgblack@eecs.umich.edu miscRegs[MISCREG_NMRR_NS] = 2063576Sgblack@eecs.umich.edu (1 << 30) | // 31:30 2079551Sandreas.hansson@arm.com (0 << 26) | // 27:26 2082223SN/A (0 << 24) | // 25:24 2093573Sgblack@eecs.umich.edu (3 << 22) | // 23:22 2104103Ssaidi@eecs.umich.edu (2 << 20) | // 21:20 2119551Sandreas.hansson@arm.com (0 << 18) | // 19:18 2124103Ssaidi@eecs.umich.edu (0 << 16) | // 17:16 2134103Ssaidi@eecs.umich.edu (1 << 14) | // 15:14 2143576Sgblack@eecs.umich.edu (0 << 12) | // 13:12 2159551Sandreas.hansson@arm.com (2 << 10) | // 11:10 2162223SN/A (0 << 8) | // 9:8 2173573Sgblack@eecs.umich.edu (3 << 6) | // 7:6 2183576Sgblack@eecs.umich.edu (2 << 4) | // 5:4 2199551Sandreas.hansson@arm.com (0 << 2) | // 3:2 2202223SN/A 0; // 1:0 2213573Sgblack@eecs.umich.edu 2223576Sgblack@eecs.umich.edu miscRegs[MISCREG_CPACR] = 0; 2239551Sandreas.hansson@arm.com 2243576Sgblack@eecs.umich.edu miscRegs[MISCREG_FPSID] = p->fpsid; 2253576Sgblack@eecs.umich.edu 2263576Sgblack@eecs.umich.edu if (haveLPAE) { 2279551Sandreas.hansson@arm.com TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 2283576Sgblack@eecs.umich.edu ttbcr.eae = 0; 2293576Sgblack@eecs.umich.edu miscRegs[MISCREG_TTBCR_NS] = ttbcr; 2303576Sgblack@eecs.umich.edu // Enforce consistency with system-level settings 2319551Sandreas.hansson@arm.com miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 2323576Sgblack@eecs.umich.edu } 2333576Sgblack@eecs.umich.edu 2343576Sgblack@eecs.umich.edu if (haveSecurity) { 2359551Sandreas.hansson@arm.com miscRegs[MISCREG_SCTLR_S] = sctlr; 2363576Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR] = 0; 2373576Sgblack@eecs.umich.edu miscRegs[MISCREG_VBAR_S] = 0; 2383576Sgblack@eecs.umich.edu } else { 2399551Sandreas.hansson@arm.com // we're always non-secure 2403576Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR] = 1; 2413576Sgblack@eecs.umich.edu } 2423576Sgblack@eecs.umich.edu 2439551Sandreas.hansson@arm.com //XXX We need to initialize the rest of the state. 2443576Sgblack@eecs.umich.edu} 2453576Sgblack@eecs.umich.edu 2463893Shsul@eecs.umich.eduvoid 2479551Sandreas.hansson@arm.comISA::clear64(const ArmISAParams *p) 2483576Sgblack@eecs.umich.edu{ 2493576Sgblack@eecs.umich.edu CPSR cpsr = 0; 2503576Sgblack@eecs.umich.edu Addr rvbar = system->resetAddr64(); 2519551Sandreas.hansson@arm.com switch (system->highestEL()) { 2523576Sgblack@eecs.umich.edu // Set initial EL to highest implemented EL using associated stack 2533576Sgblack@eecs.umich.edu // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 2543576Sgblack@eecs.umich.edu // value 2559551Sandreas.hansson@arm.com case EL3: 2563576Sgblack@eecs.umich.edu cpsr.mode = MODE_EL3H; 2573576Sgblack@eecs.umich.edu miscRegs[MISCREG_RVBAR_EL3] = rvbar; 2583576Sgblack@eecs.umich.edu break; 2599551Sandreas.hansson@arm.com case EL2: 2603576Sgblack@eecs.umich.edu cpsr.mode = MODE_EL2H; 2613576Sgblack@eecs.umich.edu miscRegs[MISCREG_RVBAR_EL2] = rvbar; 2623576Sgblack@eecs.umich.edu break; 2639551Sandreas.hansson@arm.com case EL1: 2643576Sgblack@eecs.umich.edu cpsr.mode = MODE_EL1H; 2653576Sgblack@eecs.umich.edu miscRegs[MISCREG_RVBAR_EL1] = rvbar; 2663576Sgblack@eecs.umich.edu break; 2679551Sandreas.hansson@arm.com default: 2682223SN/A panic("Invalid highest implemented exception level"); 2693415Sgblack@eecs.umich.edu break; 2703578Sgblack@eecs.umich.edu } 2713578Sgblack@eecs.umich.edu 2723415Sgblack@eecs.umich.edu // Initialize rest of CPSR 2733415Sgblack@eecs.umich.edu cpsr.daif = 0xf; // Mask all interrupts 2747741Sgblack@eecs.umich.edu cpsr.ss = 0; 2757741Sgblack@eecs.umich.edu cpsr.il = 0; 2763415Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 2773578Sgblack@eecs.umich.edu updateRegMap(cpsr); 2783578Sgblack@eecs.umich.edu 2798829Sgblack@eecs.umich.edu // Initialize other control registers 2808829Sgblack@eecs.umich.edu miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 2818829Sgblack@eecs.umich.edu if (haveSecurity) { 2828829Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 2837741Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 2847741Sgblack@eecs.umich.edu } else if (haveVirtualization) { 2858829Sgblack@eecs.umich.edu // also MISCREG_SCTLR_EL2 (by mapping) 2868829Sgblack@eecs.umich.edu miscRegs[MISCREG_HSCTLR] = 0x30c50830; 2878829Sgblack@eecs.umich.edu } else { 2883578Sgblack@eecs.umich.edu // also MISCREG_SCTLR_EL1 (by mapping) 2893578Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 2903578Sgblack@eecs.umich.edu // Always non-secure 2913578Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR_EL3] = 1; 2923578Sgblack@eecs.umich.edu } 2933578Sgblack@eecs.umich.edu 2943578Sgblack@eecs.umich.edu // Initialize configurable id registers 2957741Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 2967741Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 2973578Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64DFR0_EL1] = 2984172Ssaidi@eecs.umich.edu (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 2994172Ssaidi@eecs.umich.edu (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 3008829Sgblack@eecs.umich.edu 3018829Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 3023761Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 3034172Ssaidi@eecs.umich.edu miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 3044172Ssaidi@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 3054172Ssaidi@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 3064172Ssaidi@eecs.umich.edu 3077720Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_DFR0_EL1] = 3083578Sgblack@eecs.umich.edu (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 3093578Sgblack@eecs.umich.edu 3103578Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 3118829Sgblack@eecs.umich.edu 3123928Ssaidi@eecs.umich.edu // Enforce consistency with system-level settings... 3137741Sgblack@eecs.umich.edu 3143578Sgblack@eecs.umich.edu // EL3 3157741Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 3163578Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 3177741Sgblack@eecs.umich.edu haveSecurity ? 0x2 : 0x0); 3183578Sgblack@eecs.umich.edu // EL2 3197741Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 3208829Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 3217741Sgblack@eecs.umich.edu haveVirtualization ? 0x2 : 0x0); 3223578Sgblack@eecs.umich.edu // Large ASID support 3233578Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 3247741Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 3254172Ssaidi@eecs.umich.edu haveLargeAsid64 ? 0x2 : 0x0); 3263578Sgblack@eecs.umich.edu // Physical address size 3277741Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 3287720Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 3297741Sgblack@eecs.umich.edu encodePhysAddrRange64(physAddrRange64)); 3307720Sgblack@eecs.umich.edu} 3313578Sgblack@eecs.umich.edu 3327741Sgblack@eecs.umich.eduMiscReg 3338829Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int misc_reg) const 3343578Sgblack@eecs.umich.edu{ 3357741Sgblack@eecs.umich.edu assert(misc_reg < NumMiscRegs); 3364172Ssaidi@eecs.umich.edu 3373578Sgblack@eecs.umich.edu const auto ® = lookUpMiscReg[misc_reg]; // bit masks 3387741Sgblack@eecs.umich.edu const auto &map = getMiscIndices(misc_reg); 3394172Ssaidi@eecs.umich.edu int lower = map.first, upper = map.second; 3403578Sgblack@eecs.umich.edu // NB!: apply architectural masks according to desired register, 3418829Sgblack@eecs.umich.edu // despite possibly getting value from different (mapped) register. 3428829Sgblack@eecs.umich.edu auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 3438829Sgblack@eecs.umich.edu |(miscRegs[upper] << 32)); 3448829Sgblack@eecs.umich.edu if (val & reg.res0()) { 3458829Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 3463578Sgblack@eecs.umich.edu miscRegName[misc_reg], val & reg.res0()); 3478829Sgblack@eecs.umich.edu } 3488829Sgblack@eecs.umich.edu if ((val & reg.res1()) != reg.res1()) { 3498829Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 3508829Sgblack@eecs.umich.edu miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 3518829Sgblack@eecs.umich.edu } 3523578Sgblack@eecs.umich.edu return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 3533578Sgblack@eecs.umich.edu} 3543893Shsul@eecs.umich.edu 3553415Sgblack@eecs.umich.edu 3563893Shsul@eecs.umich.eduMiscReg 3573415Sgblack@eecs.umich.eduISA::readMiscReg(int misc_reg, ThreadContext *tc) 3583893Shsul@eecs.umich.edu{ 3593415Sgblack@eecs.umich.edu CPSR cpsr = 0; 3603415Sgblack@eecs.umich.edu PCState pc = 0; 3613415Sgblack@eecs.umich.edu SCR scr = 0; 3623420Sgblack@eecs.umich.edu 3637741Sgblack@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 3643415Sgblack@eecs.umich.edu cpsr = miscRegs[misc_reg]; 3654172Ssaidi@eecs.umich.edu pc = tc->pcState(); 3663415Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 3673415Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 3683415Sgblack@eecs.umich.edu return cpsr; 3697741Sgblack@eecs.umich.edu } 3707741Sgblack@eecs.umich.edu 3717741Sgblack@eecs.umich.edu#ifndef NDEBUG 3727741Sgblack@eecs.umich.edu if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 3737741Sgblack@eecs.umich.edu if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 3747741Sgblack@eecs.umich.edu warn("Unimplemented system register %s read.\n", 3757741Sgblack@eecs.umich.edu miscRegName[misc_reg]); 3767741Sgblack@eecs.umich.edu else 3777741Sgblack@eecs.umich.edu panic("Unimplemented system register %s read.\n", 3787741Sgblack@eecs.umich.edu miscRegName[misc_reg]); 3798829Sgblack@eecs.umich.edu } 3808829Sgblack@eecs.umich.edu#endif 3817741Sgblack@eecs.umich.edu 3827741Sgblack@eecs.umich.edu switch (unflattenMiscReg(misc_reg)) { 3837741Sgblack@eecs.umich.edu case MISCREG_HCR: 3847741Sgblack@eecs.umich.edu { 3857741Sgblack@eecs.umich.edu if (!haveVirtualization) 3867741Sgblack@eecs.umich.edu return 0; 3877741Sgblack@eecs.umich.edu else 3887741Sgblack@eecs.umich.edu return readMiscRegNoEffect(MISCREG_HCR); 3897741Sgblack@eecs.umich.edu } 3907741Sgblack@eecs.umich.edu case MISCREG_CPACR: 3917741Sgblack@eecs.umich.edu { 3928829Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 3937741Sgblack@eecs.umich.edu CPACR cpacrMask = 0; 3947741Sgblack@eecs.umich.edu // Only cp10, cp11, and ase are implemented, nothing else should 3957741Sgblack@eecs.umich.edu // be readable? (straight copy from the write code) 3967741Sgblack@eecs.umich.edu cpacrMask.cp10 = ones; 3977741Sgblack@eecs.umich.edu cpacrMask.cp11 = ones; 3987741Sgblack@eecs.umich.edu cpacrMask.asedis = ones; 3997741Sgblack@eecs.umich.edu 4007741Sgblack@eecs.umich.edu // Security Extensions may limit the readability of CPACR 4017741Sgblack@eecs.umich.edu if (haveSecurity) { 4027741Sgblack@eecs.umich.edu scr = readMiscRegNoEffect(MISCREG_SCR); 4038829Sgblack@eecs.umich.edu cpsr = readMiscRegNoEffect(MISCREG_CPSR); 4047741Sgblack@eecs.umich.edu if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 4057741Sgblack@eecs.umich.edu NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 4067741Sgblack@eecs.umich.edu // NB: Skipping the full loop, here 4077741Sgblack@eecs.umich.edu if (!nsacr.cp10) cpacrMask.cp10 = 0; 4087741Sgblack@eecs.umich.edu if (!nsacr.cp11) cpacrMask.cp11 = 0; 4097741Sgblack@eecs.umich.edu } 4107741Sgblack@eecs.umich.edu } 4117741Sgblack@eecs.umich.edu MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 4127741Sgblack@eecs.umich.edu val &= cpacrMask; 4137741Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 4147741Sgblack@eecs.umich.edu miscRegName[misc_reg], val); 4157741Sgblack@eecs.umich.edu return val; 4168829Sgblack@eecs.umich.edu } 4177741Sgblack@eecs.umich.edu case MISCREG_MPIDR: 4187741Sgblack@eecs.umich.edu cpsr = readMiscRegNoEffect(MISCREG_CPSR); 4197741Sgblack@eecs.umich.edu scr = readMiscRegNoEffect(MISCREG_SCR); 4207741Sgblack@eecs.umich.edu if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 4217741Sgblack@eecs.umich.edu return getMPIDR(system, tc); 4227741Sgblack@eecs.umich.edu } else { 4237741Sgblack@eecs.umich.edu return readMiscReg(MISCREG_VMPIDR, tc); 4247741Sgblack@eecs.umich.edu } 4257741Sgblack@eecs.umich.edu break; 4267741Sgblack@eecs.umich.edu case MISCREG_MPIDR_EL1: 4278829Sgblack@eecs.umich.edu // @todo in the absence of v8 virtualization support just return MPIDR_EL1 4288829Sgblack@eecs.umich.edu return getMPIDR(system, tc) & 0xffffffff; 4298829Sgblack@eecs.umich.edu case MISCREG_VMPIDR: 4308829Sgblack@eecs.umich.edu // top bit defined as RES1 4318829Sgblack@eecs.umich.edu return readMiscRegNoEffect(misc_reg) | 0x80000000; 4328829Sgblack@eecs.umich.edu case MISCREG_ID_AFR0: // not implemented, so alias MIDR 4337741Sgblack@eecs.umich.edu case MISCREG_REVIDR: // not implemented, so alias MIDR 4347741Sgblack@eecs.umich.edu case MISCREG_MIDR: 4358829Sgblack@eecs.umich.edu cpsr = readMiscRegNoEffect(MISCREG_CPSR); 4367741Sgblack@eecs.umich.edu scr = readMiscRegNoEffect(MISCREG_SCR); 4378829Sgblack@eecs.umich.edu if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 4388829Sgblack@eecs.umich.edu return readMiscRegNoEffect(misc_reg); 4398829Sgblack@eecs.umich.edu } else { 4408829Sgblack@eecs.umich.edu return readMiscRegNoEffect(MISCREG_VPIDR); 4418829Sgblack@eecs.umich.edu } 4427741Sgblack@eecs.umich.edu break; 4438829Sgblack@eecs.umich.edu case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 4448829Sgblack@eecs.umich.edu case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 4457741Sgblack@eecs.umich.edu case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 4468829Sgblack@eecs.umich.edu case MISCREG_AIDR: // AUX ID set to 0 4477741Sgblack@eecs.umich.edu case MISCREG_TCMTR: // No TCM's 4487741Sgblack@eecs.umich.edu return 0; 4497741Sgblack@eecs.umich.edu 4507741Sgblack@eecs.umich.edu case MISCREG_CLIDR: 4517741Sgblack@eecs.umich.edu warn_once("The clidr register always reports 0 caches.\n"); 4527741Sgblack@eecs.umich.edu warn_once("clidr LoUIS field of 0b001 to match current " 4537741Sgblack@eecs.umich.edu "ARM implementations.\n"); 4547741Sgblack@eecs.umich.edu return 0x00200000; 4557741Sgblack@eecs.umich.edu case MISCREG_CCSIDR: 4567741Sgblack@eecs.umich.edu warn_once("The ccsidr register isn't implemented and " 4577741Sgblack@eecs.umich.edu "always reads as 0.\n"); 4587741Sgblack@eecs.umich.edu break; 4597741Sgblack@eecs.umich.edu case MISCREG_CTR: // AArch32, ARMv7, top bit set 4607741Sgblack@eecs.umich.edu case MISCREG_CTR_EL0: // AArch64 4617741Sgblack@eecs.umich.edu { 4627741Sgblack@eecs.umich.edu //all caches have the same line size in gem5 4637741Sgblack@eecs.umich.edu //4 byte words in ARM 4647741Sgblack@eecs.umich.edu unsigned lineSizeWords = 4657741Sgblack@eecs.umich.edu tc->getSystemPtr()->cacheLineSize() / 4; 4667741Sgblack@eecs.umich.edu unsigned log2LineSizeWords = 0; 4673578Sgblack@eecs.umich.edu 4683585Sgblack@eecs.umich.edu while (lineSizeWords >>= 1) { 4693603Ssaidi@eecs.umich.edu ++log2LineSizeWords; 4703595Sgblack@eecs.umich.edu } 4713578Sgblack@eecs.umich.edu 4723578Sgblack@eecs.umich.edu CTR ctr = 0; 4733578Sgblack@eecs.umich.edu //log2 of minimun i-cache line size (words) 4747741Sgblack@eecs.umich.edu ctr.iCacheLineSize = log2LineSizeWords; 4757741Sgblack@eecs.umich.edu //b11 - gem5 uses pipt 4763578Sgblack@eecs.umich.edu ctr.l1IndexPolicy = 0x3; 4774172Ssaidi@eecs.umich.edu //log2 of minimum d-cache line size (words) 4783578Sgblack@eecs.umich.edu ctr.dCacheLineSize = log2LineSizeWords; 4793578Sgblack@eecs.umich.edu //log2 of max reservation size (words) 4803578Sgblack@eecs.umich.edu ctr.erg = log2LineSizeWords; 4813578Sgblack@eecs.umich.edu //log2 of max writeback size (words) 4827741Sgblack@eecs.umich.edu ctr.cwg = log2LineSizeWords; 4837741Sgblack@eecs.umich.edu //b100 - gem5 format is ARMv7 4843578Sgblack@eecs.umich.edu ctr.format = 0x4; 4854172Ssaidi@eecs.umich.edu 4863578Sgblack@eecs.umich.edu return ctr; 4873578Sgblack@eecs.umich.edu } 4883578Sgblack@eecs.umich.edu case MISCREG_ACTLR: 4893578Sgblack@eecs.umich.edu warn("Not doing anything for miscreg ACTLR\n"); 4903578Sgblack@eecs.umich.edu break; 4913578Sgblack@eecs.umich.edu 4927741Sgblack@eecs.umich.edu case MISCREG_PMXEVTYPER_PMCCFILTR: 49310417Sandreas.hansson@arm.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 4942221SN/A case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 4952680Sktlim@umich.edu case MISCREG_PMCR ... MISCREG_PMOVSSET: 4968750Sgblack@eecs.umich.edu return pmu->readMiscReg(misc_reg); 4978750Sgblack@eecs.umich.edu 4988750Sgblack@eecs.umich.edu case MISCREG_CPSR_Q: 4992223SN/A panic("shouldn't be reading this register seperately\n"); 5002221SN/A case MISCREG_FPSCR_QC: 5017741Sgblack@eecs.umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 5027741Sgblack@eecs.umich.edu case MISCREG_FPSCR_EXC: 5034172Ssaidi@eecs.umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 5044172Ssaidi@eecs.umich.edu case MISCREG_FPSR: 5058829Sgblack@eecs.umich.edu { 5068829Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 5073578Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 5083578Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 5093578Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 5103578Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 5118829Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 5123746Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 5138829Sgblack@eecs.umich.edu fpscrMask.idc = ones; 5143578Sgblack@eecs.umich.edu fpscrMask.qc = ones; 5153578Sgblack@eecs.umich.edu fpscrMask.v = ones; 5163746Sgblack@eecs.umich.edu fpscrMask.c = ones; 5173578Sgblack@eecs.umich.edu fpscrMask.z = ones; 5183578Sgblack@eecs.umich.edu fpscrMask.n = ones; 5193578Sgblack@eecs.umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 5208829Sgblack@eecs.umich.edu } 5213595Sgblack@eecs.umich.edu case MISCREG_FPCR: 5223893Shsul@eecs.umich.edu { 5237741Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 5247741Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 5253578Sgblack@eecs.umich.edu fpscrMask.len = ones; 5263893Shsul@eecs.umich.edu fpscrMask.stride = ones; 5273825Ssaidi@eecs.umich.edu fpscrMask.rMode = ones; 5287741Sgblack@eecs.umich.edu fpscrMask.fz = ones; 5297741Sgblack@eecs.umich.edu fpscrMask.dn = ones; 5307741Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 5313893Shsul@eecs.umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 5327741Sgblack@eecs.umich.edu } 5333578Sgblack@eecs.umich.edu case MISCREG_NZCV: 5343585Sgblack@eecs.umich.edu { 5353893Shsul@eecs.umich.edu CPSR cpsr = 0; 5365570Snate@binkert.org cpsr.nz = tc->readCCReg(CCREG_NZ); 5373578Sgblack@eecs.umich.edu cpsr.c = tc->readCCReg(CCREG_C); 5383585Sgblack@eecs.umich.edu cpsr.v = tc->readCCReg(CCREG_V); 5393826Ssaidi@eecs.umich.edu return cpsr; 5403578Sgblack@eecs.umich.edu } 5417741Sgblack@eecs.umich.edu case MISCREG_DAIF: 5423578Sgblack@eecs.umich.edu { 5433578Sgblack@eecs.umich.edu CPSR cpsr = 0; 5447720Sgblack@eecs.umich.edu cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 5457720Sgblack@eecs.umich.edu return cpsr; 5467720Sgblack@eecs.umich.edu } 5477720Sgblack@eecs.umich.edu case MISCREG_SP_EL0: 5487720Sgblack@eecs.umich.edu { 5497720Sgblack@eecs.umich.edu return tc->readIntReg(INTREG_SP0); 5507720Sgblack@eecs.umich.edu } 5513420Sgblack@eecs.umich.edu case MISCREG_SP_EL1: 5522221SN/A { 5537741Sgblack@eecs.umich.edu return tc->readIntReg(INTREG_SP1); 55410417Sandreas.hansson@arm.com } 5553523Sgblack@eecs.umich.edu case MISCREG_SP_EL2: 5567741Sgblack@eecs.umich.edu { 5577741Sgblack@eecs.umich.edu return tc->readIntReg(INTREG_SP2); 5587741Sgblack@eecs.umich.edu } 5593595Sgblack@eecs.umich.edu case MISCREG_SPSEL: 5604172Ssaidi@eecs.umich.edu { 5614172Ssaidi@eecs.umich.edu return miscRegs[MISCREG_CPSR] & 0x1; 5624172Ssaidi@eecs.umich.edu } 5633595Sgblack@eecs.umich.edu case MISCREG_CURRENTEL: 5648829Sgblack@eecs.umich.edu { 5658829Sgblack@eecs.umich.edu return miscRegs[MISCREG_CPSR] & 0xc; 5668829Sgblack@eecs.umich.edu } 5678829Sgblack@eecs.umich.edu case MISCREG_L2CTLR: 5683595Sgblack@eecs.umich.edu { 5697741Sgblack@eecs.umich.edu // mostly unimplemented, just set NumCPUs field from sim and return 5708829Sgblack@eecs.umich.edu L2CTLR l2ctlr = 0; 5718829Sgblack@eecs.umich.edu // b00:1CPU to b11:4CPUs 5728829Sgblack@eecs.umich.edu l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 5738829Sgblack@eecs.umich.edu return l2ctlr; 5748829Sgblack@eecs.umich.edu } 5758829Sgblack@eecs.umich.edu case MISCREG_DBGDIDR: 5763595Sgblack@eecs.umich.edu /* For now just implement the version number. 5777741Sgblack@eecs.umich.edu * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 5784172Ssaidi@eecs.umich.edu */ 5793595Sgblack@eecs.umich.edu return 0x5 << 16; 5807741Sgblack@eecs.umich.edu case MISCREG_DBGDSCRint: 5817741Sgblack@eecs.umich.edu return 0; 5823746Sgblack@eecs.umich.edu case MISCREG_ISR: 5833746Sgblack@eecs.umich.edu return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 5843595Sgblack@eecs.umich.edu readMiscRegNoEffect(MISCREG_HCR), 5853595Sgblack@eecs.umich.edu readMiscRegNoEffect(MISCREG_CPSR), 5867720Sgblack@eecs.umich.edu readMiscRegNoEffect(MISCREG_SCR)); 5877720Sgblack@eecs.umich.edu case MISCREG_ISR_EL1: 5887720Sgblack@eecs.umich.edu return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 5897720Sgblack@eecs.umich.edu readMiscRegNoEffect(MISCREG_HCR_EL2), 5907720Sgblack@eecs.umich.edu readMiscRegNoEffect(MISCREG_CPSR), 5917720Sgblack@eecs.umich.edu readMiscRegNoEffect(MISCREG_SCR_EL3)); 5927720Sgblack@eecs.umich.edu case MISCREG_DCZID_EL0: 5937720Sgblack@eecs.umich.edu return 0x04; // DC ZVA clear 64-byte chunks 5943595Sgblack@eecs.umich.edu case MISCREG_HCPTR: 5957741Sgblack@eecs.umich.edu { 5967741Sgblack@eecs.umich.edu MiscReg val = readMiscRegNoEffect(misc_reg); 5973523Sgblack@eecs.umich.edu // The trap bit associated with CP14 is defined as RAZ 5983595Sgblack@eecs.umich.edu val &= ~(1 << 14); 5993595Sgblack@eecs.umich.edu // If a CP bit in NSACR is 0 then the corresponding bit in 6003595Sgblack@eecs.umich.edu // HCPTR is RAO/WI 6014172Ssaidi@eecs.umich.edu bool secure_lookup = haveSecurity && 6023595Sgblack@eecs.umich.edu inSecureState(readMiscRegNoEffect(MISCREG_SCR), 6033523Sgblack@eecs.umich.edu readMiscRegNoEffect(MISCREG_CPSR)); 6047741Sgblack@eecs.umich.edu if (!secure_lookup) { 6053523Sgblack@eecs.umich.edu MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 6063523Sgblack@eecs.umich.edu val |= (mask ^ 0x7FFF) & 0xBFFF; 6073523Sgblack@eecs.umich.edu } 6083523Sgblack@eecs.umich.edu // Set the bits for unimplemented coprocessors to RAO/WI 6093523Sgblack@eecs.umich.edu val |= 0x33FF; 6103523Sgblack@eecs.umich.edu return (val); 6113523Sgblack@eecs.umich.edu } 6123523Sgblack@eecs.umich.edu case MISCREG_HDFAR: // alias for secure DFAR 6133523Sgblack@eecs.umich.edu return readMiscRegNoEffect(MISCREG_DFAR_S); 6142221SN/A case MISCREG_HIFAR: // alias for secure IFAR 6152221SN/A return readMiscRegNoEffect(MISCREG_IFAR_S); 6167741Sgblack@eecs.umich.edu case MISCREG_HVBAR: // bottom bits reserved 61710417Sandreas.hansson@arm.com return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 61810417Sandreas.hansson@arm.com case MISCREG_SCTLR: 6194997Sgblack@eecs.umich.edu return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 6208767Sgblack@eecs.umich.edu case MISCREG_SCTLR_EL1: 6218767Sgblack@eecs.umich.edu return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 6228806Sgblack@eecs.umich.edu case MISCREG_SCTLR_EL2: 6238806Sgblack@eecs.umich.edu case MISCREG_SCTLR_EL3: 6248806Sgblack@eecs.umich.edu case MISCREG_HSCTLR: 6258806Sgblack@eecs.umich.edu return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 6268806Sgblack@eecs.umich.edu 6278806Sgblack@eecs.umich.edu case MISCREG_ID_PFR0: 6288806Sgblack@eecs.umich.edu // !ThumbEE | !Jazelle | Thumb | ARM 6298806Sgblack@eecs.umich.edu return 0x00000031; 6304997Sgblack@eecs.umich.edu case MISCREG_ID_PFR1: 63111850Sbrandon.potter@amd.com { // Timer | Virti | !M Profile | TrustZone | ARMv4 63211850Sbrandon.potter@amd.com bool haveTimer = (system->getGenericTimer() != NULL); 63311850Sbrandon.potter@amd.com return 0x00000001 63411850Sbrandon.potter@amd.com | (haveSecurity ? 0x00000010 : 0x0) 63511850Sbrandon.potter@amd.com | (haveVirtualization ? 0x00001000 : 0x0) 63611850Sbrandon.potter@amd.com | (haveTimer ? 0x00010000 : 0x0); 63711850Sbrandon.potter@amd.com } 63811850Sbrandon.potter@amd.com case MISCREG_ID_AA64PFR0_EL1: 63911850Sbrandon.potter@amd.com return 0x0000000000000002 // AArch{64,32} supported at EL0 64011850Sbrandon.potter@amd.com | 0x0000000000000020 // EL1 64111850Sbrandon.potter@amd.com | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 64211850Sbrandon.potter@amd.com | (haveSecurity ? 0x0000000000002000 : 0); // EL3 64311850Sbrandon.potter@amd.com case MISCREG_ID_AA64PFR1_EL1: 64411850Sbrandon.potter@amd.com return 0; // bits [63:0] RES0 (reserved for future use) 64511850Sbrandon.potter@amd.com 64611850Sbrandon.potter@amd.com // Generic Timer registers 64711850Sbrandon.potter@amd.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 64811850Sbrandon.potter@amd.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 64911850Sbrandon.potter@amd.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 65011850Sbrandon.potter@amd.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 65111850Sbrandon.potter@amd.com return getGenericTimer(tc).readMiscReg(misc_reg); 65211850Sbrandon.potter@amd.com 65311850Sbrandon.potter@amd.com default: 65411850Sbrandon.potter@amd.com break; 65511850Sbrandon.potter@amd.com 65611850Sbrandon.potter@amd.com } 65711850Sbrandon.potter@amd.com return readMiscRegNoEffect(misc_reg); 65811850Sbrandon.potter@amd.com} 65911850Sbrandon.potter@amd.com 66011850Sbrandon.potter@amd.comvoid 66111850Sbrandon.potter@amd.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 66211850Sbrandon.potter@amd.com{ 66311850Sbrandon.potter@amd.com assert(misc_reg < NumMiscRegs); 66411850Sbrandon.potter@amd.com 66511850Sbrandon.potter@amd.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 66611850Sbrandon.potter@amd.com const auto &map = getMiscIndices(misc_reg); 66711850Sbrandon.potter@amd.com int lower = map.first, upper = map.second; 6684997Sgblack@eecs.umich.edu 6694997Sgblack@eecs.umich.edu auto v = (val & ~reg.wi()) | reg.rao(); 6704997Sgblack@eecs.umich.edu if (upper > 0) { 6717741Sgblack@eecs.umich.edu miscRegs[lower] = bits(v, 31, 0); 67210417Sandreas.hansson@arm.com miscRegs[upper] = bits(v, 63, 32); 6734997Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 6748767Sgblack@eecs.umich.edu misc_reg, lower, upper, v); 6758767Sgblack@eecs.umich.edu } else { 6768806Sgblack@eecs.umich.edu miscRegs[lower] = v; 6778806Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 6788806Sgblack@eecs.umich.edu misc_reg, lower, v); 6798806Sgblack@eecs.umich.edu } 6808806Sgblack@eecs.umich.edu} 6818806Sgblack@eecs.umich.edu 6828806Sgblack@eecs.umich.eduvoid 6838806Sgblack@eecs.umich.eduISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 6848806Sgblack@eecs.umich.edu{ 6858806Sgblack@eecs.umich.edu 6868806Sgblack@eecs.umich.edu MiscReg newVal = val; 6878806Sgblack@eecs.umich.edu bool secure_lookup; 6888767Sgblack@eecs.umich.edu SCR scr; 68911850Sbrandon.potter@amd.com 69011850Sbrandon.potter@amd.com if (misc_reg == MISCREG_CPSR) { 69111850Sbrandon.potter@amd.com updateRegMap(val); 69211850Sbrandon.potter@amd.com 69311850Sbrandon.potter@amd.com 69411850Sbrandon.potter@amd.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 69511850Sbrandon.potter@amd.com int old_mode = old_cpsr.mode; 69611850Sbrandon.potter@amd.com CPSR cpsr = val; 69711850Sbrandon.potter@amd.com if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 69811850Sbrandon.potter@amd.com getITBPtr(tc)->invalidateMiscReg(); 69911850Sbrandon.potter@amd.com getDTBPtr(tc)->invalidateMiscReg(); 70011850Sbrandon.potter@amd.com } 70111850Sbrandon.potter@amd.com 70211850Sbrandon.potter@amd.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 70311850Sbrandon.potter@amd.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 70411850Sbrandon.potter@amd.com PCState pc = tc->pcState(); 70511850Sbrandon.potter@amd.com pc.nextThumb(cpsr.t); 70611850Sbrandon.potter@amd.com pc.nextJazelle(cpsr.j); 70711850Sbrandon.potter@amd.com pc.illegalExec(cpsr.il == 1); 70811850Sbrandon.potter@amd.com 70911850Sbrandon.potter@amd.com // Follow slightly different semantics if a CheckerCPU object 71011850Sbrandon.potter@amd.com // is connected 71111850Sbrandon.potter@amd.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 71211850Sbrandon.potter@amd.com if (checker) { 71311850Sbrandon.potter@amd.com tc->pcStateNoRecord(pc); 71411850Sbrandon.potter@amd.com } else { 71511850Sbrandon.potter@amd.com tc->pcState(pc); 71611850Sbrandon.potter@amd.com } 71711850Sbrandon.potter@amd.com } else { 71811850Sbrandon.potter@amd.com#ifndef NDEBUG 71911850Sbrandon.potter@amd.com if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 72011850Sbrandon.potter@amd.com if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 72111850Sbrandon.potter@amd.com warn("Unimplemented system register %s write with %#x.\n", 72211850Sbrandon.potter@amd.com miscRegName[misc_reg], val); 72311850Sbrandon.potter@amd.com else 72411850Sbrandon.potter@amd.com panic("Unimplemented system register %s write with %#x.\n", 72511850Sbrandon.potter@amd.com miscRegName[misc_reg], val); 72611850Sbrandon.potter@amd.com } 72711850Sbrandon.potter@amd.com#endif 72811850Sbrandon.potter@amd.com switch (unflattenMiscReg(misc_reg)) { 72911850Sbrandon.potter@amd.com case MISCREG_CPACR: 73011850Sbrandon.potter@amd.com { 73111850Sbrandon.potter@amd.com 73211850Sbrandon.potter@amd.com const uint32_t ones = (uint32_t)(-1); 73311850Sbrandon.potter@amd.com CPACR cpacrMask = 0; 73411850Sbrandon.potter@amd.com // Only cp10, cp11, and ase are implemented, nothing else should 73511850Sbrandon.potter@amd.com // be writable 73611850Sbrandon.potter@amd.com cpacrMask.cp10 = ones; 73711850Sbrandon.potter@amd.com cpacrMask.cp11 = ones; 73811850Sbrandon.potter@amd.com cpacrMask.asedis = ones; 73911850Sbrandon.potter@amd.com 74011850Sbrandon.potter@amd.com // Security Extensions may limit the writability of CPACR 74111850Sbrandon.potter@amd.com if (haveSecurity) { 74211850Sbrandon.potter@amd.com scr = readMiscRegNoEffect(MISCREG_SCR); 74311850Sbrandon.potter@amd.com CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 74411850Sbrandon.potter@amd.com if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 74511850Sbrandon.potter@amd.com NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 74611850Sbrandon.potter@amd.com // NB: Skipping the full loop, here 74711850Sbrandon.potter@amd.com if (!nsacr.cp10) cpacrMask.cp10 = 0; 74811850Sbrandon.potter@amd.com if (!nsacr.cp11) cpacrMask.cp11 = 0; 74911850Sbrandon.potter@amd.com } 75011850Sbrandon.potter@amd.com } 75111850Sbrandon.potter@amd.com 75211850Sbrandon.potter@amd.com MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 75311850Sbrandon.potter@amd.com newVal &= cpacrMask; 75411850Sbrandon.potter@amd.com newVal |= old_val & ~cpacrMask; 75511850Sbrandon.potter@amd.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 7564997Sgblack@eecs.umich.edu miscRegName[misc_reg], newVal); 7574997Sgblack@eecs.umich.edu } 7584997Sgblack@eecs.umich.edu break; 7597741Sgblack@eecs.umich.edu case MISCREG_CPTR_EL2: 76010417Sandreas.hansson@arm.com { 7613415Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 7628778Sgblack@eecs.umich.edu CPTR cptrMask = 0; 7638778Sgblack@eecs.umich.edu cptrMask.tcpac = ones; 7648806Sgblack@eecs.umich.edu cptrMask.tta = ones; 7658806Sgblack@eecs.umich.edu cptrMask.tfp = ones; 7663415Sgblack@eecs.umich.edu newVal &= cptrMask; 7678806Sgblack@eecs.umich.edu cptrMask = 0; 7683415Sgblack@eecs.umich.edu cptrMask.res1_13_12_el2 = ones; 7698806Sgblack@eecs.umich.edu cptrMask.res1_9_0_el2 = ones; 7703415Sgblack@eecs.umich.edu newVal |= cptrMask; 77111851Sbrandon.potter@amd.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 77211851Sbrandon.potter@amd.com miscRegName[misc_reg], newVal); 7738806Sgblack@eecs.umich.edu } 7748806Sgblack@eecs.umich.edu break; 77511851Sbrandon.potter@amd.com case MISCREG_CPTR_EL3: 7763415Sgblack@eecs.umich.edu { 7773415Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 7787741Sgblack@eecs.umich.edu CPTR cptrMask = 0; 77910417Sandreas.hansson@arm.com cptrMask.tcpac = ones; 7803415Sgblack@eecs.umich.edu cptrMask.tta = ones; 7818778Sgblack@eecs.umich.edu cptrMask.tfp = ones; 7828778Sgblack@eecs.umich.edu newVal &= cptrMask; 7838806Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 7848806Sgblack@eecs.umich.edu miscRegName[misc_reg], newVal); 7853415Sgblack@eecs.umich.edu } 7868806Sgblack@eecs.umich.edu break; 7873415Sgblack@eecs.umich.edu case MISCREG_CSSELR: 7888806Sgblack@eecs.umich.edu warn_once("The csselr register isn't implemented.\n"); 7893415Sgblack@eecs.umich.edu return; 79011851Sbrandon.potter@amd.com 79111851Sbrandon.potter@amd.com case MISCREG_DC_ZVA_Xt: 7928806Sgblack@eecs.umich.edu warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 7938806Sgblack@eecs.umich.edu return; 79411851Sbrandon.potter@amd.com 7953415Sgblack@eecs.umich.edu case MISCREG_FPSCR: 7963415Sgblack@eecs.umich.edu { 7977741Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 79810417Sandreas.hansson@arm.com FPSCR fpscrMask = 0; 7994111Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 8008778Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 8018778Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 8028806Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 8038806Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 8044111Sgblack@eecs.umich.edu fpscrMask.idc = ones; 8058806Sgblack@eecs.umich.edu fpscrMask.ioe = ones; 8068806Sgblack@eecs.umich.edu fpscrMask.dze = ones; 8078806Sgblack@eecs.umich.edu fpscrMask.ofe = ones; 8084111Sgblack@eecs.umich.edu fpscrMask.ufe = ones; 8098806Sgblack@eecs.umich.edu fpscrMask.ixe = ones; 8104111Sgblack@eecs.umich.edu fpscrMask.ide = ones; 81111851Sbrandon.potter@amd.com fpscrMask.len = ones; 81211851Sbrandon.potter@amd.com fpscrMask.stride = ones; 8134111Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 81411877Sbrandon.potter@amd.com fpscrMask.fz = ones; 81511877Sbrandon.potter@amd.com fpscrMask.dn = ones; 8168806Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 8178806Sgblack@eecs.umich.edu fpscrMask.qc = ones; 8188806Sgblack@eecs.umich.edu fpscrMask.v = ones; 8198806Sgblack@eecs.umich.edu fpscrMask.c = ones; 8208806Sgblack@eecs.umich.edu fpscrMask.z = ones; 8218806Sgblack@eecs.umich.edu fpscrMask.n = ones; 8224111Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 8234111Sgblack@eecs.umich.edu (readMiscRegNoEffect(MISCREG_FPSCR) & 8242223SN/A ~(uint32_t)fpscrMask); 8252221SN/A tc->getDecoderPtr()->setContext(newVal); 826 } 827 break; 828 case MISCREG_FPSR: 829 { 830 const uint32_t ones = (uint32_t)(-1); 831 FPSCR fpscrMask = 0; 832 fpscrMask.ioc = ones; 833 fpscrMask.dzc = ones; 834 fpscrMask.ofc = ones; 835 fpscrMask.ufc = ones; 836 fpscrMask.ixc = ones; 837 fpscrMask.idc = ones; 838 fpscrMask.qc = ones; 839 fpscrMask.v = ones; 840 fpscrMask.c = ones; 841 fpscrMask.z = ones; 842 fpscrMask.n = ones; 843 newVal = (newVal & (uint32_t)fpscrMask) | 844 (readMiscRegNoEffect(MISCREG_FPSCR) & 845 ~(uint32_t)fpscrMask); 846 misc_reg = MISCREG_FPSCR; 847 } 848 break; 849 case MISCREG_FPCR: 850 { 851 const uint32_t ones = (uint32_t)(-1); 852 FPSCR fpscrMask = 0; 853 fpscrMask.len = ones; 854 fpscrMask.stride = ones; 855 fpscrMask.rMode = ones; 856 fpscrMask.fz = ones; 857 fpscrMask.dn = ones; 858 fpscrMask.ahp = ones; 859 newVal = (newVal & (uint32_t)fpscrMask) | 860 (readMiscRegNoEffect(MISCREG_FPSCR) & 861 ~(uint32_t)fpscrMask); 862 misc_reg = MISCREG_FPSCR; 863 } 864 break; 865 case MISCREG_CPSR_Q: 866 { 867 assert(!(newVal & ~CpsrMaskQ)); 868 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 869 misc_reg = MISCREG_CPSR; 870 } 871 break; 872 case MISCREG_FPSCR_QC: 873 { 874 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 875 (newVal & FpscrQcMask); 876 misc_reg = MISCREG_FPSCR; 877 } 878 break; 879 case MISCREG_FPSCR_EXC: 880 { 881 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 882 (newVal & FpscrExcMask); 883 misc_reg = MISCREG_FPSCR; 884 } 885 break; 886 case MISCREG_FPEXC: 887 { 888 // vfpv3 architecture, section B.6.1 of DDI04068 889 // bit 29 - valid only if fpexc[31] is 0 890 const uint32_t fpexcMask = 0x60000000; 891 newVal = (newVal & fpexcMask) | 892 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 893 } 894 break; 895 case MISCREG_HCR: 896 { 897 if (!haveVirtualization) 898 return; 899 } 900 break; 901 case MISCREG_IFSR: 902 { 903 // ARM ARM (ARM DDI 0406C.b) B4.1.96 904 const uint32_t ifsrMask = 905 mask(31, 13) | mask(11, 11) | mask(8, 6); 906 newVal = newVal & ~ifsrMask; 907 } 908 break; 909 case MISCREG_DFSR: 910 { 911 // ARM ARM (ARM DDI 0406C.b) B4.1.52 912 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 913 newVal = newVal & ~dfsrMask; 914 } 915 break; 916 case MISCREG_AMAIR0: 917 case MISCREG_AMAIR1: 918 { 919 // ARM ARM (ARM DDI 0406C.b) B4.1.5 920 // Valid only with LPAE 921 if (!haveLPAE) 922 return; 923 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 924 } 925 break; 926 case MISCREG_SCR: 927 getITBPtr(tc)->invalidateMiscReg(); 928 getDTBPtr(tc)->invalidateMiscReg(); 929 break; 930 case MISCREG_SCTLR: 931 { 932 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 933 scr = readMiscRegNoEffect(MISCREG_SCR); 934 935 MiscRegIndex sctlr_idx; 936 if (haveSecurity && !highestELIs64 && !scr.ns) { 937 sctlr_idx = MISCREG_SCTLR_S; 938 } else { 939 sctlr_idx = MISCREG_SCTLR_NS; 940 } 941 942 SCTLR sctlr = miscRegs[sctlr_idx]; 943 SCTLR new_sctlr = newVal; 944 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 945 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 946 getITBPtr(tc)->invalidateMiscReg(); 947 getDTBPtr(tc)->invalidateMiscReg(); 948 } 949 case MISCREG_MIDR: 950 case MISCREG_ID_PFR0: 951 case MISCREG_ID_PFR1: 952 case MISCREG_ID_DFR0: 953 case MISCREG_ID_MMFR0: 954 case MISCREG_ID_MMFR1: 955 case MISCREG_ID_MMFR2: 956 case MISCREG_ID_MMFR3: 957 case MISCREG_ID_ISAR0: 958 case MISCREG_ID_ISAR1: 959 case MISCREG_ID_ISAR2: 960 case MISCREG_ID_ISAR3: 961 case MISCREG_ID_ISAR4: 962 case MISCREG_ID_ISAR5: 963 964 case MISCREG_MPIDR: 965 case MISCREG_FPSID: 966 case MISCREG_TLBTR: 967 case MISCREG_MVFR0: 968 case MISCREG_MVFR1: 969 970 case MISCREG_ID_AA64AFR0_EL1: 971 case MISCREG_ID_AA64AFR1_EL1: 972 case MISCREG_ID_AA64DFR0_EL1: 973 case MISCREG_ID_AA64DFR1_EL1: 974 case MISCREG_ID_AA64ISAR0_EL1: 975 case MISCREG_ID_AA64ISAR1_EL1: 976 case MISCREG_ID_AA64MMFR0_EL1: 977 case MISCREG_ID_AA64MMFR1_EL1: 978 case MISCREG_ID_AA64PFR0_EL1: 979 case MISCREG_ID_AA64PFR1_EL1: 980 // ID registers are constants. 981 return; 982 983 // TLB Invalidate All 984 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 985 { 986 assert32(tc); 987 scr = readMiscReg(MISCREG_SCR, tc); 988 989 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 990 tlbiOp(tc); 991 return; 992 } 993 // TLB Invalidate All, Inner Shareable 994 case MISCREG_TLBIALLIS: 995 { 996 assert32(tc); 997 scr = readMiscReg(MISCREG_SCR, tc); 998 999 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1000 tlbiOp.broadcast(tc); 1001 return; 1002 } 1003 // Instruction TLB Invalidate All 1004 case MISCREG_ITLBIALL: 1005 { 1006 assert32(tc); 1007 scr = readMiscReg(MISCREG_SCR, tc); 1008 1009 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1010 tlbiOp(tc); 1011 return; 1012 } 1013 // Data TLB Invalidate All 1014 case MISCREG_DTLBIALL: 1015 { 1016 assert32(tc); 1017 scr = readMiscReg(MISCREG_SCR, tc); 1018 1019 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1020 tlbiOp(tc); 1021 return; 1022 } 1023 // TLB Invalidate by VA 1024 // mcr tlbimval(is) is invalidating all matching entries 1025 // regardless of the level of lookup, since in gem5 we cache 1026 // in the tlb the last level of lookup only. 1027 case MISCREG_TLBIMVA: 1028 case MISCREG_TLBIMVAL: 1029 { 1030 assert32(tc); 1031 scr = readMiscReg(MISCREG_SCR, tc); 1032 1033 TLBIMVA tlbiOp(EL1, 1034 haveSecurity && !scr.ns, 1035 mbits(newVal, 31, 12), 1036 bits(newVal, 7,0)); 1037 1038 tlbiOp(tc); 1039 return; 1040 } 1041 // TLB Invalidate by VA, Inner Shareable 1042 case MISCREG_TLBIMVAIS: 1043 case MISCREG_TLBIMVALIS: 1044 { 1045 assert32(tc); 1046 scr = readMiscReg(MISCREG_SCR, tc); 1047 1048 TLBIMVA tlbiOp(EL1, 1049 haveSecurity && !scr.ns, 1050 mbits(newVal, 31, 12), 1051 bits(newVal, 7,0)); 1052 1053 tlbiOp.broadcast(tc); 1054 return; 1055 } 1056 // TLB Invalidate by ASID match 1057 case MISCREG_TLBIASID: 1058 { 1059 assert32(tc); 1060 scr = readMiscReg(MISCREG_SCR, tc); 1061 1062 TLBIASID tlbiOp(EL1, 1063 haveSecurity && !scr.ns, 1064 bits(newVal, 7,0)); 1065 1066 tlbiOp(tc); 1067 return; 1068 } 1069 // TLB Invalidate by ASID match, Inner Shareable 1070 case MISCREG_TLBIASIDIS: 1071 { 1072 assert32(tc); 1073 scr = readMiscReg(MISCREG_SCR, tc); 1074 1075 TLBIASID tlbiOp(EL1, 1076 haveSecurity && !scr.ns, 1077 bits(newVal, 7,0)); 1078 1079 tlbiOp.broadcast(tc); 1080 return; 1081 } 1082 // mcr tlbimvaal(is) is invalidating all matching entries 1083 // regardless of the level of lookup, since in gem5 we cache 1084 // in the tlb the last level of lookup only. 1085 // TLB Invalidate by VA, All ASID 1086 case MISCREG_TLBIMVAA: 1087 case MISCREG_TLBIMVAAL: 1088 { 1089 assert32(tc); 1090 scr = readMiscReg(MISCREG_SCR, tc); 1091 1092 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1093 mbits(newVal, 31,12), false); 1094 1095 tlbiOp(tc); 1096 return; 1097 } 1098 // TLB Invalidate by VA, All ASID, Inner Shareable 1099 case MISCREG_TLBIMVAAIS: 1100 case MISCREG_TLBIMVAALIS: 1101 { 1102 assert32(tc); 1103 scr = readMiscReg(MISCREG_SCR, tc); 1104 1105 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1106 mbits(newVal, 31,12), false); 1107 1108 tlbiOp.broadcast(tc); 1109 return; 1110 } 1111 // mcr tlbimvalh(is) is invalidating all matching entries 1112 // regardless of the level of lookup, since in gem5 we cache 1113 // in the tlb the last level of lookup only. 1114 // TLB Invalidate by VA, Hyp mode 1115 case MISCREG_TLBIMVAH: 1116 case MISCREG_TLBIMVALH: 1117 { 1118 assert32(tc); 1119 scr = readMiscReg(MISCREG_SCR, tc); 1120 1121 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1122 mbits(newVal, 31,12), true); 1123 1124 tlbiOp(tc); 1125 return; 1126 } 1127 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1128 case MISCREG_TLBIMVAHIS: 1129 case MISCREG_TLBIMVALHIS: 1130 { 1131 assert32(tc); 1132 scr = readMiscReg(MISCREG_SCR, tc); 1133 1134 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1135 mbits(newVal, 31,12), true); 1136 1137 tlbiOp.broadcast(tc); 1138 return; 1139 } 1140 // mcr tlbiipas2l(is) is invalidating all matching entries 1141 // regardless of the level of lookup, since in gem5 we cache 1142 // in the tlb the last level of lookup only. 1143 // TLB Invalidate by Intermediate Physical Address, Stage 2 1144 case MISCREG_TLBIIPAS2: 1145 case MISCREG_TLBIIPAS2L: 1146 { 1147 assert32(tc); 1148 scr = readMiscReg(MISCREG_SCR, tc); 1149 1150 TLBIIPA tlbiOp(EL1, 1151 haveSecurity && !scr.ns, 1152 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1153 1154 tlbiOp(tc); 1155 return; 1156 } 1157 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1158 // Inner Shareable 1159 case MISCREG_TLBIIPAS2IS: 1160 case MISCREG_TLBIIPAS2LIS: 1161 { 1162 assert32(tc); 1163 scr = readMiscReg(MISCREG_SCR, tc); 1164 1165 TLBIIPA tlbiOp(EL1, 1166 haveSecurity && !scr.ns, 1167 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1168 1169 tlbiOp.broadcast(tc); 1170 return; 1171 } 1172 // Instruction TLB Invalidate by VA 1173 case MISCREG_ITLBIMVA: 1174 { 1175 assert32(tc); 1176 scr = readMiscReg(MISCREG_SCR, tc); 1177 1178 ITLBIMVA tlbiOp(EL1, 1179 haveSecurity && !scr.ns, 1180 mbits(newVal, 31, 12), 1181 bits(newVal, 7,0)); 1182 1183 tlbiOp(tc); 1184 return; 1185 } 1186 // Data TLB Invalidate by VA 1187 case MISCREG_DTLBIMVA: 1188 { 1189 assert32(tc); 1190 scr = readMiscReg(MISCREG_SCR, tc); 1191 1192 DTLBIMVA tlbiOp(EL1, 1193 haveSecurity && !scr.ns, 1194 mbits(newVal, 31, 12), 1195 bits(newVal, 7,0)); 1196 1197 tlbiOp(tc); 1198 return; 1199 } 1200 // Instruction TLB Invalidate by ASID match 1201 case MISCREG_ITLBIASID: 1202 { 1203 assert32(tc); 1204 scr = readMiscReg(MISCREG_SCR, tc); 1205 1206 ITLBIASID tlbiOp(EL1, 1207 haveSecurity && !scr.ns, 1208 bits(newVal, 7,0)); 1209 1210 tlbiOp(tc); 1211 return; 1212 } 1213 // Data TLB Invalidate by ASID match 1214 case MISCREG_DTLBIASID: 1215 { 1216 assert32(tc); 1217 scr = readMiscReg(MISCREG_SCR, tc); 1218 1219 DTLBIASID tlbiOp(EL1, 1220 haveSecurity && !scr.ns, 1221 bits(newVal, 7,0)); 1222 1223 tlbiOp(tc); 1224 return; 1225 } 1226 // TLB Invalidate All, Non-Secure Non-Hyp 1227 case MISCREG_TLBIALLNSNH: 1228 { 1229 assert32(tc); 1230 1231 TLBIALLN tlbiOp(EL1, false); 1232 tlbiOp(tc); 1233 return; 1234 } 1235 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1236 case MISCREG_TLBIALLNSNHIS: 1237 { 1238 assert32(tc); 1239 1240 TLBIALLN tlbiOp(EL1, false); 1241 tlbiOp.broadcast(tc); 1242 return; 1243 } 1244 // TLB Invalidate All, Hyp mode 1245 case MISCREG_TLBIALLH: 1246 { 1247 assert32(tc); 1248 1249 TLBIALLN tlbiOp(EL1, true); 1250 tlbiOp(tc); 1251 return; 1252 } 1253 // TLB Invalidate All, Hyp mode, Inner Shareable 1254 case MISCREG_TLBIALLHIS: 1255 { 1256 assert32(tc); 1257 1258 TLBIALLN tlbiOp(EL1, true); 1259 tlbiOp.broadcast(tc); 1260 return; 1261 } 1262 // AArch64 TLB Invalidate All, EL3 1263 case MISCREG_TLBI_ALLE3: 1264 { 1265 assert64(tc); 1266 1267 TLBIALL tlbiOp(EL3, true); 1268 tlbiOp(tc); 1269 return; 1270 } 1271 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1272 case MISCREG_TLBI_ALLE3IS: 1273 { 1274 assert64(tc); 1275 1276 TLBIALL tlbiOp(EL3, true); 1277 tlbiOp.broadcast(tc); 1278 return; 1279 } 1280 // @todo: uncomment this to enable Virtualization 1281 // case MISCREG_TLBI_ALLE2IS: 1282 // case MISCREG_TLBI_ALLE2: 1283 // AArch64 TLB Invalidate All, EL1 1284 case MISCREG_TLBI_ALLE1: 1285 case MISCREG_TLBI_VMALLE1: 1286 case MISCREG_TLBI_VMALLS12E1: 1287 // @todo: handle VMID and stage 2 to enable Virtualization 1288 { 1289 assert64(tc); 1290 scr = readMiscReg(MISCREG_SCR, tc); 1291 1292 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1293 tlbiOp(tc); 1294 return; 1295 } 1296 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1297 case MISCREG_TLBI_ALLE1IS: 1298 case MISCREG_TLBI_VMALLE1IS: 1299 case MISCREG_TLBI_VMALLS12E1IS: 1300 // @todo: handle VMID and stage 2 to enable Virtualization 1301 { 1302 assert64(tc); 1303 scr = readMiscReg(MISCREG_SCR, tc); 1304 1305 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1306 tlbiOp.broadcast(tc); 1307 return; 1308 } 1309 // VAEx(IS) and VALEx(IS) are the same because TLBs 1310 // only store entries 1311 // from the last level of translation table walks 1312 // @todo: handle VMID to enable Virtualization 1313 // AArch64 TLB Invalidate by VA, EL3 1314 case MISCREG_TLBI_VAE3_Xt: 1315 case MISCREG_TLBI_VALE3_Xt: 1316 { 1317 assert64(tc); 1318 1319 TLBIMVA tlbiOp(EL3, true, 1320 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1321 0xbeef); 1322 tlbiOp(tc); 1323 return; 1324 } 1325 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1326 case MISCREG_TLBI_VAE3IS_Xt: 1327 case MISCREG_TLBI_VALE3IS_Xt: 1328 { 1329 assert64(tc); 1330 1331 TLBIMVA tlbiOp(EL3, true, 1332 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1333 0xbeef); 1334 1335 tlbiOp.broadcast(tc); 1336 return; 1337 } 1338 // AArch64 TLB Invalidate by VA, EL2 1339 case MISCREG_TLBI_VAE2_Xt: 1340 case MISCREG_TLBI_VALE2_Xt: 1341 { 1342 assert64(tc); 1343 scr = readMiscReg(MISCREG_SCR, tc); 1344 1345 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1346 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1347 0xbeef); 1348 tlbiOp(tc); 1349 return; 1350 } 1351 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1352 case MISCREG_TLBI_VAE2IS_Xt: 1353 case MISCREG_TLBI_VALE2IS_Xt: 1354 { 1355 assert64(tc); 1356 scr = readMiscReg(MISCREG_SCR, tc); 1357 1358 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1359 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1360 0xbeef); 1361 1362 tlbiOp.broadcast(tc); 1363 return; 1364 } 1365 // AArch64 TLB Invalidate by VA, EL1 1366 case MISCREG_TLBI_VAE1_Xt: 1367 case MISCREG_TLBI_VALE1_Xt: 1368 { 1369 assert64(tc); 1370 scr = readMiscReg(MISCREG_SCR, tc); 1371 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1372 bits(newVal, 55, 48); 1373 1374 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1375 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1376 asid); 1377 1378 tlbiOp(tc); 1379 return; 1380 } 1381 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1382 case MISCREG_TLBI_VAE1IS_Xt: 1383 case MISCREG_TLBI_VALE1IS_Xt: 1384 { 1385 assert64(tc); 1386 scr = readMiscReg(MISCREG_SCR, tc); 1387 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1388 bits(newVal, 55, 48); 1389 1390 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1391 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1392 asid); 1393 1394 tlbiOp.broadcast(tc); 1395 return; 1396 } 1397 // AArch64 TLB Invalidate by ASID, EL1 1398 // @todo: handle VMID to enable Virtualization 1399 case MISCREG_TLBI_ASIDE1_Xt: 1400 { 1401 assert64(tc); 1402 scr = readMiscReg(MISCREG_SCR, tc); 1403 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1404 bits(newVal, 55, 48); 1405 1406 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1407 tlbiOp(tc); 1408 return; 1409 } 1410 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1411 case MISCREG_TLBI_ASIDE1IS_Xt: 1412 { 1413 assert64(tc); 1414 scr = readMiscReg(MISCREG_SCR, tc); 1415 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1416 bits(newVal, 55, 48); 1417 1418 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1419 tlbiOp.broadcast(tc); 1420 return; 1421 } 1422 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1423 // entries from the last level of translation table walks 1424 // AArch64 TLB Invalidate by VA, All ASID, EL1 1425 case MISCREG_TLBI_VAAE1_Xt: 1426 case MISCREG_TLBI_VAALE1_Xt: 1427 { 1428 assert64(tc); 1429 scr = readMiscReg(MISCREG_SCR, tc); 1430 1431 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1432 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1433 1434 tlbiOp(tc); 1435 return; 1436 } 1437 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1438 case MISCREG_TLBI_VAAE1IS_Xt: 1439 case MISCREG_TLBI_VAALE1IS_Xt: 1440 { 1441 assert64(tc); 1442 scr = readMiscReg(MISCREG_SCR, tc); 1443 1444 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1445 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1446 1447 tlbiOp.broadcast(tc); 1448 return; 1449 } 1450 // AArch64 TLB Invalidate by Intermediate Physical Address, 1451 // Stage 2, EL1 1452 case MISCREG_TLBI_IPAS2E1_Xt: 1453 case MISCREG_TLBI_IPAS2LE1_Xt: 1454 { 1455 assert64(tc); 1456 scr = readMiscReg(MISCREG_SCR, tc); 1457 1458 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1459 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1460 1461 tlbiOp(tc); 1462 return; 1463 } 1464 // AArch64 TLB Invalidate by Intermediate Physical Address, 1465 // Stage 2, EL1, Inner Shareable 1466 case MISCREG_TLBI_IPAS2E1IS_Xt: 1467 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1468 { 1469 assert64(tc); 1470 scr = readMiscReg(MISCREG_SCR, tc); 1471 1472 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1473 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1474 1475 tlbiOp.broadcast(tc); 1476 return; 1477 } 1478 case MISCREG_ACTLR: 1479 warn("Not doing anything for write of miscreg ACTLR\n"); 1480 break; 1481 1482 case MISCREG_PMXEVTYPER_PMCCFILTR: 1483 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1484 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1485 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1486 pmu->setMiscReg(misc_reg, newVal); 1487 break; 1488 1489 1490 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1491 { 1492 HSTR hstrMask = 0; 1493 hstrMask.tjdbx = 1; 1494 newVal &= ~((uint32_t) hstrMask); 1495 break; 1496 } 1497 case MISCREG_HCPTR: 1498 { 1499 // If a CP bit in NSACR is 0 then the corresponding bit in 1500 // HCPTR is RAO/WI. Same applies to NSASEDIS 1501 secure_lookup = haveSecurity && 1502 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1503 readMiscRegNoEffect(MISCREG_CPSR)); 1504 if (!secure_lookup) { 1505 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1506 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1507 newVal = (newVal & ~mask) | (oldValue & mask); 1508 } 1509 break; 1510 } 1511 case MISCREG_HDFAR: // alias for secure DFAR 1512 misc_reg = MISCREG_DFAR_S; 1513 break; 1514 case MISCREG_HIFAR: // alias for secure IFAR 1515 misc_reg = MISCREG_IFAR_S; 1516 break; 1517 case MISCREG_ATS1CPR: 1518 case MISCREG_ATS1CPW: 1519 case MISCREG_ATS1CUR: 1520 case MISCREG_ATS1CUW: 1521 case MISCREG_ATS12NSOPR: 1522 case MISCREG_ATS12NSOPW: 1523 case MISCREG_ATS12NSOUR: 1524 case MISCREG_ATS12NSOUW: 1525 case MISCREG_ATS1HR: 1526 case MISCREG_ATS1HW: 1527 { 1528 Request::Flags flags = 0; 1529 BaseTLB::Mode mode = BaseTLB::Read; 1530 TLB::ArmTranslationType tranType = TLB::NormalTran; 1531 Fault fault; 1532 switch(misc_reg) { 1533 case MISCREG_ATS1CPR: 1534 flags = TLB::MustBeOne; 1535 tranType = TLB::S1CTran; 1536 mode = BaseTLB::Read; 1537 break; 1538 case MISCREG_ATS1CPW: 1539 flags = TLB::MustBeOne; 1540 tranType = TLB::S1CTran; 1541 mode = BaseTLB::Write; 1542 break; 1543 case MISCREG_ATS1CUR: 1544 flags = TLB::MustBeOne | TLB::UserMode; 1545 tranType = TLB::S1CTran; 1546 mode = BaseTLB::Read; 1547 break; 1548 case MISCREG_ATS1CUW: 1549 flags = TLB::MustBeOne | TLB::UserMode; 1550 tranType = TLB::S1CTran; 1551 mode = BaseTLB::Write; 1552 break; 1553 case MISCREG_ATS12NSOPR: 1554 if (!haveSecurity) 1555 panic("Security Extensions required for ATS12NSOPR"); 1556 flags = TLB::MustBeOne; 1557 tranType = TLB::S1S2NsTran; 1558 mode = BaseTLB::Read; 1559 break; 1560 case MISCREG_ATS12NSOPW: 1561 if (!haveSecurity) 1562 panic("Security Extensions required for ATS12NSOPW"); 1563 flags = TLB::MustBeOne; 1564 tranType = TLB::S1S2NsTran; 1565 mode = BaseTLB::Write; 1566 break; 1567 case MISCREG_ATS12NSOUR: 1568 if (!haveSecurity) 1569 panic("Security Extensions required for ATS12NSOUR"); 1570 flags = TLB::MustBeOne | TLB::UserMode; 1571 tranType = TLB::S1S2NsTran; 1572 mode = BaseTLB::Read; 1573 break; 1574 case MISCREG_ATS12NSOUW: 1575 if (!haveSecurity) 1576 panic("Security Extensions required for ATS12NSOUW"); 1577 flags = TLB::MustBeOne | TLB::UserMode; 1578 tranType = TLB::S1S2NsTran; 1579 mode = BaseTLB::Write; 1580 break; 1581 case MISCREG_ATS1HR: // only really useful from secure mode. 1582 flags = TLB::MustBeOne; 1583 tranType = TLB::HypMode; 1584 mode = BaseTLB::Read; 1585 break; 1586 case MISCREG_ATS1HW: 1587 flags = TLB::MustBeOne; 1588 tranType = TLB::HypMode; 1589 mode = BaseTLB::Write; 1590 break; 1591 } 1592 // If we're in timing mode then doing the translation in 1593 // functional mode then we're slightly distorting performance 1594 // results obtained from simulations. The translation should be 1595 // done in the same mode the core is running in. NOTE: This 1596 // can't be an atomic translation because that causes problems 1597 // with unexpected atomic snoop requests. 1598 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1599 1600 auto req = std::make_shared<Request>( 1601 0, val, 0, flags, Request::funcMasterId, 1602 tc->pcState().pc(), tc->contextId()); 1603 1604 fault = getDTBPtr(tc)->translateFunctional( 1605 req, tc, mode, tranType); 1606 1607 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1608 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1609 1610 MiscReg newVal; 1611 if (fault == NoFault) { 1612 Addr paddr = req->getPaddr(); 1613 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1614 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1615 newVal = (paddr & mask(39, 12)) | 1616 (getDTBPtr(tc)->getAttr()); 1617 } else { 1618 newVal = (paddr & 0xfffff000) | 1619 (getDTBPtr(tc)->getAttr()); 1620 } 1621 DPRINTF(MiscRegs, 1622 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1623 val, newVal); 1624 } else { 1625 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1626 armFault->update(tc); 1627 // Set fault bit and FSR 1628 FSR fsr = armFault->getFsr(tc); 1629 1630 newVal = ((fsr >> 9) & 1) << 11; 1631 if (newVal) { 1632 // LPAE - rearange fault status 1633 newVal |= ((fsr >> 0) & 0x3f) << 1; 1634 } else { 1635 // VMSA - rearange fault status 1636 newVal |= ((fsr >> 0) & 0xf) << 1; 1637 newVal |= ((fsr >> 10) & 0x1) << 5; 1638 newVal |= ((fsr >> 12) & 0x1) << 6; 1639 } 1640 newVal |= 0x1; // F bit 1641 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1642 newVal |= armFault->isStage2() ? 0x200 : 0; 1643 DPRINTF(MiscRegs, 1644 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1645 val, fsr, newVal); 1646 } 1647 setMiscRegNoEffect(MISCREG_PAR, newVal); 1648 return; 1649 } 1650 case MISCREG_TTBCR: 1651 { 1652 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1653 const uint32_t ones = (uint32_t)(-1); 1654 TTBCR ttbcrMask = 0; 1655 TTBCR ttbcrNew = newVal; 1656 1657 // ARM DDI 0406C.b, ARMv7-32 1658 ttbcrMask.n = ones; // T0SZ 1659 if (haveSecurity) { 1660 ttbcrMask.pd0 = ones; 1661 ttbcrMask.pd1 = ones; 1662 } 1663 ttbcrMask.epd0 = ones; 1664 ttbcrMask.irgn0 = ones; 1665 ttbcrMask.orgn0 = ones; 1666 ttbcrMask.sh0 = ones; 1667 ttbcrMask.ps = ones; // T1SZ 1668 ttbcrMask.a1 = ones; 1669 ttbcrMask.epd1 = ones; 1670 ttbcrMask.irgn1 = ones; 1671 ttbcrMask.orgn1 = ones; 1672 ttbcrMask.sh1 = ones; 1673 if (haveLPAE) 1674 ttbcrMask.eae = ones; 1675 1676 if (haveLPAE && ttbcrNew.eae) { 1677 newVal = newVal & ttbcrMask; 1678 } else { 1679 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1680 } 1681 // Invalidate TLB MiscReg 1682 getITBPtr(tc)->invalidateMiscReg(); 1683 getDTBPtr(tc)->invalidateMiscReg(); 1684 break; 1685 } 1686 case MISCREG_TTBR0: 1687 case MISCREG_TTBR1: 1688 { 1689 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1690 if (haveLPAE) { 1691 if (ttbcr.eae) { 1692 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1693 // ARMv8 AArch32 bit 63-56 only 1694 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1695 newVal = (newVal & (~ttbrMask)); 1696 } 1697 } 1698 // Invalidate TLB MiscReg 1699 getITBPtr(tc)->invalidateMiscReg(); 1700 getDTBPtr(tc)->invalidateMiscReg(); 1701 break; 1702 } 1703 case MISCREG_SCTLR_EL1: 1704 case MISCREG_CONTEXTIDR: 1705 case MISCREG_PRRR: 1706 case MISCREG_NMRR: 1707 case MISCREG_MAIR0: 1708 case MISCREG_MAIR1: 1709 case MISCREG_DACR: 1710 case MISCREG_VTTBR: 1711 case MISCREG_SCR_EL3: 1712 case MISCREG_HCR_EL2: 1713 case MISCREG_TCR_EL1: 1714 case MISCREG_TCR_EL2: 1715 case MISCREG_TCR_EL3: 1716 case MISCREG_SCTLR_EL2: 1717 case MISCREG_SCTLR_EL3: 1718 case MISCREG_HSCTLR: 1719 case MISCREG_TTBR0_EL1: 1720 case MISCREG_TTBR1_EL1: 1721 case MISCREG_TTBR0_EL2: 1722 case MISCREG_TTBR1_EL2: 1723 case MISCREG_TTBR0_EL3: 1724 getITBPtr(tc)->invalidateMiscReg(); 1725 getDTBPtr(tc)->invalidateMiscReg(); 1726 break; 1727 case MISCREG_NZCV: 1728 { 1729 CPSR cpsr = val; 1730 1731 tc->setCCReg(CCREG_NZ, cpsr.nz); 1732 tc->setCCReg(CCREG_C, cpsr.c); 1733 tc->setCCReg(CCREG_V, cpsr.v); 1734 } 1735 break; 1736 case MISCREG_DAIF: 1737 { 1738 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1739 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1740 newVal = cpsr; 1741 misc_reg = MISCREG_CPSR; 1742 } 1743 break; 1744 case MISCREG_SP_EL0: 1745 tc->setIntReg(INTREG_SP0, newVal); 1746 break; 1747 case MISCREG_SP_EL1: 1748 tc->setIntReg(INTREG_SP1, newVal); 1749 break; 1750 case MISCREG_SP_EL2: 1751 tc->setIntReg(INTREG_SP2, newVal); 1752 break; 1753 case MISCREG_SPSEL: 1754 { 1755 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1756 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1757 newVal = cpsr; 1758 misc_reg = MISCREG_CPSR; 1759 } 1760 break; 1761 case MISCREG_CURRENTEL: 1762 { 1763 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1764 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1765 newVal = cpsr; 1766 misc_reg = MISCREG_CPSR; 1767 } 1768 break; 1769 case MISCREG_AT_S1E1R_Xt: 1770 case MISCREG_AT_S1E1W_Xt: 1771 case MISCREG_AT_S1E0R_Xt: 1772 case MISCREG_AT_S1E0W_Xt: 1773 case MISCREG_AT_S1E2R_Xt: 1774 case MISCREG_AT_S1E2W_Xt: 1775 case MISCREG_AT_S12E1R_Xt: 1776 case MISCREG_AT_S12E1W_Xt: 1777 case MISCREG_AT_S12E0R_Xt: 1778 case MISCREG_AT_S12E0W_Xt: 1779 case MISCREG_AT_S1E3R_Xt: 1780 case MISCREG_AT_S1E3W_Xt: 1781 { 1782 RequestPtr req = std::make_shared<Request>(); 1783 Request::Flags flags = 0; 1784 BaseTLB::Mode mode = BaseTLB::Read; 1785 TLB::ArmTranslationType tranType = TLB::NormalTran; 1786 Fault fault; 1787 switch(misc_reg) { 1788 case MISCREG_AT_S1E1R_Xt: 1789 flags = TLB::MustBeOne; 1790 tranType = TLB::S1E1Tran; 1791 mode = BaseTLB::Read; 1792 break; 1793 case MISCREG_AT_S1E1W_Xt: 1794 flags = TLB::MustBeOne; 1795 tranType = TLB::S1E1Tran; 1796 mode = BaseTLB::Write; 1797 break; 1798 case MISCREG_AT_S1E0R_Xt: 1799 flags = TLB::MustBeOne | TLB::UserMode; 1800 tranType = TLB::S1E0Tran; 1801 mode = BaseTLB::Read; 1802 break; 1803 case MISCREG_AT_S1E0W_Xt: 1804 flags = TLB::MustBeOne | TLB::UserMode; 1805 tranType = TLB::S1E0Tran; 1806 mode = BaseTLB::Write; 1807 break; 1808 case MISCREG_AT_S1E2R_Xt: 1809 flags = TLB::MustBeOne; 1810 tranType = TLB::S1E2Tran; 1811 mode = BaseTLB::Read; 1812 break; 1813 case MISCREG_AT_S1E2W_Xt: 1814 flags = TLB::MustBeOne; 1815 tranType = TLB::S1E2Tran; 1816 mode = BaseTLB::Write; 1817 break; 1818 case MISCREG_AT_S12E0R_Xt: 1819 flags = TLB::MustBeOne | TLB::UserMode; 1820 tranType = TLB::S12E0Tran; 1821 mode = BaseTLB::Read; 1822 break; 1823 case MISCREG_AT_S12E0W_Xt: 1824 flags = TLB::MustBeOne | TLB::UserMode; 1825 tranType = TLB::S12E0Tran; 1826 mode = BaseTLB::Write; 1827 break; 1828 case MISCREG_AT_S12E1R_Xt: 1829 flags = TLB::MustBeOne; 1830 tranType = TLB::S12E1Tran; 1831 mode = BaseTLB::Read; 1832 break; 1833 case MISCREG_AT_S12E1W_Xt: 1834 flags = TLB::MustBeOne; 1835 tranType = TLB::S12E1Tran; 1836 mode = BaseTLB::Write; 1837 break; 1838 case MISCREG_AT_S1E3R_Xt: 1839 flags = TLB::MustBeOne; 1840 tranType = TLB::S1E3Tran; 1841 mode = BaseTLB::Read; 1842 break; 1843 case MISCREG_AT_S1E3W_Xt: 1844 flags = TLB::MustBeOne; 1845 tranType = TLB::S1E3Tran; 1846 mode = BaseTLB::Write; 1847 break; 1848 } 1849 // If we're in timing mode then doing the translation in 1850 // functional mode then we're slightly distorting performance 1851 // results obtained from simulations. The translation should be 1852 // done in the same mode the core is running in. NOTE: This 1853 // can't be an atomic translation because that causes problems 1854 // with unexpected atomic snoop requests. 1855 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1856 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1857 tc->pcState().pc()); 1858 req->setContext(tc->contextId()); 1859 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1860 tranType); 1861 1862 MiscReg newVal; 1863 if (fault == NoFault) { 1864 Addr paddr = req->getPaddr(); 1865 uint64_t attr = getDTBPtr(tc)->getAttr(); 1866 uint64_t attr1 = attr >> 56; 1867 if (!attr1 || attr1 ==0x44) { 1868 attr |= 0x100; 1869 attr &= ~ uint64_t(0x80); 1870 } 1871 newVal = (paddr & mask(47, 12)) | attr; 1872 DPRINTF(MiscRegs, 1873 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1874 val, newVal); 1875 } else { 1876 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1877 armFault->update(tc); 1878 // Set fault bit and FSR 1879 FSR fsr = armFault->getFsr(tc); 1880 1881 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1882 if (cpsr.width) { // AArch32 1883 newVal = ((fsr >> 9) & 1) << 11; 1884 // rearrange fault status 1885 newVal |= ((fsr >> 0) & 0x3f) << 1; 1886 newVal |= 0x1; // F bit 1887 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1888 newVal |= armFault->isStage2() ? 0x200 : 0; 1889 } else { // AArch64 1890 newVal = 1; // F bit 1891 newVal |= fsr << 1; // FST 1892 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1893 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1894 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1895 newVal |= 1 << 11; // RES1 1896 } 1897 DPRINTF(MiscRegs, 1898 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1899 val, fsr, newVal); 1900 } 1901 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1902 return; 1903 } 1904 case MISCREG_SPSR_EL3: 1905 case MISCREG_SPSR_EL2: 1906 case MISCREG_SPSR_EL1: 1907 // Force bits 23:21 to 0 1908 newVal = val & ~(0x7 << 21); 1909 break; 1910 case MISCREG_L2CTLR: 1911 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1912 miscRegName[misc_reg], uint32_t(val)); 1913 break; 1914 1915 // Generic Timer registers 1916 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1917 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1918 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1919 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1920 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1921 break; 1922 } 1923 } 1924 setMiscRegNoEffect(misc_reg, newVal); 1925} 1926 1927BaseISADevice & 1928ISA::getGenericTimer(ThreadContext *tc) 1929{ 1930 // We only need to create an ISA interface the first time we try 1931 // to access the timer. 1932 if (timer) 1933 return *timer.get(); 1934 1935 assert(system); 1936 GenericTimer *generic_timer(system->getGenericTimer()); 1937 if (!generic_timer) { 1938 panic("Trying to get a generic timer from a system that hasn't " 1939 "been configured to use a generic timer.\n"); 1940 } 1941 1942 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1943 return *timer.get(); 1944} 1945 1946} 1947 1948ArmISA::ISA * 1949ArmISAParams::create() 1950{ 1951 return new ArmISA::ISA(this); 1952} 1953