isa.cc revision 12577
17405SAli.Saidi@ARM.com/* 211573SDylan.Johnson@ARM.com * Copyright (c) 2010-2016 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 439050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 4412406Sgabeblack@google.com#include "arch/arm/tlb.hh" 4511793Sbrandon.potter@amd.com#include "cpu/base.hh" 468887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 478232Snate@binkert.org#include "debug/Arm.hh" 488232Snate@binkert.org#include "debug/MiscRegs.hh" 4910844Sandreas.sandberg@arm.com#include "dev/arm/generic_timer.hh" 509384SAndreas.Sandberg@arm.com#include "params/ArmISA.hh" 517678Sgblack@eecs.umich.edu#include "sim/faults.hh" 528059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 538284SAli.Saidi@ARM.com#include "sim/system.hh" 547405SAli.Saidi@ARM.com 557405SAli.Saidi@ARM.comnamespace ArmISA 567405SAli.Saidi@ARM.com{ 577405SAli.Saidi@ARM.com 589384SAndreas.Sandberg@arm.comISA::ISA(Params *p) 5910461SAndreas.Sandberg@ARM.com : SimObject(p), 6010461SAndreas.Sandberg@ARM.com system(NULL), 6111165SRekai.GonzalezAlberquilla@arm.com _decoderFlavour(p->decoderFlavour), 6212109SRekai.GonzalezAlberquilla@arm.com _vecRegRenameMode(p->vecRegRenameMode), 6312479SCurtis.Dunham@arm.com pmu(p->pmu) 649384SAndreas.Sandberg@arm.com{ 6511770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_RST] = 0; 6610037SARM gem5 Developers 6710461SAndreas.Sandberg@ARM.com // Hook up a dummy device if we haven't been configured with a 6810461SAndreas.Sandberg@ARM.com // real PMU. By using a dummy device, we don't need to check that 6910461SAndreas.Sandberg@ARM.com // the PMU exist every time we try to access a PMU register. 7010461SAndreas.Sandberg@ARM.com if (!pmu) 7110461SAndreas.Sandberg@ARM.com pmu = &dummyDevice; 7210461SAndreas.Sandberg@ARM.com 7310609Sandreas.sandberg@arm.com // Give all ISA devices a pointer to this ISA 7410609Sandreas.sandberg@arm.com pmu->setISA(this); 7510609Sandreas.sandberg@arm.com 7610037SARM gem5 Developers system = dynamic_cast<ArmSystem *>(p->system); 7710037SARM gem5 Developers 7810037SARM gem5 Developers // Cache system-level properties 7910037SARM gem5 Developers if (FullSystem && system) { 8011771SCurtis.Dunham@arm.com highestELIs64 = system->highestELIs64(); 8110037SARM gem5 Developers haveSecurity = system->haveSecurity(); 8210037SARM gem5 Developers haveLPAE = system->haveLPAE(); 8310037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 8410037SARM gem5 Developers haveLargeAsid64 = system->haveLargeAsid64(); 8510037SARM gem5 Developers physAddrRange64 = system->physAddrRange64(); 8610037SARM gem5 Developers } else { 8711771SCurtis.Dunham@arm.com highestELIs64 = true; // ArmSystem::highestELIs64 does the same 8810037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 8910037SARM gem5 Developers haveLargeAsid64 = false; 9010037SARM gem5 Developers physAddrRange64 = 32; // dummy value 9110037SARM gem5 Developers } 9210037SARM gem5 Developers 9312477SCurtis.Dunham@arm.com initializeMiscRegMetadata(); 9410037SARM gem5 Developers preUnflattenMiscReg(); 9510037SARM gem5 Developers 969384SAndreas.Sandberg@arm.com clear(); 979384SAndreas.Sandberg@arm.com} 989384SAndreas.Sandberg@arm.com 9912479SCurtis.Dunham@arm.comstd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 10012479SCurtis.Dunham@arm.com 1019384SAndreas.Sandberg@arm.comconst ArmISAParams * 1029384SAndreas.Sandberg@arm.comISA::params() const 1039384SAndreas.Sandberg@arm.com{ 1049384SAndreas.Sandberg@arm.com return dynamic_cast<const Params *>(_params); 1059384SAndreas.Sandberg@arm.com} 1069384SAndreas.Sandberg@arm.com 1077427Sgblack@eecs.umich.eduvoid 1087427Sgblack@eecs.umich.eduISA::clear() 1097427Sgblack@eecs.umich.edu{ 1109385SAndreas.Sandberg@arm.com const Params *p(params()); 1119385SAndreas.Sandberg@arm.com 1127427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 1137427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 11410037SARM gem5 Developers 11510037SARM gem5 Developers // Initialize configurable default values 11610037SARM gem5 Developers miscRegs[MISCREG_MIDR] = p->midr; 11710037SARM gem5 Developers miscRegs[MISCREG_MIDR_EL1] = p->midr; 11810037SARM gem5 Developers miscRegs[MISCREG_VPIDR] = p->midr; 11910037SARM gem5 Developers 12010037SARM gem5 Developers if (FullSystem && system->highestELIs64()) { 12110037SARM gem5 Developers // Initialize AArch64 state 12210037SARM gem5 Developers clear64(p); 12310037SARM gem5 Developers return; 12410037SARM gem5 Developers } 12510037SARM gem5 Developers 12610037SARM gem5 Developers // Initialize AArch32 state... 12710037SARM gem5 Developers 1287427Sgblack@eecs.umich.edu CPSR cpsr = 0; 1297427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 1307427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 1317427Sgblack@eecs.umich.edu updateRegMap(cpsr); 1327427Sgblack@eecs.umich.edu 1337427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 13410037SARM gem5 Developers sctlr.te = (bool) sctlr_rst.te; 13510037SARM gem5 Developers sctlr.nmfi = (bool) sctlr_rst.nmfi; 13610037SARM gem5 Developers sctlr.v = (bool) sctlr_rst.v; 13710037SARM gem5 Developers sctlr.u = 1; 1387427Sgblack@eecs.umich.edu sctlr.xp = 1; 1397427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 1407427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 14110037SARM gem5 Developers sctlr.rao4 = 0xf; // SCTLR[6:3] 14210204SAli.Saidi@ARM.com sctlr.uci = 1; 14310204SAli.Saidi@ARM.com sctlr.dze = 1; 14410037SARM gem5 Developers miscRegs[MISCREG_SCTLR_NS] = sctlr; 1457427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 14610037SARM gem5 Developers miscRegs[MISCREG_HCPTR] = 0; 1477427Sgblack@eecs.umich.edu 14810037SARM gem5 Developers // Start with an event in the mailbox 1497427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 1507427Sgblack@eecs.umich.edu 15110037SARM gem5 Developers // Separate Instruction and Data TLBs 1527427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 1537427Sgblack@eecs.umich.edu 1547427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 1557427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 1567427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 1577427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 1587427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 1597427Sgblack@eecs.umich.edu mvfr0.divide = 1; 1607427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 1617427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 1627427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 1637427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 1647427Sgblack@eecs.umich.edu 1657427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1667427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1677427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1687427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1697427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1707427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1717427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1727427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1737427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1747427Sgblack@eecs.umich.edu 1757436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1767436Sdam.sunwoo@arm.com 17710037SARM gem5 Developers // @todo: PRRR and NMRR in secure state? 17810037SARM gem5 Developers miscRegs[MISCREG_PRRR_NS] = 1797436Sdam.sunwoo@arm.com (1 << 19) | // 19 1807436Sdam.sunwoo@arm.com (0 << 18) | // 18 1817436Sdam.sunwoo@arm.com (0 << 17) | // 17 1827436Sdam.sunwoo@arm.com (1 << 16) | // 16 1837436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1847436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1857436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1867436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1877436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1887436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1897436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1907436Sdam.sunwoo@arm.com 0; // 1:0 19110037SARM gem5 Developers miscRegs[MISCREG_NMRR_NS] = 1927436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1937436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1947436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1957436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1967436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1977436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1987436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 1997436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 2007436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 2017436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 2027436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 2037436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 2047436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 2057436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 2067436Sdam.sunwoo@arm.com 0; // 1:0 2077436Sdam.sunwoo@arm.com 2087644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 2098147SAli.Saidi@ARM.com 2109385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 2119385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 2129385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 2139385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 2149385SAndreas.Sandberg@arm.com 2159385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 2169385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 2179385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 2189385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 2199385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 2209385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 2219385SAndreas.Sandberg@arm.com 2229385SAndreas.Sandberg@arm.com miscRegs[MISCREG_FPSID] = p->fpsid; 2239385SAndreas.Sandberg@arm.com 22410037SARM gem5 Developers if (haveLPAE) { 22510037SARM gem5 Developers TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 22610037SARM gem5 Developers ttbcr.eae = 0; 22710037SARM gem5 Developers miscRegs[MISCREG_TTBCR_NS] = ttbcr; 22810037SARM gem5 Developers // Enforce consistency with system-level settings 22910037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 23010037SARM gem5 Developers } 23110037SARM gem5 Developers 23210037SARM gem5 Developers if (haveSecurity) { 23310037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] = sctlr; 23410037SARM gem5 Developers miscRegs[MISCREG_SCR] = 0; 23510037SARM gem5 Developers miscRegs[MISCREG_VBAR_S] = 0; 23610037SARM gem5 Developers } else { 23710037SARM gem5 Developers // we're always non-secure 23810037SARM gem5 Developers miscRegs[MISCREG_SCR] = 1; 23910037SARM gem5 Developers } 2408147SAli.Saidi@ARM.com 2417427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 2427427Sgblack@eecs.umich.edu} 2437427Sgblack@eecs.umich.edu 24410037SARM gem5 Developersvoid 24510037SARM gem5 DevelopersISA::clear64(const ArmISAParams *p) 24610037SARM gem5 Developers{ 24710037SARM gem5 Developers CPSR cpsr = 0; 24810037SARM gem5 Developers Addr rvbar = system->resetAddr64(); 24910037SARM gem5 Developers switch (system->highestEL()) { 25010037SARM gem5 Developers // Set initial EL to highest implemented EL using associated stack 25110037SARM gem5 Developers // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 25210037SARM gem5 Developers // value 25310037SARM gem5 Developers case EL3: 25410037SARM gem5 Developers cpsr.mode = MODE_EL3H; 25510037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL3] = rvbar; 25610037SARM gem5 Developers break; 25710037SARM gem5 Developers case EL2: 25810037SARM gem5 Developers cpsr.mode = MODE_EL2H; 25910037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL2] = rvbar; 26010037SARM gem5 Developers break; 26110037SARM gem5 Developers case EL1: 26210037SARM gem5 Developers cpsr.mode = MODE_EL1H; 26310037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL1] = rvbar; 26410037SARM gem5 Developers break; 26510037SARM gem5 Developers default: 26610037SARM gem5 Developers panic("Invalid highest implemented exception level"); 26710037SARM gem5 Developers break; 26810037SARM gem5 Developers } 26910037SARM gem5 Developers 27010037SARM gem5 Developers // Initialize rest of CPSR 27110037SARM gem5 Developers cpsr.daif = 0xf; // Mask all interrupts 27210037SARM gem5 Developers cpsr.ss = 0; 27310037SARM gem5 Developers cpsr.il = 0; 27410037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 27510037SARM gem5 Developers updateRegMap(cpsr); 27610037SARM gem5 Developers 27710037SARM gem5 Developers // Initialize other control registers 27810037SARM gem5 Developers miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 27910037SARM gem5 Developers if (haveSecurity) { 28011770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 28110037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 28211574SCurtis.Dunham@arm.com } else if (haveVirtualization) { 28311770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL2 (by mapping) 28411770SCurtis.Dunham@arm.com miscRegs[MISCREG_HSCTLR] = 0x30c50830; 28510037SARM gem5 Developers } else { 28611770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL1 (by mapping) 28711770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 28810037SARM gem5 Developers // Always non-secure 28910037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 1; 29010037SARM gem5 Developers } 29110037SARM gem5 Developers 29210037SARM gem5 Developers // Initialize configurable id registers 29310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 29410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 29510461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 29610461SAndreas.Sandberg@ARM.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 29710461SAndreas.Sandberg@ARM.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 29810461SAndreas.Sandberg@ARM.com 29910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 30010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 30110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 30210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 30310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 30410037SARM gem5 Developers 30510461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0_EL1] = 30610461SAndreas.Sandberg@ARM.com (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 30710461SAndreas.Sandberg@ARM.com 30810461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 30910461SAndreas.Sandberg@ARM.com 31010037SARM gem5 Developers // Enforce consistency with system-level settings... 31110037SARM gem5 Developers 31210037SARM gem5 Developers // EL3 31310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 31410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 31511574SCurtis.Dunham@arm.com haveSecurity ? 0x2 : 0x0); 31610037SARM gem5 Developers // EL2 31710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 31810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 31911574SCurtis.Dunham@arm.com haveVirtualization ? 0x2 : 0x0); 32010037SARM gem5 Developers // Large ASID support 32110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 32210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 32310037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 32410037SARM gem5 Developers // Physical address size 32510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 32610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 32710037SARM gem5 Developers encodePhysAddrRange64(physAddrRange64)); 32810037SARM gem5 Developers} 32910037SARM gem5 Developers 3307405SAli.Saidi@ARM.comMiscReg 33110035Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg) const 3327405SAli.Saidi@ARM.com{ 3337405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 3347614Sminkyu.jeong@arm.com 33512478SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 33612478SCurtis.Dunham@arm.com const auto &map = getMiscIndices(misc_reg); 33712478SCurtis.Dunham@arm.com int lower = map.first, upper = map.second; 33812478SCurtis.Dunham@arm.com // NB!: apply architectural masks according to desired register, 33912478SCurtis.Dunham@arm.com // despite possibly getting value from different (mapped) register. 34012478SCurtis.Dunham@arm.com auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 34112478SCurtis.Dunham@arm.com |(miscRegs[upper] << 32)); 34212478SCurtis.Dunham@arm.com if (val & reg.res0()) { 34312478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 34412478SCurtis.Dunham@arm.com miscRegName[misc_reg], val & reg.res0()); 34512478SCurtis.Dunham@arm.com } 34612478SCurtis.Dunham@arm.com if ((val & reg.res1()) != reg.res1()) { 34712478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 34812478SCurtis.Dunham@arm.com miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 34912478SCurtis.Dunham@arm.com } 35012478SCurtis.Dunham@arm.com return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 3517405SAli.Saidi@ARM.com} 3527405SAli.Saidi@ARM.com 3537405SAli.Saidi@ARM.com 3547405SAli.Saidi@ARM.comMiscReg 3557405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 3567405SAli.Saidi@ARM.com{ 35710037SARM gem5 Developers CPSR cpsr = 0; 35810037SARM gem5 Developers PCState pc = 0; 35910037SARM gem5 Developers SCR scr = 0; 3609050Schander.sudanthi@arm.com 3617405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 36210037SARM gem5 Developers cpsr = miscRegs[misc_reg]; 36310037SARM gem5 Developers pc = tc->pcState(); 3647720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 3657720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 3667405SAli.Saidi@ARM.com return cpsr; 3677405SAli.Saidi@ARM.com } 3687757SAli.Saidi@ARM.com 36910037SARM gem5 Developers#ifndef NDEBUG 37010037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 37110037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 37210037SARM gem5 Developers warn("Unimplemented system register %s read.\n", 37310037SARM gem5 Developers miscRegName[misc_reg]); 37410037SARM gem5 Developers else 37510037SARM gem5 Developers panic("Unimplemented system register %s read.\n", 37610037SARM gem5 Developers miscRegName[misc_reg]); 37710037SARM gem5 Developers } 37810037SARM gem5 Developers#endif 37910037SARM gem5 Developers 38010037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 38110037SARM gem5 Developers case MISCREG_HCR: 38210037SARM gem5 Developers { 38310037SARM gem5 Developers if (!haveVirtualization) 38410037SARM gem5 Developers return 0; 38510037SARM gem5 Developers else 38610037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HCR); 38710037SARM gem5 Developers } 38810037SARM gem5 Developers case MISCREG_CPACR: 38910037SARM gem5 Developers { 39010037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 39110037SARM gem5 Developers CPACR cpacrMask = 0; 39210037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 39310037SARM gem5 Developers // be readable? (straight copy from the write code) 39410037SARM gem5 Developers cpacrMask.cp10 = ones; 39510037SARM gem5 Developers cpacrMask.cp11 = ones; 39610037SARM gem5 Developers cpacrMask.asedis = ones; 39710037SARM gem5 Developers 39810037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 39910037SARM gem5 Developers if (haveSecurity) { 40010037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 40110037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 40210037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON)) { 40310037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 40410037SARM gem5 Developers // NB: Skipping the full loop, here 40510037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 40610037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 40710037SARM gem5 Developers } 40810037SARM gem5 Developers } 40910037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 41010037SARM gem5 Developers val &= cpacrMask; 41110037SARM gem5 Developers DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 41210037SARM gem5 Developers miscRegName[misc_reg], val); 41310037SARM gem5 Developers return val; 41410037SARM gem5 Developers } 4158284SAli.Saidi@ARM.com case MISCREG_MPIDR: 41610037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 41710037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 41810037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 41910037SARM gem5 Developers return getMPIDR(system, tc); 4209050Schander.sudanthi@arm.com } else { 42110037SARM gem5 Developers return readMiscReg(MISCREG_VMPIDR, tc); 42210037SARM gem5 Developers } 42310037SARM gem5 Developers break; 42410037SARM gem5 Developers case MISCREG_MPIDR_EL1: 42510037SARM gem5 Developers // @todo in the absence of v8 virtualization support just return MPIDR_EL1 42610037SARM gem5 Developers return getMPIDR(system, tc) & 0xffffffff; 42710037SARM gem5 Developers case MISCREG_VMPIDR: 42810037SARM gem5 Developers // top bit defined as RES1 42910037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 43010037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 43110037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 43210037SARM gem5 Developers case MISCREG_MIDR: 43310037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 43410037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 43510037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 43610037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 43710037SARM gem5 Developers } else { 43810037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_VPIDR); 4399050Schander.sudanthi@arm.com } 4408284SAli.Saidi@ARM.com break; 44110037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 44210037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 44310037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 44410037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 44510037SARM gem5 Developers case MISCREG_TCMTR: // No TCM's 44610037SARM gem5 Developers return 0; 44710037SARM gem5 Developers 4487405SAli.Saidi@ARM.com case MISCREG_CLIDR: 4497731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 4508468Swade.walker@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 4518468Swade.walker@arm.com "ARM implementations.\n"); 4528468Swade.walker@arm.com return 0x00200000; 4537405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 4547731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 4557405SAli.Saidi@ARM.com "always reads as 0.\n"); 4567405SAli.Saidi@ARM.com break; 45711809Sbaz21@cam.ac.uk case MISCREG_CTR: // AArch32, ARMv7, top bit set 45811809Sbaz21@cam.ac.uk case MISCREG_CTR_EL0: // AArch64 4599130Satgutier@umich.edu { 4609130Satgutier@umich.edu //all caches have the same line size in gem5 4619130Satgutier@umich.edu //4 byte words in ARM 4629130Satgutier@umich.edu unsigned lineSizeWords = 4639814Sandreas.hansson@arm.com tc->getSystemPtr()->cacheLineSize() / 4; 4649130Satgutier@umich.edu unsigned log2LineSizeWords = 0; 4659130Satgutier@umich.edu 4669130Satgutier@umich.edu while (lineSizeWords >>= 1) { 4679130Satgutier@umich.edu ++log2LineSizeWords; 4689130Satgutier@umich.edu } 4699130Satgutier@umich.edu 4709130Satgutier@umich.edu CTR ctr = 0; 4719130Satgutier@umich.edu //log2 of minimun i-cache line size (words) 4729130Satgutier@umich.edu ctr.iCacheLineSize = log2LineSizeWords; 4739130Satgutier@umich.edu //b11 - gem5 uses pipt 4749130Satgutier@umich.edu ctr.l1IndexPolicy = 0x3; 4759130Satgutier@umich.edu //log2 of minimum d-cache line size (words) 4769130Satgutier@umich.edu ctr.dCacheLineSize = log2LineSizeWords; 4779130Satgutier@umich.edu //log2 of max reservation size (words) 4789130Satgutier@umich.edu ctr.erg = log2LineSizeWords; 4799130Satgutier@umich.edu //log2 of max writeback size (words) 4809130Satgutier@umich.edu ctr.cwg = log2LineSizeWords; 4819130Satgutier@umich.edu //b100 - gem5 format is ARMv7 4829130Satgutier@umich.edu ctr.format = 0x4; 4839130Satgutier@umich.edu 4849130Satgutier@umich.edu return ctr; 4859130Satgutier@umich.edu } 4867583SAli.Saidi@arm.com case MISCREG_ACTLR: 4877583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 4887583SAli.Saidi@arm.com break; 48910461SAndreas.Sandberg@ARM.com 49010461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 49110461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 49210461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 49310461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 49410461SAndreas.Sandberg@ARM.com return pmu->readMiscReg(misc_reg); 49510461SAndreas.Sandberg@ARM.com 4968302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 4978302SAli.Saidi@ARM.com panic("shouldn't be reading this register seperately\n"); 4987783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 4997783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 5007783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 5017783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 50210037SARM gem5 Developers case MISCREG_FPSR: 50310037SARM gem5 Developers { 50410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 50510037SARM gem5 Developers FPSCR fpscrMask = 0; 50610037SARM gem5 Developers fpscrMask.ioc = ones; 50710037SARM gem5 Developers fpscrMask.dzc = ones; 50810037SARM gem5 Developers fpscrMask.ofc = ones; 50910037SARM gem5 Developers fpscrMask.ufc = ones; 51010037SARM gem5 Developers fpscrMask.ixc = ones; 51110037SARM gem5 Developers fpscrMask.idc = ones; 51210037SARM gem5 Developers fpscrMask.qc = ones; 51310037SARM gem5 Developers fpscrMask.v = ones; 51410037SARM gem5 Developers fpscrMask.c = ones; 51510037SARM gem5 Developers fpscrMask.z = ones; 51610037SARM gem5 Developers fpscrMask.n = ones; 51710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 51810037SARM gem5 Developers } 51910037SARM gem5 Developers case MISCREG_FPCR: 52010037SARM gem5 Developers { 52110037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 52210037SARM gem5 Developers FPSCR fpscrMask = 0; 52310037SARM gem5 Developers fpscrMask.ioe = ones; 52410037SARM gem5 Developers fpscrMask.dze = ones; 52510037SARM gem5 Developers fpscrMask.ofe = ones; 52610037SARM gem5 Developers fpscrMask.ufe = ones; 52710037SARM gem5 Developers fpscrMask.ixe = ones; 52810037SARM gem5 Developers fpscrMask.ide = ones; 52910037SARM gem5 Developers fpscrMask.len = ones; 53010037SARM gem5 Developers fpscrMask.stride = ones; 53110037SARM gem5 Developers fpscrMask.rMode = ones; 53210037SARM gem5 Developers fpscrMask.fz = ones; 53310037SARM gem5 Developers fpscrMask.dn = ones; 53410037SARM gem5 Developers fpscrMask.ahp = ones; 53510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 53610037SARM gem5 Developers } 53710037SARM gem5 Developers case MISCREG_NZCV: 53810037SARM gem5 Developers { 53910037SARM gem5 Developers CPSR cpsr = 0; 54010338SCurtis.Dunham@arm.com cpsr.nz = tc->readCCReg(CCREG_NZ); 54110338SCurtis.Dunham@arm.com cpsr.c = tc->readCCReg(CCREG_C); 54210338SCurtis.Dunham@arm.com cpsr.v = tc->readCCReg(CCREG_V); 54310037SARM gem5 Developers return cpsr; 54410037SARM gem5 Developers } 54510037SARM gem5 Developers case MISCREG_DAIF: 54610037SARM gem5 Developers { 54710037SARM gem5 Developers CPSR cpsr = 0; 54810037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 54910037SARM gem5 Developers return cpsr; 55010037SARM gem5 Developers } 55110037SARM gem5 Developers case MISCREG_SP_EL0: 55210037SARM gem5 Developers { 55310037SARM gem5 Developers return tc->readIntReg(INTREG_SP0); 55410037SARM gem5 Developers } 55510037SARM gem5 Developers case MISCREG_SP_EL1: 55610037SARM gem5 Developers { 55710037SARM gem5 Developers return tc->readIntReg(INTREG_SP1); 55810037SARM gem5 Developers } 55910037SARM gem5 Developers case MISCREG_SP_EL2: 56010037SARM gem5 Developers { 56110037SARM gem5 Developers return tc->readIntReg(INTREG_SP2); 56210037SARM gem5 Developers } 56310037SARM gem5 Developers case MISCREG_SPSEL: 56410037SARM gem5 Developers { 56510037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0x1; 56610037SARM gem5 Developers } 56710037SARM gem5 Developers case MISCREG_CURRENTEL: 56810037SARM gem5 Developers { 56910037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0xc; 57010037SARM gem5 Developers } 5718549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 5728868SMatt.Horsnell@arm.com { 5738868SMatt.Horsnell@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 5748868SMatt.Horsnell@arm.com L2CTLR l2ctlr = 0; 5758868SMatt.Horsnell@arm.com // b00:1CPU to b11:4CPUs 5768868SMatt.Horsnell@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 5778868SMatt.Horsnell@arm.com return l2ctlr; 5788868SMatt.Horsnell@arm.com } 5798868SMatt.Horsnell@arm.com case MISCREG_DBGDIDR: 5808868SMatt.Horsnell@arm.com /* For now just implement the version number. 58110461SAndreas.Sandberg@ARM.com * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 5828868SMatt.Horsnell@arm.com */ 58310461SAndreas.Sandberg@ARM.com return 0x5 << 16; 58410037SARM gem5 Developers case MISCREG_DBGDSCRint: 5858868SMatt.Horsnell@arm.com return 0; 58610037SARM gem5 Developers case MISCREG_ISR: 58711150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 58810037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR), 58910037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 59010037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR)); 59110037SARM gem5 Developers case MISCREG_ISR_EL1: 59211150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 59310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR_EL2), 59410037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 59510037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR_EL3)); 59610037SARM gem5 Developers case MISCREG_DCZID_EL0: 59710037SARM gem5 Developers return 0x04; // DC ZVA clear 64-byte chunks 59810037SARM gem5 Developers case MISCREG_HCPTR: 59910037SARM gem5 Developers { 60010037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(misc_reg); 60110037SARM gem5 Developers // The trap bit associated with CP14 is defined as RAZ 60210037SARM gem5 Developers val &= ~(1 << 14); 60310037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 60410037SARM gem5 Developers // HCPTR is RAO/WI 60510037SARM gem5 Developers bool secure_lookup = haveSecurity && 60610037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 60710037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 60810037SARM gem5 Developers if (!secure_lookup) { 60910037SARM gem5 Developers MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 61010037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 61110037SARM gem5 Developers } 61210037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 61310037SARM gem5 Developers val |= 0x33FF; 61410037SARM gem5 Developers return (val); 61510037SARM gem5 Developers } 61610037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 61710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 61810037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 61910037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 62010037SARM gem5 Developers case MISCREG_HVBAR: // bottom bits reserved 62110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 62211769SCurtis.Dunham@arm.com case MISCREG_SCTLR: 62311769SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 62410037SARM gem5 Developers case MISCREG_SCTLR_EL1: 62511770SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 62611770SCurtis.Dunham@arm.com case MISCREG_SCTLR_EL2: 62710037SARM gem5 Developers case MISCREG_SCTLR_EL3: 62811770SCurtis.Dunham@arm.com case MISCREG_HSCTLR: 62911769SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 63010844Sandreas.sandberg@arm.com 63111772SCurtis.Dunham@arm.com case MISCREG_ID_PFR0: 63211772SCurtis.Dunham@arm.com // !ThumbEE | !Jazelle | Thumb | ARM 63311772SCurtis.Dunham@arm.com return 0x00000031; 63411772SCurtis.Dunham@arm.com case MISCREG_ID_PFR1: 63511774SCurtis.Dunham@arm.com { // Timer | Virti | !M Profile | TrustZone | ARMv4 63611774SCurtis.Dunham@arm.com bool haveTimer = (system->getGenericTimer() != NULL); 63711774SCurtis.Dunham@arm.com return 0x00000001 63811774SCurtis.Dunham@arm.com | (haveSecurity ? 0x00000010 : 0x0) 63911774SCurtis.Dunham@arm.com | (haveVirtualization ? 0x00001000 : 0x0) 64011774SCurtis.Dunham@arm.com | (haveTimer ? 0x00010000 : 0x0); 64111774SCurtis.Dunham@arm.com } 64211773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR0_EL1: 64311773SCurtis.Dunham@arm.com return 0x0000000000000002 // AArch{64,32} supported at EL0 64411773SCurtis.Dunham@arm.com | 0x0000000000000020 // EL1 64511773SCurtis.Dunham@arm.com | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 64611773SCurtis.Dunham@arm.com | (haveSecurity ? 0x0000000000002000 : 0); // EL3 64711773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR1_EL1: 64811773SCurtis.Dunham@arm.com return 0; // bits [63:0] RES0 (reserved for future use) 64911772SCurtis.Dunham@arm.com 65010037SARM gem5 Developers // Generic Timer registers 65110844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 65210844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 65310844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 65410844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 65510844Sandreas.sandberg@arm.com return getGenericTimer(tc).readMiscReg(misc_reg); 65610844Sandreas.sandberg@arm.com 65710188Sgeoffrey.blake@arm.com default: 65810037SARM gem5 Developers break; 65910037SARM gem5 Developers 6607405SAli.Saidi@ARM.com } 6617405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 6627405SAli.Saidi@ARM.com} 6637405SAli.Saidi@ARM.com 6647405SAli.Saidi@ARM.comvoid 6657405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 6667405SAli.Saidi@ARM.com{ 6677405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 6687614Sminkyu.jeong@arm.com 66912478SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 67012478SCurtis.Dunham@arm.com const auto &map = getMiscIndices(misc_reg); 67112478SCurtis.Dunham@arm.com int lower = map.first, upper = map.second; 67212478SCurtis.Dunham@arm.com 67312478SCurtis.Dunham@arm.com auto v = (val & ~reg.wi()) | reg.rao(); 67411771SCurtis.Dunham@arm.com if (upper > 0) { 67512478SCurtis.Dunham@arm.com miscRegs[lower] = bits(v, 31, 0); 67612478SCurtis.Dunham@arm.com miscRegs[upper] = bits(v, 63, 32); 67710037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 67812478SCurtis.Dunham@arm.com misc_reg, lower, upper, v); 67910037SARM gem5 Developers } else { 68012478SCurtis.Dunham@arm.com miscRegs[lower] = v; 68110037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 68212478SCurtis.Dunham@arm.com misc_reg, lower, v); 68310037SARM gem5 Developers } 6847405SAli.Saidi@ARM.com} 6857405SAli.Saidi@ARM.com 68612406Sgabeblack@google.comnamespace { 68712406Sgabeblack@google.com 68812406Sgabeblack@google.comtemplate<typename T> 68912406Sgabeblack@google.comTLB * 69012406Sgabeblack@google.comgetITBPtr(T *tc) 69112406Sgabeblack@google.com{ 69212406Sgabeblack@google.com auto tlb = dynamic_cast<TLB *>(tc->getITBPtr()); 69312406Sgabeblack@google.com assert(tlb); 69412406Sgabeblack@google.com return tlb; 69512406Sgabeblack@google.com} 69612406Sgabeblack@google.com 69712406Sgabeblack@google.comtemplate<typename T> 69812406Sgabeblack@google.comTLB * 69912406Sgabeblack@google.comgetDTBPtr(T *tc) 70012406Sgabeblack@google.com{ 70112406Sgabeblack@google.com auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr()); 70212406Sgabeblack@google.com assert(tlb); 70312406Sgabeblack@google.com return tlb; 70412406Sgabeblack@google.com} 70512406Sgabeblack@google.com 70612406Sgabeblack@google.com} // anonymous namespace 70712406Sgabeblack@google.com 7087405SAli.Saidi@ARM.comvoid 7097405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 7107405SAli.Saidi@ARM.com{ 7117749SAli.Saidi@ARM.com 7127405SAli.Saidi@ARM.com MiscReg newVal = val; 7138284SAli.Saidi@ARM.com int x; 71410037SARM gem5 Developers bool secure_lookup; 71510037SARM gem5 Developers bool hyp; 7168284SAli.Saidi@ARM.com System *sys; 7178284SAli.Saidi@ARM.com ThreadContext *oc; 71810037SARM gem5 Developers uint8_t target_el; 71910037SARM gem5 Developers uint16_t asid; 72010037SARM gem5 Developers SCR scr; 7218284SAli.Saidi@ARM.com 7227405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 7237405SAli.Saidi@ARM.com updateRegMap(val); 7247749SAli.Saidi@ARM.com 7257749SAli.Saidi@ARM.com 7267749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 7277749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 7287405SAli.Saidi@ARM.com CPSR cpsr = val; 72912510Sgiacomo.travaglini@arm.com if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 73012406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 73112406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 7327749SAli.Saidi@ARM.com } 7337749SAli.Saidi@ARM.com 7347614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 7357614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 7367720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 7377720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 7387720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 7398887Sgeoffrey.blake@arm.com 7408887Sgeoffrey.blake@arm.com // Follow slightly different semantics if a CheckerCPU object 7418887Sgeoffrey.blake@arm.com // is connected 7428887Sgeoffrey.blake@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 7438887Sgeoffrey.blake@arm.com if (checker) { 7448887Sgeoffrey.blake@arm.com tc->pcStateNoRecord(pc); 7458887Sgeoffrey.blake@arm.com } else { 7468887Sgeoffrey.blake@arm.com tc->pcState(pc); 7478887Sgeoffrey.blake@arm.com } 7487408Sgblack@eecs.umich.edu } else { 74910037SARM gem5 Developers#ifndef NDEBUG 75010037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 75110037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 75210037SARM gem5 Developers warn("Unimplemented system register %s write with %#x.\n", 75310037SARM gem5 Developers miscRegName[misc_reg], val); 75410037SARM gem5 Developers else 75510037SARM gem5 Developers panic("Unimplemented system register %s write with %#x.\n", 75610037SARM gem5 Developers miscRegName[misc_reg], val); 75710037SARM gem5 Developers } 75810037SARM gem5 Developers#endif 75910037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 7607408Sgblack@eecs.umich.edu case MISCREG_CPACR: 7617408Sgblack@eecs.umich.edu { 7628206SWilliam.Wang@arm.com 7638206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 7648206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 7658206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 7668206SWilliam.Wang@arm.com // be writable 7678206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 7688206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 7698206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 77010037SARM gem5 Developers 77110037SARM gem5 Developers // Security Extensions may limit the writability of CPACR 77210037SARM gem5 Developers if (haveSecurity) { 77310037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 77410037SARM gem5 Developers CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 77510037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON)) { 77610037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 77710037SARM gem5 Developers // NB: Skipping the full loop, here 77810037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 77910037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 78010037SARM gem5 Developers } 78110037SARM gem5 Developers } 78210037SARM gem5 Developers 78310037SARM gem5 Developers MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 7848206SWilliam.Wang@arm.com newVal &= cpacrMask; 78510037SARM gem5 Developers newVal |= old_val & ~cpacrMask; 78610037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 78710037SARM gem5 Developers miscRegName[misc_reg], newVal); 78810037SARM gem5 Developers } 78910037SARM gem5 Developers break; 79010037SARM gem5 Developers case MISCREG_CPACR_EL1: 79110037SARM gem5 Developers { 79210037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 79310037SARM gem5 Developers CPACR cpacrMask = 0; 79410037SARM gem5 Developers cpacrMask.tta = ones; 79510037SARM gem5 Developers cpacrMask.fpen = ones; 79610037SARM gem5 Developers newVal &= cpacrMask; 79710037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 79810037SARM gem5 Developers miscRegName[misc_reg], newVal); 79910037SARM gem5 Developers } 80010037SARM gem5 Developers break; 80110037SARM gem5 Developers case MISCREG_CPTR_EL2: 80210037SARM gem5 Developers { 80310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 80410037SARM gem5 Developers CPTR cptrMask = 0; 80510037SARM gem5 Developers cptrMask.tcpac = ones; 80610037SARM gem5 Developers cptrMask.tta = ones; 80710037SARM gem5 Developers cptrMask.tfp = ones; 80810037SARM gem5 Developers newVal &= cptrMask; 80910037SARM gem5 Developers cptrMask = 0; 81010037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 81110037SARM gem5 Developers cptrMask.res1_9_0_el2 = ones; 81210037SARM gem5 Developers newVal |= cptrMask; 81310037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 81410037SARM gem5 Developers miscRegName[misc_reg], newVal); 81510037SARM gem5 Developers } 81610037SARM gem5 Developers break; 81710037SARM gem5 Developers case MISCREG_CPTR_EL3: 81810037SARM gem5 Developers { 81910037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 82010037SARM gem5 Developers CPTR cptrMask = 0; 82110037SARM gem5 Developers cptrMask.tcpac = ones; 82210037SARM gem5 Developers cptrMask.tta = ones; 82310037SARM gem5 Developers cptrMask.tfp = ones; 82410037SARM gem5 Developers newVal &= cptrMask; 8258206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 8268206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 8277408Sgblack@eecs.umich.edu } 8287408Sgblack@eecs.umich.edu break; 8297408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 8307731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 8318206SWilliam.Wang@arm.com return; 83210037SARM gem5 Developers 83310037SARM gem5 Developers case MISCREG_DC_ZVA_Xt: 83410037SARM gem5 Developers warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 83510037SARM gem5 Developers return; 83610037SARM gem5 Developers 8377408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 8387408Sgblack@eecs.umich.edu { 8397408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 8407408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 8417408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 8427408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 8437408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 8447408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 8457408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 8467408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 84710037SARM gem5 Developers fpscrMask.ioe = ones; 84810037SARM gem5 Developers fpscrMask.dze = ones; 84910037SARM gem5 Developers fpscrMask.ofe = ones; 85010037SARM gem5 Developers fpscrMask.ufe = ones; 85110037SARM gem5 Developers fpscrMask.ixe = ones; 85210037SARM gem5 Developers fpscrMask.ide = ones; 8537408Sgblack@eecs.umich.edu fpscrMask.len = ones; 8547408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 8557408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 8567408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 8577408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 8587408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 8597408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 8607408Sgblack@eecs.umich.edu fpscrMask.v = ones; 8617408Sgblack@eecs.umich.edu fpscrMask.c = ones; 8627408Sgblack@eecs.umich.edu fpscrMask.z = ones; 8637408Sgblack@eecs.umich.edu fpscrMask.n = ones; 8647408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 86510037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 86610037SARM gem5 Developers ~(uint32_t)fpscrMask); 8679377Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(newVal); 8687408Sgblack@eecs.umich.edu } 8697408Sgblack@eecs.umich.edu break; 87010037SARM gem5 Developers case MISCREG_FPSR: 87110037SARM gem5 Developers { 87210037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 87310037SARM gem5 Developers FPSCR fpscrMask = 0; 87410037SARM gem5 Developers fpscrMask.ioc = ones; 87510037SARM gem5 Developers fpscrMask.dzc = ones; 87610037SARM gem5 Developers fpscrMask.ofc = ones; 87710037SARM gem5 Developers fpscrMask.ufc = ones; 87810037SARM gem5 Developers fpscrMask.ixc = ones; 87910037SARM gem5 Developers fpscrMask.idc = ones; 88010037SARM gem5 Developers fpscrMask.qc = ones; 88110037SARM gem5 Developers fpscrMask.v = ones; 88210037SARM gem5 Developers fpscrMask.c = ones; 88310037SARM gem5 Developers fpscrMask.z = ones; 88410037SARM gem5 Developers fpscrMask.n = ones; 88510037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 88610037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 88710037SARM gem5 Developers ~(uint32_t)fpscrMask); 88810037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 88910037SARM gem5 Developers } 89010037SARM gem5 Developers break; 89110037SARM gem5 Developers case MISCREG_FPCR: 89210037SARM gem5 Developers { 89310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 89410037SARM gem5 Developers FPSCR fpscrMask = 0; 89510037SARM gem5 Developers fpscrMask.ioe = ones; 89610037SARM gem5 Developers fpscrMask.dze = ones; 89710037SARM gem5 Developers fpscrMask.ofe = ones; 89810037SARM gem5 Developers fpscrMask.ufe = ones; 89910037SARM gem5 Developers fpscrMask.ixe = ones; 90010037SARM gem5 Developers fpscrMask.ide = ones; 90110037SARM gem5 Developers fpscrMask.len = ones; 90210037SARM gem5 Developers fpscrMask.stride = ones; 90310037SARM gem5 Developers fpscrMask.rMode = ones; 90410037SARM gem5 Developers fpscrMask.fz = ones; 90510037SARM gem5 Developers fpscrMask.dn = ones; 90610037SARM gem5 Developers fpscrMask.ahp = ones; 90710037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 90810037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 90910037SARM gem5 Developers ~(uint32_t)fpscrMask); 91010037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 91110037SARM gem5 Developers } 91210037SARM gem5 Developers break; 9138302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 9148302SAli.Saidi@ARM.com { 9158302SAli.Saidi@ARM.com assert(!(newVal & ~CpsrMaskQ)); 91610037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 9178302SAli.Saidi@ARM.com misc_reg = MISCREG_CPSR; 9188302SAli.Saidi@ARM.com } 9198302SAli.Saidi@ARM.com break; 9207783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 9217783SGiacomo.Gabrielli@arm.com { 92210037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 92310037SARM gem5 Developers (newVal & FpscrQcMask); 9247783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 9257783SGiacomo.Gabrielli@arm.com } 9267783SGiacomo.Gabrielli@arm.com break; 9277783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 9287783SGiacomo.Gabrielli@arm.com { 92910037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 93010037SARM gem5 Developers (newVal & FpscrExcMask); 9317783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 9327783SGiacomo.Gabrielli@arm.com } 9337783SGiacomo.Gabrielli@arm.com break; 9347408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 9357408Sgblack@eecs.umich.edu { 9368206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 9378206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 9387408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 9397408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 94010037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 9417408Sgblack@eecs.umich.edu } 9427408Sgblack@eecs.umich.edu break; 94310037SARM gem5 Developers case MISCREG_HCR: 94410037SARM gem5 Developers { 94510037SARM gem5 Developers if (!haveVirtualization) 94610037SARM gem5 Developers return; 94710037SARM gem5 Developers } 94810037SARM gem5 Developers break; 94910037SARM gem5 Developers case MISCREG_IFSR: 95010037SARM gem5 Developers { 95110037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.96 95210037SARM gem5 Developers const uint32_t ifsrMask = 95310037SARM gem5 Developers mask(31, 13) | mask(11, 11) | mask(8, 6); 95410037SARM gem5 Developers newVal = newVal & ~ifsrMask; 95510037SARM gem5 Developers } 95610037SARM gem5 Developers break; 95710037SARM gem5 Developers case MISCREG_DFSR: 95810037SARM gem5 Developers { 95910037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.52 96010037SARM gem5 Developers const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 96110037SARM gem5 Developers newVal = newVal & ~dfsrMask; 96210037SARM gem5 Developers } 96310037SARM gem5 Developers break; 96410037SARM gem5 Developers case MISCREG_AMAIR0: 96510037SARM gem5 Developers case MISCREG_AMAIR1: 96610037SARM gem5 Developers { 96710037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 96810037SARM gem5 Developers // Valid only with LPAE 96910037SARM gem5 Developers if (!haveLPAE) 97010037SARM gem5 Developers return; 97110037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 97210037SARM gem5 Developers } 97310037SARM gem5 Developers break; 97410037SARM gem5 Developers case MISCREG_SCR: 97512406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 97612406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 97710037SARM gem5 Developers break; 9787408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 9797408Sgblack@eecs.umich.edu { 9807408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 98110037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 98211769SCurtis.Dunham@arm.com MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns) 98311769SCurtis.Dunham@arm.com ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS; 98410037SARM gem5 Developers SCTLR sctlr = miscRegs[sctlr_idx]; 9857408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 98610037SARM gem5 Developers new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 98710037SARM gem5 Developers miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 98812406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 98912406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 9907408Sgblack@eecs.umich.edu } 9919385SAndreas.Sandberg@arm.com case MISCREG_MIDR: 9929385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR0: 9939385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR1: 99410461SAndreas.Sandberg@ARM.com case MISCREG_ID_DFR0: 9959385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR0: 9969385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR1: 9979385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR2: 9989385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR3: 9999385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR0: 10009385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR1: 10019385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR2: 10029385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR3: 10039385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR4: 10049385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR5: 10059385SAndreas.Sandberg@arm.com 10069385SAndreas.Sandberg@arm.com case MISCREG_MPIDR: 10079385SAndreas.Sandberg@arm.com case MISCREG_FPSID: 10087408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 10097408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 10107408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 101110037SARM gem5 Developers 101210037SARM gem5 Developers case MISCREG_ID_AA64AFR0_EL1: 101310037SARM gem5 Developers case MISCREG_ID_AA64AFR1_EL1: 101410037SARM gem5 Developers case MISCREG_ID_AA64DFR0_EL1: 101510037SARM gem5 Developers case MISCREG_ID_AA64DFR1_EL1: 101610037SARM gem5 Developers case MISCREG_ID_AA64ISAR0_EL1: 101710037SARM gem5 Developers case MISCREG_ID_AA64ISAR1_EL1: 101810037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 101910037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 102010037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 102110037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 10229385SAndreas.Sandberg@arm.com // ID registers are constants. 10237408Sgblack@eecs.umich.edu return; 10249385SAndreas.Sandberg@arm.com 102510037SARM gem5 Developers // TLBI all entries, EL0&1 inner sharable (ignored) 10267408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 102710037SARM gem5 Developers case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 102810037SARM gem5 Developers assert32(tc); 102910037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 103010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 103110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 10328284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 10338284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 10348284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 103512406Sgabeblack@google.com getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el); 103612406Sgabeblack@google.com getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el); 10378887Sgeoffrey.blake@arm.com 10388887Sgeoffrey.blake@arm.com // If CheckerCPU is connected, need to notify it of a flush 10398887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 10408733Sgeoffrey.blake@arm.com if (checker) { 104112406Sgabeblack@google.com getITBPtr(checker)->flushAllSecurity(secure_lookup, 104212406Sgabeblack@google.com target_el); 104312406Sgabeblack@google.com getDTBPtr(checker)->flushAllSecurity(secure_lookup, 104412406Sgabeblack@google.com target_el); 10458733Sgeoffrey.blake@arm.com } 10468284SAli.Saidi@ARM.com } 10477408Sgblack@eecs.umich.edu return; 104810037SARM gem5 Developers // TLBI all entries, EL0&1, instruction side 10497408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 105010037SARM gem5 Developers assert32(tc); 105110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 105210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 105310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 105412406Sgabeblack@google.com getITBPtr(tc)->flushAllSecurity(secure_lookup, target_el); 10557408Sgblack@eecs.umich.edu return; 105610037SARM gem5 Developers // TLBI all entries, EL0&1, data side 10577408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 105810037SARM gem5 Developers assert32(tc); 105910037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 106010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 106110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 106212406Sgabeblack@google.com getDTBPtr(tc)->flushAllSecurity(secure_lookup, target_el); 10637408Sgblack@eecs.umich.edu return; 106410037SARM gem5 Developers // TLBI based on VA, EL0&1 inner sharable (ignored) 106512576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAL: 106612576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALIS: 106712576Sgiacomo.travaglini@arm.com // mcr tlbimval(is) is invalidating all matching entries 106812576Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 106912576Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 107012576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVA: 10717408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 107210037SARM gem5 Developers assert32(tc); 107310037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 107410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 107510037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 10768284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 10778284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 10788284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 107912406Sgabeblack@google.com getITBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12), 108010037SARM gem5 Developers bits(newVal, 7,0), 108110037SARM gem5 Developers secure_lookup, target_el); 108212406Sgabeblack@google.com getDTBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12), 108310037SARM gem5 Developers bits(newVal, 7,0), 108410037SARM gem5 Developers secure_lookup, target_el); 10858887Sgeoffrey.blake@arm.com 10868887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 10878733Sgeoffrey.blake@arm.com if (checker) { 108812406Sgabeblack@google.com getITBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12), 108910037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 109012406Sgabeblack@google.com getDTBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12), 109110037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 10928733Sgeoffrey.blake@arm.com } 10938284SAli.Saidi@ARM.com } 10947408Sgblack@eecs.umich.edu return; 109510037SARM gem5 Developers // TLBI by ASID, EL0&1, inner sharable 10967408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 10977408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 109810037SARM gem5 Developers assert32(tc); 109910037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 110010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 110110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 11028284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 11038284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 11048284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 110512406Sgabeblack@google.com getITBPtr(oc)->flushAsid(bits(newVal, 7,0), 110610037SARM gem5 Developers secure_lookup, target_el); 110712406Sgabeblack@google.com getDTBPtr(oc)->flushAsid(bits(newVal, 7,0), 110810037SARM gem5 Developers secure_lookup, target_el); 11098887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 11108733Sgeoffrey.blake@arm.com if (checker) { 111112406Sgabeblack@google.com getITBPtr(checker)->flushAsid(bits(newVal, 7,0), 111210037SARM gem5 Developers secure_lookup, target_el); 111312406Sgabeblack@google.com getDTBPtr(checker)->flushAsid(bits(newVal, 7,0), 111410037SARM gem5 Developers secure_lookup, target_el); 11158733Sgeoffrey.blake@arm.com } 11168284SAli.Saidi@ARM.com } 11177408Sgblack@eecs.umich.edu return; 111810037SARM gem5 Developers // TLBI by address, EL0&1, inner sharable (ignored) 111912576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAAL: 112012576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAALIS: 112112576Sgiacomo.travaglini@arm.com // mcr tlbimvaal(is) is invalidating all matching entries 112212576Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 112312576Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 112412576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAA: 11257408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 112610037SARM gem5 Developers assert32(tc); 112710037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 112810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 112910037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 113010037SARM gem5 Developers hyp = 0; 113110037SARM gem5 Developers tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 113210037SARM gem5 Developers return; 113310037SARM gem5 Developers // TLBI by address, EL2, hypervisor mode 113412576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALH: 113512576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALHIS: 113612576Sgiacomo.travaglini@arm.com // mcr tlbimvalh(is) is invalidating all matching entries 113712576Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 113812576Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 113910037SARM gem5 Developers case MISCREG_TLBIMVAH: 114010037SARM gem5 Developers case MISCREG_TLBIMVAHIS: 114110037SARM gem5 Developers assert32(tc); 114210037SARM gem5 Developers target_el = 1; // aarch32, use hyp bit 114310037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 114410037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 114510037SARM gem5 Developers hyp = 1; 114610037SARM gem5 Developers tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 114710037SARM gem5 Developers return; 114812577Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2L: 114912577Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2LIS: 115012577Sgiacomo.travaglini@arm.com // mcr tlbiipas2l(is) is invalidating all matching entries 115112577Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 115212577Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 115312577Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2: 115412577Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2IS: 115512577Sgiacomo.travaglini@arm.com assert32(tc); 115612577Sgiacomo.travaglini@arm.com target_el = 1; // EL 0 and 1 are handled together 115712577Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 115812577Sgiacomo.travaglini@arm.com secure_lookup = haveSecurity && !scr.ns; 115912577Sgiacomo.travaglini@arm.com tlbiIPA(tc, newVal, secure_lookup, target_el); 116012577Sgiacomo.travaglini@arm.com return; 116110037SARM gem5 Developers // TLBI by address and asid, EL0&1, instruction side only 116210037SARM gem5 Developers case MISCREG_ITLBIMVA: 116310037SARM gem5 Developers assert32(tc); 116410037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 116510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 116610037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 116712406Sgabeblack@google.com getITBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12), 116810037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 116910037SARM gem5 Developers return; 117010037SARM gem5 Developers // TLBI by address and asid, EL0&1, data side only 117110037SARM gem5 Developers case MISCREG_DTLBIMVA: 117210037SARM gem5 Developers assert32(tc); 117310037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 117410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 117510037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 117612406Sgabeblack@google.com getDTBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12), 117710037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 117810037SARM gem5 Developers return; 117910037SARM gem5 Developers // TLBI by ASID, EL0&1, instrution side only 118010037SARM gem5 Developers case MISCREG_ITLBIASID: 118110037SARM gem5 Developers assert32(tc); 118210037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 118310037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 118410037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 118512406Sgabeblack@google.com getITBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup, 118610037SARM gem5 Developers target_el); 118710037SARM gem5 Developers return; 118810037SARM gem5 Developers // TLBI by ASID EL0&1 data size only 118910037SARM gem5 Developers case MISCREG_DTLBIASID: 119010037SARM gem5 Developers assert32(tc); 119110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 119210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 119310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 119412406Sgabeblack@google.com getDTBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup, 119510037SARM gem5 Developers target_el); 119610037SARM gem5 Developers return; 119710037SARM gem5 Developers // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 119810037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 119910037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 120010037SARM gem5 Developers assert32(tc); 120110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 120210037SARM gem5 Developers hyp = 0; 120310037SARM gem5 Developers tlbiALLN(tc, hyp, target_el); 120410037SARM gem5 Developers return; 120510037SARM gem5 Developers // TLBI all entries, EL2, hyp, 120610037SARM gem5 Developers case MISCREG_TLBIALLH: 120710037SARM gem5 Developers case MISCREG_TLBIALLHIS: 120810037SARM gem5 Developers assert32(tc); 120910037SARM gem5 Developers target_el = 1; // aarch32, use hyp bit 121010037SARM gem5 Developers hyp = 1; 121110037SARM gem5 Developers tlbiALLN(tc, hyp, target_el); 121210037SARM gem5 Developers return; 121310037SARM gem5 Developers // AArch64 TLBI: invalidate all entries EL3 121410037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 121510037SARM gem5 Developers case MISCREG_TLBI_ALLE3: 121610037SARM gem5 Developers assert64(tc); 121710037SARM gem5 Developers target_el = 3; 121810037SARM gem5 Developers secure_lookup = true; 121910037SARM gem5 Developers tlbiALL(tc, secure_lookup, target_el); 122010037SARM gem5 Developers return; 122110037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 122210037SARM gem5 Developers // case MISCREG_TLBI_ALLE2IS: 122310037SARM gem5 Developers // case MISCREG_TLBI_ALLE2: 122410037SARM gem5 Developers // TLBI all entries, EL0&1 122510037SARM gem5 Developers case MISCREG_TLBI_ALLE1IS: 122610037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 122710037SARM gem5 Developers // AArch64 TLBI: invalidate all entries, stage 1, current VMID 122810037SARM gem5 Developers case MISCREG_TLBI_VMALLE1IS: 122910037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 123010037SARM gem5 Developers // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 123110037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1IS: 123210037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 123310037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 123410037SARM gem5 Developers assert64(tc); 123510037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 123610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 123710037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 123810037SARM gem5 Developers tlbiALL(tc, secure_lookup, target_el); 123910037SARM gem5 Developers return; 124010037SARM gem5 Developers // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 124110037SARM gem5 Developers // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 124210037SARM gem5 Developers // from the last level of translation table walks 124310037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 124410037SARM gem5 Developers // TLBI all entries, EL0&1 124510037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 124610037SARM gem5 Developers case MISCREG_TLBI_VAE3_Xt: 124710037SARM gem5 Developers // TLBI by VA, EL3 regime stage 1, last level walk 124810037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 124910037SARM gem5 Developers case MISCREG_TLBI_VALE3_Xt: 125010037SARM gem5 Developers assert64(tc); 125110037SARM gem5 Developers target_el = 3; 125210037SARM gem5 Developers asid = 0xbeef; // does not matter, tlbi is global 125310037SARM gem5 Developers secure_lookup = true; 125410037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 125510037SARM gem5 Developers return; 125610037SARM gem5 Developers // TLBI by VA, EL2 125710037SARM gem5 Developers case MISCREG_TLBI_VAE2IS_Xt: 125810037SARM gem5 Developers case MISCREG_TLBI_VAE2_Xt: 125910037SARM gem5 Developers // TLBI by VA, EL2, stage1 last level walk 126010037SARM gem5 Developers case MISCREG_TLBI_VALE2IS_Xt: 126110037SARM gem5 Developers case MISCREG_TLBI_VALE2_Xt: 126210037SARM gem5 Developers assert64(tc); 126310037SARM gem5 Developers target_el = 2; 126410037SARM gem5 Developers asid = 0xbeef; // does not matter, tlbi is global 126510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 126610037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 126710037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 126810037SARM gem5 Developers return; 126910037SARM gem5 Developers // TLBI by VA EL1 & 0, stage1, ASID, current VMID 127010037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 127110037SARM gem5 Developers case MISCREG_TLBI_VAE1_Xt: 127210037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 127310037SARM gem5 Developers case MISCREG_TLBI_VALE1_Xt: 127410037SARM gem5 Developers assert64(tc); 127510037SARM gem5 Developers asid = bits(newVal, 63, 48); 127610037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 127710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 127810037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 127910037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 128010037SARM gem5 Developers return; 128110037SARM gem5 Developers // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 128210037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 128310037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 128410037SARM gem5 Developers case MISCREG_TLBI_ASIDE1_Xt: 128510037SARM gem5 Developers assert64(tc); 128610037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 128710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 128810037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 12898284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 12908284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 12918284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 129210037SARM gem5 Developers asid = bits(newVal, 63, 48); 129310709SAndreas.Sandberg@ARM.com if (!haveLargeAsid64) 129410037SARM gem5 Developers asid &= mask(8); 129512406Sgabeblack@google.com getITBPtr(oc)->flushAsid(asid, secure_lookup, target_el); 129612406Sgabeblack@google.com getDTBPtr(oc)->flushAsid(asid, secure_lookup, target_el); 129710037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 129810037SARM gem5 Developers if (checker) { 129912406Sgabeblack@google.com getITBPtr(checker)->flushAsid(asid, 130010037SARM gem5 Developers secure_lookup, target_el); 130112406Sgabeblack@google.com getDTBPtr(checker)->flushAsid(asid, 130210037SARM gem5 Developers secure_lookup, target_el); 130310037SARM gem5 Developers } 130410037SARM gem5 Developers } 130510037SARM gem5 Developers return; 130610037SARM gem5 Developers // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 130710037SARM gem5 Developers // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 130810037SARM gem5 Developers // entries from the last level of translation table walks 130910037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 131010037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 131110037SARM gem5 Developers case MISCREG_TLBI_VAAE1_Xt: 131210037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 131310037SARM gem5 Developers case MISCREG_TLBI_VAALE1_Xt: 131410037SARM gem5 Developers assert64(tc); 131510037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 131610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 131710037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 131810037SARM gem5 Developers sys = tc->getSystemPtr(); 131910037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 132010037SARM gem5 Developers // @todo: extra controls on TLBI broadcast? 132110037SARM gem5 Developers oc = sys->getThreadContext(x); 132210037SARM gem5 Developers Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 132312406Sgabeblack@google.com getITBPtr(oc)->flushMva(va, 132410037SARM gem5 Developers secure_lookup, false, target_el); 132512406Sgabeblack@google.com getDTBPtr(oc)->flushMva(va, 132610037SARM gem5 Developers secure_lookup, false, target_el); 13278887Sgeoffrey.blake@arm.com 13288887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 13298733Sgeoffrey.blake@arm.com if (checker) { 133012406Sgabeblack@google.com getITBPtr(checker)->flushMva(va, 133110037SARM gem5 Developers secure_lookup, false, target_el); 133212406Sgabeblack@google.com getDTBPtr(checker)->flushMva(va, 133310037SARM gem5 Developers secure_lookup, false, target_el); 13348733Sgeoffrey.blake@arm.com } 13358284SAli.Saidi@ARM.com } 13367408Sgblack@eecs.umich.edu return; 133710037SARM gem5 Developers // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 133810037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1IS_Xt: 133910037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1_Xt: 134010037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1IS_Xt: 134110037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1_Xt: 134210037SARM gem5 Developers assert64(tc); 134311584SDylan.Johnson@ARM.com target_el = 1; // EL 0 and 1 are handled together 134411584SDylan.Johnson@ARM.com scr = readMiscReg(MISCREG_SCR, tc); 134511584SDylan.Johnson@ARM.com secure_lookup = haveSecurity && !scr.ns; 134612577Sgiacomo.travaglini@arm.com tlbiIPA(tc, newVal, secure_lookup, target_el); 13477405SAli.Saidi@ARM.com return; 13487583SAli.Saidi@arm.com case MISCREG_ACTLR: 13497583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 13507583SAli.Saidi@arm.com break; 135110461SAndreas.Sandberg@ARM.com 135210461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 135310461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 135410461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 135510461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 135610461SAndreas.Sandberg@ARM.com pmu->setMiscReg(misc_reg, newVal); 13577583SAli.Saidi@arm.com break; 135810461SAndreas.Sandberg@ARM.com 135910461SAndreas.Sandberg@ARM.com 136010037SARM gem5 Developers case MISCREG_HSTR: // TJDBX, now redifined to be RES0 136110037SARM gem5 Developers { 136210037SARM gem5 Developers HSTR hstrMask = 0; 136310037SARM gem5 Developers hstrMask.tjdbx = 1; 136410037SARM gem5 Developers newVal &= ~((uint32_t) hstrMask); 136510037SARM gem5 Developers break; 136610037SARM gem5 Developers } 136710037SARM gem5 Developers case MISCREG_HCPTR: 136810037SARM gem5 Developers { 136910037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 137010037SARM gem5 Developers // HCPTR is RAO/WI. Same applies to NSASEDIS 137110037SARM gem5 Developers secure_lookup = haveSecurity && 137210037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 137310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 137410037SARM gem5 Developers if (!secure_lookup) { 137510037SARM gem5 Developers MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 137610037SARM gem5 Developers MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 137710037SARM gem5 Developers newVal = (newVal & ~mask) | (oldValue & mask); 137810037SARM gem5 Developers } 137910037SARM gem5 Developers break; 138010037SARM gem5 Developers } 138110037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 138210037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 138310037SARM gem5 Developers break; 138410037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 138510037SARM gem5 Developers misc_reg = MISCREG_IFAR_S; 138610037SARM gem5 Developers break; 138710037SARM gem5 Developers case MISCREG_ATS1CPR: 138810037SARM gem5 Developers case MISCREG_ATS1CPW: 138910037SARM gem5 Developers case MISCREG_ATS1CUR: 139010037SARM gem5 Developers case MISCREG_ATS1CUW: 139110037SARM gem5 Developers case MISCREG_ATS12NSOPR: 139210037SARM gem5 Developers case MISCREG_ATS12NSOPW: 139310037SARM gem5 Developers case MISCREG_ATS12NSOUR: 139410037SARM gem5 Developers case MISCREG_ATS12NSOUW: 139510037SARM gem5 Developers case MISCREG_ATS1HR: 139610037SARM gem5 Developers case MISCREG_ATS1HW: 13977436Sdam.sunwoo@arm.com { 139811608Snikos.nikoleris@arm.com Request::Flags flags = 0; 139910037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 140010037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 14017436Sdam.sunwoo@arm.com Fault fault; 14027436Sdam.sunwoo@arm.com switch(misc_reg) { 140310037SARM gem5 Developers case MISCREG_ATS1CPR: 140410037SARM gem5 Developers flags = TLB::MustBeOne; 140510037SARM gem5 Developers tranType = TLB::S1CTran; 140610037SARM gem5 Developers mode = BaseTLB::Read; 140710037SARM gem5 Developers break; 140810037SARM gem5 Developers case MISCREG_ATS1CPW: 140910037SARM gem5 Developers flags = TLB::MustBeOne; 141010037SARM gem5 Developers tranType = TLB::S1CTran; 141110037SARM gem5 Developers mode = BaseTLB::Write; 141210037SARM gem5 Developers break; 141310037SARM gem5 Developers case MISCREG_ATS1CUR: 141410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 141510037SARM gem5 Developers tranType = TLB::S1CTran; 141610037SARM gem5 Developers mode = BaseTLB::Read; 141710037SARM gem5 Developers break; 141810037SARM gem5 Developers case MISCREG_ATS1CUW: 141910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 142010037SARM gem5 Developers tranType = TLB::S1CTran; 142110037SARM gem5 Developers mode = BaseTLB::Write; 142210037SARM gem5 Developers break; 142310037SARM gem5 Developers case MISCREG_ATS12NSOPR: 142410037SARM gem5 Developers if (!haveSecurity) 142510037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 142610037SARM gem5 Developers flags = TLB::MustBeOne; 142710037SARM gem5 Developers tranType = TLB::S1S2NsTran; 142810037SARM gem5 Developers mode = BaseTLB::Read; 142910037SARM gem5 Developers break; 143010037SARM gem5 Developers case MISCREG_ATS12NSOPW: 143110037SARM gem5 Developers if (!haveSecurity) 143210037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPW"); 143310037SARM gem5 Developers flags = TLB::MustBeOne; 143410037SARM gem5 Developers tranType = TLB::S1S2NsTran; 143510037SARM gem5 Developers mode = BaseTLB::Write; 143610037SARM gem5 Developers break; 143710037SARM gem5 Developers case MISCREG_ATS12NSOUR: 143810037SARM gem5 Developers if (!haveSecurity) 143910037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 144010037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 144110037SARM gem5 Developers tranType = TLB::S1S2NsTran; 144210037SARM gem5 Developers mode = BaseTLB::Read; 144310037SARM gem5 Developers break; 144410037SARM gem5 Developers case MISCREG_ATS12NSOUW: 144510037SARM gem5 Developers if (!haveSecurity) 144610037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 144710037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 144810037SARM gem5 Developers tranType = TLB::S1S2NsTran; 144910037SARM gem5 Developers mode = BaseTLB::Write; 145010037SARM gem5 Developers break; 145110037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 145210037SARM gem5 Developers flags = TLB::MustBeOne; 145310037SARM gem5 Developers tranType = TLB::HypMode; 145410037SARM gem5 Developers mode = BaseTLB::Read; 145510037SARM gem5 Developers break; 145610037SARM gem5 Developers case MISCREG_ATS1HW: 145710037SARM gem5 Developers flags = TLB::MustBeOne; 145810037SARM gem5 Developers tranType = TLB::HypMode; 145910037SARM gem5 Developers mode = BaseTLB::Write; 146010037SARM gem5 Developers break; 14617436Sdam.sunwoo@arm.com } 146210037SARM gem5 Developers // If we're in timing mode then doing the translation in 146310037SARM gem5 Developers // functional mode then we're slightly distorting performance 146410037SARM gem5 Developers // results obtained from simulations. The translation should be 146510037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 146610037SARM gem5 Developers // can't be an atomic translation because that causes problems 146710037SARM gem5 Developers // with unexpected atomic snoop requests. 146810037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 146911560Sandreas.sandberg@arm.com Request req(0, val, 0, flags, Request::funcMasterId, 147011435Smitch.hayenga@arm.com tc->pcState().pc(), tc->contextId()); 147112406Sgabeblack@google.com fault = getDTBPtr(tc)->translateFunctional( 147212406Sgabeblack@google.com &req, tc, mode, tranType); 147310037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 147410037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 147510037SARM gem5 Developers 147610037SARM gem5 Developers MiscReg newVal; 14777436Sdam.sunwoo@arm.com if (fault == NoFault) { 147810653Sandreas.hansson@arm.com Addr paddr = req.getPaddr(); 147910037SARM gem5 Developers if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 148010037SARM gem5 Developers ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 148110037SARM gem5 Developers newVal = (paddr & mask(39, 12)) | 148212406Sgabeblack@google.com (getDTBPtr(tc)->getAttr()); 148310037SARM gem5 Developers } else { 148410037SARM gem5 Developers newVal = (paddr & 0xfffff000) | 148512406Sgabeblack@google.com (getDTBPtr(tc)->getAttr()); 148610037SARM gem5 Developers } 14877436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 14887436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 148910037SARM gem5 Developers val, newVal); 149010037SARM gem5 Developers } else { 149112524Sgiacomo.travaglini@arm.com ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 149212570Sgiacomo.travaglini@arm.com armFault->update(tc); 149310037SARM gem5 Developers // Set fault bit and FSR 149410037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 149510037SARM gem5 Developers 149610037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 149710037SARM gem5 Developers if (newVal) { 149810037SARM gem5 Developers // LPAE - rearange fault status 149910037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 150010037SARM gem5 Developers } else { 150110037SARM gem5 Developers // VMSA - rearange fault status 150210037SARM gem5 Developers newVal |= ((fsr >> 0) & 0xf) << 1; 150310037SARM gem5 Developers newVal |= ((fsr >> 10) & 0x1) << 5; 150410037SARM gem5 Developers newVal |= ((fsr >> 12) & 0x1) << 6; 150510037SARM gem5 Developers } 150610037SARM gem5 Developers newVal |= 0x1; // F bit 150710037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 150810037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 150910037SARM gem5 Developers DPRINTF(MiscRegs, 151010037SARM gem5 Developers "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 151110037SARM gem5 Developers val, fsr, newVal); 15127436Sdam.sunwoo@arm.com } 151310037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 15147436Sdam.sunwoo@arm.com return; 15157436Sdam.sunwoo@arm.com } 151610037SARM gem5 Developers case MISCREG_TTBCR: 151710037SARM gem5 Developers { 151810037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 151910037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 152010037SARM gem5 Developers TTBCR ttbcrMask = 0; 152110037SARM gem5 Developers TTBCR ttbcrNew = newVal; 152210037SARM gem5 Developers 152310037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 152410037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 152510037SARM gem5 Developers if (haveSecurity) { 152610037SARM gem5 Developers ttbcrMask.pd0 = ones; 152710037SARM gem5 Developers ttbcrMask.pd1 = ones; 152810037SARM gem5 Developers } 152910037SARM gem5 Developers ttbcrMask.epd0 = ones; 153010037SARM gem5 Developers ttbcrMask.irgn0 = ones; 153110037SARM gem5 Developers ttbcrMask.orgn0 = ones; 153210037SARM gem5 Developers ttbcrMask.sh0 = ones; 153310037SARM gem5 Developers ttbcrMask.ps = ones; // T1SZ 153410037SARM gem5 Developers ttbcrMask.a1 = ones; 153510037SARM gem5 Developers ttbcrMask.epd1 = ones; 153610037SARM gem5 Developers ttbcrMask.irgn1 = ones; 153710037SARM gem5 Developers ttbcrMask.orgn1 = ones; 153810037SARM gem5 Developers ttbcrMask.sh1 = ones; 153910037SARM gem5 Developers if (haveLPAE) 154010037SARM gem5 Developers ttbcrMask.eae = ones; 154110037SARM gem5 Developers 154210037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 154310037SARM gem5 Developers newVal = newVal & ttbcrMask; 154410037SARM gem5 Developers } else { 154510037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 154610037SARM gem5 Developers } 154710037SARM gem5 Developers } 154812392Sjason@lowepower.com M5_FALLTHROUGH; 154910037SARM gem5 Developers case MISCREG_TTBR0: 155010037SARM gem5 Developers case MISCREG_TTBR1: 155110037SARM gem5 Developers { 155210037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 155310037SARM gem5 Developers if (haveLPAE) { 155410037SARM gem5 Developers if (ttbcr.eae) { 155510037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 155610037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 155710037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 155810037SARM gem5 Developers newVal = (newVal & (~ttbrMask)); 155910037SARM gem5 Developers } 156010037SARM gem5 Developers } 156110037SARM gem5 Developers } 156212392Sjason@lowepower.com M5_FALLTHROUGH; 156310508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL1: 156410508SAli.Saidi@ARM.com { 156512406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 156612406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 156710508SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 156810508SAli.Saidi@ARM.com } 156912392Sjason@lowepower.com M5_FALLTHROUGH; 15707749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 15717749SAli.Saidi@ARM.com case MISCREG_PRRR: 15727749SAli.Saidi@ARM.com case MISCREG_NMRR: 157310037SARM gem5 Developers case MISCREG_MAIR0: 157410037SARM gem5 Developers case MISCREG_MAIR1: 15757749SAli.Saidi@ARM.com case MISCREG_DACR: 157610037SARM gem5 Developers case MISCREG_VTTBR: 157710037SARM gem5 Developers case MISCREG_SCR_EL3: 157811575SDylan.Johnson@ARM.com case MISCREG_HCR_EL2: 157910037SARM gem5 Developers case MISCREG_TCR_EL1: 158010037SARM gem5 Developers case MISCREG_TCR_EL2: 158110037SARM gem5 Developers case MISCREG_TCR_EL3: 158210508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL2: 158310508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL3: 158411573SDylan.Johnson@ARM.com case MISCREG_HSCTLR: 158510037SARM gem5 Developers case MISCREG_TTBR0_EL1: 158610037SARM gem5 Developers case MISCREG_TTBR1_EL1: 158710037SARM gem5 Developers case MISCREG_TTBR0_EL2: 158810037SARM gem5 Developers case MISCREG_TTBR0_EL3: 158912406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 159012406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 15917749SAli.Saidi@ARM.com break; 159210037SARM gem5 Developers case MISCREG_NZCV: 159310037SARM gem5 Developers { 159410037SARM gem5 Developers CPSR cpsr = val; 159510037SARM gem5 Developers 159610338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_NZ, cpsr.nz); 159710338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_C, cpsr.c); 159810338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_V, cpsr.v); 159910037SARM gem5 Developers } 160010037SARM gem5 Developers break; 160110037SARM gem5 Developers case MISCREG_DAIF: 160210037SARM gem5 Developers { 160310037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 160410037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 160510037SARM gem5 Developers newVal = cpsr; 160610037SARM gem5 Developers misc_reg = MISCREG_CPSR; 160710037SARM gem5 Developers } 160810037SARM gem5 Developers break; 160910037SARM gem5 Developers case MISCREG_SP_EL0: 161010037SARM gem5 Developers tc->setIntReg(INTREG_SP0, newVal); 161110037SARM gem5 Developers break; 161210037SARM gem5 Developers case MISCREG_SP_EL1: 161310037SARM gem5 Developers tc->setIntReg(INTREG_SP1, newVal); 161410037SARM gem5 Developers break; 161510037SARM gem5 Developers case MISCREG_SP_EL2: 161610037SARM gem5 Developers tc->setIntReg(INTREG_SP2, newVal); 161710037SARM gem5 Developers break; 161810037SARM gem5 Developers case MISCREG_SPSEL: 161910037SARM gem5 Developers { 162010037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 162110037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 162210037SARM gem5 Developers newVal = cpsr; 162310037SARM gem5 Developers misc_reg = MISCREG_CPSR; 162410037SARM gem5 Developers } 162510037SARM gem5 Developers break; 162610037SARM gem5 Developers case MISCREG_CURRENTEL: 162710037SARM gem5 Developers { 162810037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 162910037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 163010037SARM gem5 Developers newVal = cpsr; 163110037SARM gem5 Developers misc_reg = MISCREG_CPSR; 163210037SARM gem5 Developers } 163310037SARM gem5 Developers break; 163410037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 163510037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 163610037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 163710037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 163810037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 163910037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 164010037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 164110037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 164210037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 164310037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 164410037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 164510037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 164610037SARM gem5 Developers { 164710037SARM gem5 Developers RequestPtr req = new Request; 164811608Snikos.nikoleris@arm.com Request::Flags flags = 0; 164910037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 165010037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 165110037SARM gem5 Developers Fault fault; 165210037SARM gem5 Developers switch(misc_reg) { 165310037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 165410037SARM gem5 Developers flags = TLB::MustBeOne; 165511577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 165610037SARM gem5 Developers mode = BaseTLB::Read; 165710037SARM gem5 Developers break; 165810037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 165910037SARM gem5 Developers flags = TLB::MustBeOne; 166011577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 166110037SARM gem5 Developers mode = BaseTLB::Write; 166210037SARM gem5 Developers break; 166310037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 166410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 166511577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 166610037SARM gem5 Developers mode = BaseTLB::Read; 166710037SARM gem5 Developers break; 166810037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 166910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 167011577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 167110037SARM gem5 Developers mode = BaseTLB::Write; 167210037SARM gem5 Developers break; 167310037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 167410037SARM gem5 Developers flags = TLB::MustBeOne; 167511577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 167610037SARM gem5 Developers mode = BaseTLB::Read; 167710037SARM gem5 Developers break; 167810037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 167910037SARM gem5 Developers flags = TLB::MustBeOne; 168011577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 168110037SARM gem5 Developers mode = BaseTLB::Write; 168210037SARM gem5 Developers break; 168310037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 168410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 168511577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 168610037SARM gem5 Developers mode = BaseTLB::Read; 168710037SARM gem5 Developers break; 168810037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 168910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 169011577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 169110037SARM gem5 Developers mode = BaseTLB::Write; 169210037SARM gem5 Developers break; 169310037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 169410037SARM gem5 Developers flags = TLB::MustBeOne; 169511577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 169610037SARM gem5 Developers mode = BaseTLB::Read; 169710037SARM gem5 Developers break; 169810037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 169910037SARM gem5 Developers flags = TLB::MustBeOne; 170011577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 170110037SARM gem5 Developers mode = BaseTLB::Write; 170210037SARM gem5 Developers break; 170310037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 170410037SARM gem5 Developers flags = TLB::MustBeOne; 170511577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 170610037SARM gem5 Developers mode = BaseTLB::Read; 170710037SARM gem5 Developers break; 170810037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 170910037SARM gem5 Developers flags = TLB::MustBeOne; 171011577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 171110037SARM gem5 Developers mode = BaseTLB::Write; 171210037SARM gem5 Developers break; 171310037SARM gem5 Developers } 171410037SARM gem5 Developers // If we're in timing mode then doing the translation in 171510037SARM gem5 Developers // functional mode then we're slightly distorting performance 171610037SARM gem5 Developers // results obtained from simulations. The translation should be 171710037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 171810037SARM gem5 Developers // can't be an atomic translation because that causes problems 171910037SARM gem5 Developers // with unexpected atomic snoop requests. 172010037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 172111560Sandreas.sandberg@arm.com req->setVirt(0, val, 0, flags, Request::funcMasterId, 172210037SARM gem5 Developers tc->pcState().pc()); 172311435Smitch.hayenga@arm.com req->setContext(tc->contextId()); 172412406Sgabeblack@google.com fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 172512406Sgabeblack@google.com tranType); 172610037SARM gem5 Developers 172710037SARM gem5 Developers MiscReg newVal; 172810037SARM gem5 Developers if (fault == NoFault) { 172910037SARM gem5 Developers Addr paddr = req->getPaddr(); 173012406Sgabeblack@google.com uint64_t attr = getDTBPtr(tc)->getAttr(); 173110037SARM gem5 Developers uint64_t attr1 = attr >> 56; 173210037SARM gem5 Developers if (!attr1 || attr1 ==0x44) { 173310037SARM gem5 Developers attr |= 0x100; 173410037SARM gem5 Developers attr &= ~ uint64_t(0x80); 173510037SARM gem5 Developers } 173610037SARM gem5 Developers newVal = (paddr & mask(47, 12)) | attr; 173710037SARM gem5 Developers DPRINTF(MiscRegs, 173810037SARM gem5 Developers "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 173910037SARM gem5 Developers val, newVal); 174010037SARM gem5 Developers } else { 174112524Sgiacomo.travaglini@arm.com ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 174212570Sgiacomo.travaglini@arm.com armFault->update(tc); 174310037SARM gem5 Developers // Set fault bit and FSR 174410037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 174510037SARM gem5 Developers 174611577SDylan.Johnson@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 174711577SDylan.Johnson@ARM.com if (cpsr.width) { // AArch32 174811577SDylan.Johnson@ARM.com newVal = ((fsr >> 9) & 1) << 11; 174911577SDylan.Johnson@ARM.com // rearrange fault status 175011577SDylan.Johnson@ARM.com newVal |= ((fsr >> 0) & 0x3f) << 1; 175111577SDylan.Johnson@ARM.com newVal |= 0x1; // F bit 175211577SDylan.Johnson@ARM.com newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 175311577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 0x200 : 0; 175411577SDylan.Johnson@ARM.com } else { // AArch64 175511577SDylan.Johnson@ARM.com newVal = 1; // F bit 175611577SDylan.Johnson@ARM.com newVal |= fsr << 1; // FST 175711577SDylan.Johnson@ARM.com // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 175811577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 175911577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 176011577SDylan.Johnson@ARM.com newVal |= 1 << 11; // RES1 176111577SDylan.Johnson@ARM.com } 176210037SARM gem5 Developers DPRINTF(MiscRegs, 176310037SARM gem5 Developers "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 176410037SARM gem5 Developers val, fsr, newVal); 176510037SARM gem5 Developers } 176610037SARM gem5 Developers delete req; 176710037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 176810037SARM gem5 Developers return; 176910037SARM gem5 Developers } 177010037SARM gem5 Developers case MISCREG_SPSR_EL3: 177110037SARM gem5 Developers case MISCREG_SPSR_EL2: 177210037SARM gem5 Developers case MISCREG_SPSR_EL1: 177310037SARM gem5 Developers // Force bits 23:21 to 0 177410037SARM gem5 Developers newVal = val & ~(0x7 << 21); 177510037SARM gem5 Developers break; 17768549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 17778549Sdaniel.johnson@arm.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 17788549Sdaniel.johnson@arm.com miscRegName[misc_reg], uint32_t(val)); 177910037SARM gem5 Developers break; 178010037SARM gem5 Developers 178110037SARM gem5 Developers // Generic Timer registers 178210844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 178310844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 178410844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 178510844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 178610844Sandreas.sandberg@arm.com getGenericTimer(tc).setMiscReg(misc_reg, newVal); 178710037SARM gem5 Developers break; 17887405SAli.Saidi@ARM.com } 17897405SAli.Saidi@ARM.com } 17907405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 17917405SAli.Saidi@ARM.com} 17927405SAli.Saidi@ARM.com 179310037SARM gem5 Developersvoid 179410709SAndreas.Sandberg@ARM.comISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 179510709SAndreas.Sandberg@ARM.com bool secure_lookup, uint8_t target_el) 179610037SARM gem5 Developers{ 179710709SAndreas.Sandberg@ARM.com if (!haveLargeAsid64) 179810037SARM gem5 Developers asid &= mask(8); 179910037SARM gem5 Developers Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 180010037SARM gem5 Developers System *sys = tc->getSystemPtr(); 180110037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 180210037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 180312406Sgabeblack@google.com getITBPtr(oc)->flushMvaAsid(va, asid, 180410037SARM gem5 Developers secure_lookup, target_el); 180512406Sgabeblack@google.com getDTBPtr(oc)->flushMvaAsid(va, asid, 180610037SARM gem5 Developers secure_lookup, target_el); 180710037SARM gem5 Developers 180810037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 180910037SARM gem5 Developers if (checker) { 181012406Sgabeblack@google.com getITBPtr(checker)->flushMvaAsid( 181110037SARM gem5 Developers va, asid, secure_lookup, target_el); 181212406Sgabeblack@google.com getDTBPtr(checker)->flushMvaAsid( 181310037SARM gem5 Developers va, asid, secure_lookup, target_el); 181410037SARM gem5 Developers } 181510037SARM gem5 Developers } 181610037SARM gem5 Developers} 181710037SARM gem5 Developers 181810037SARM gem5 Developersvoid 181910037SARM gem5 DevelopersISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 182010037SARM gem5 Developers{ 182110037SARM gem5 Developers System *sys = tc->getSystemPtr(); 182210037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 182310037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 182412406Sgabeblack@google.com getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el); 182512406Sgabeblack@google.com getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el); 182610037SARM gem5 Developers 182710037SARM gem5 Developers // If CheckerCPU is connected, need to notify it of a flush 182810037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 182910037SARM gem5 Developers if (checker) { 183012406Sgabeblack@google.com getITBPtr(checker)->flushAllSecurity(secure_lookup, 183110037SARM gem5 Developers target_el); 183212406Sgabeblack@google.com getDTBPtr(checker)->flushAllSecurity(secure_lookup, 183310037SARM gem5 Developers target_el); 183410037SARM gem5 Developers } 183510037SARM gem5 Developers } 183610037SARM gem5 Developers} 183710037SARM gem5 Developers 183810037SARM gem5 Developersvoid 183910037SARM gem5 DevelopersISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 184010037SARM gem5 Developers{ 184110037SARM gem5 Developers System *sys = tc->getSystemPtr(); 184210037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 184310037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 184412406Sgabeblack@google.com getITBPtr(oc)->flushAllNs(hyp, target_el); 184512406Sgabeblack@google.com getDTBPtr(oc)->flushAllNs(hyp, target_el); 184610037SARM gem5 Developers 184710037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 184810037SARM gem5 Developers if (checker) { 184912406Sgabeblack@google.com getITBPtr(checker)->flushAllNs(hyp, target_el); 185012406Sgabeblack@google.com getDTBPtr(checker)->flushAllNs(hyp, target_el); 185110037SARM gem5 Developers } 185210037SARM gem5 Developers } 185310037SARM gem5 Developers} 185410037SARM gem5 Developers 185510037SARM gem5 Developersvoid 185610037SARM gem5 DevelopersISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 185710037SARM gem5 Developers uint8_t target_el) 185810037SARM gem5 Developers{ 185910037SARM gem5 Developers System *sys = tc->getSystemPtr(); 186010037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 186110037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 186212406Sgabeblack@google.com getITBPtr(oc)->flushMva(mbits(newVal, 31,12), 186310037SARM gem5 Developers secure_lookup, hyp, target_el); 186412406Sgabeblack@google.com getDTBPtr(oc)->flushMva(mbits(newVal, 31,12), 186510037SARM gem5 Developers secure_lookup, hyp, target_el); 186610037SARM gem5 Developers 186710037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 186810037SARM gem5 Developers if (checker) { 186912406Sgabeblack@google.com getITBPtr(checker)->flushMva(mbits(newVal, 31,12), 187010037SARM gem5 Developers secure_lookup, hyp, target_el); 187112406Sgabeblack@google.com getDTBPtr(checker)->flushMva(mbits(newVal, 31,12), 187210037SARM gem5 Developers secure_lookup, hyp, target_el); 187310037SARM gem5 Developers } 187410037SARM gem5 Developers } 187510037SARM gem5 Developers} 187610037SARM gem5 Developers 187712577Sgiacomo.travaglini@arm.comvoid 187812577Sgiacomo.travaglini@arm.comISA::tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, 187912577Sgiacomo.travaglini@arm.com uint8_t target_el) 188012577Sgiacomo.travaglini@arm.com{ 188112577Sgiacomo.travaglini@arm.com System *sys = tc->getSystemPtr(); 188212577Sgiacomo.travaglini@arm.com for (auto x = 0; x < sys->numContexts(); x++) { 188312577Sgiacomo.travaglini@arm.com tc = sys->getThreadContext(x); 188412577Sgiacomo.travaglini@arm.com Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; 188512577Sgiacomo.travaglini@arm.com getITBPtr(tc)->flushIpaVmid(ipa, 188612577Sgiacomo.travaglini@arm.com secure_lookup, false, target_el); 188712577Sgiacomo.travaglini@arm.com getDTBPtr(tc)->flushIpaVmid(ipa, 188812577Sgiacomo.travaglini@arm.com secure_lookup, false, target_el); 188912577Sgiacomo.travaglini@arm.com 189012577Sgiacomo.travaglini@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 189112577Sgiacomo.travaglini@arm.com if (checker) { 189212577Sgiacomo.travaglini@arm.com getITBPtr(checker)->flushIpaVmid(ipa, 189312577Sgiacomo.travaglini@arm.com secure_lookup, false, target_el); 189412577Sgiacomo.travaglini@arm.com getDTBPtr(checker)->flushIpaVmid(ipa, 189512577Sgiacomo.travaglini@arm.com secure_lookup, false, target_el); 189612577Sgiacomo.travaglini@arm.com } 189712577Sgiacomo.travaglini@arm.com } 189812577Sgiacomo.travaglini@arm.com} 189912577Sgiacomo.travaglini@arm.com 190010844Sandreas.sandberg@arm.comBaseISADevice & 190110844Sandreas.sandberg@arm.comISA::getGenericTimer(ThreadContext *tc) 190210037SARM gem5 Developers{ 190310844Sandreas.sandberg@arm.com // We only need to create an ISA interface the first time we try 190410844Sandreas.sandberg@arm.com // to access the timer. 190510844Sandreas.sandberg@arm.com if (timer) 190610844Sandreas.sandberg@arm.com return *timer.get(); 190710844Sandreas.sandberg@arm.com 190810844Sandreas.sandberg@arm.com assert(system); 190910844Sandreas.sandberg@arm.com GenericTimer *generic_timer(system->getGenericTimer()); 191010844Sandreas.sandberg@arm.com if (!generic_timer) { 191110844Sandreas.sandberg@arm.com panic("Trying to get a generic timer from a system that hasn't " 191210844Sandreas.sandberg@arm.com "been configured to use a generic timer.\n"); 191310037SARM gem5 Developers } 191410037SARM gem5 Developers 191511150Smitch.hayenga@arm.com timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 191610844Sandreas.sandberg@arm.com return *timer.get(); 191710037SARM gem5 Developers} 191810037SARM gem5 Developers 19197405SAli.Saidi@ARM.com} 19209384SAndreas.Sandberg@arm.com 19219384SAndreas.Sandberg@arm.comArmISA::ISA * 19229384SAndreas.Sandberg@arm.comArmISAParams::create() 19239384SAndreas.Sandberg@arm.com{ 19249384SAndreas.Sandberg@arm.com return new ArmISA::ISA(this); 19259384SAndreas.Sandberg@arm.com} 1926