isa.cc revision 12109
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2010-2016 ARM Limited 36313Sgblack@eecs.umich.edu * All rights reserved 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 66313Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 76313Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 86313Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 96313Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 106313Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 116313Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 126313Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 136313Sgblack@eecs.umich.edu * 146313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 156313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 166313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 176313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 186313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 196313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 206313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 216313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 226313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 236313Sgblack@eecs.umich.edu * this software without specific prior written permission. 246313Sgblack@eecs.umich.edu * 256313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 296313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 306313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 316313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 328229Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336334Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346334Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356334Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366334Sgblack@eecs.umich.edu * 376313Sgblack@eecs.umich.edu * Authors: Gabe Black 388232Snate@binkert.org * Ali Saidi 396313Sgblack@eecs.umich.edu */ 406313Sgblack@eecs.umich.edu 416313Sgblack@eecs.umich.edu#include "arch/arm/isa.hh" 426313Sgblack@eecs.umich.edu 436334Sgblack@eecs.umich.edu#include "arch/arm/pmu.hh" 446334Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 456334Sgblack@eecs.umich.edu#include "cpu/base.hh" 466334Sgblack@eecs.umich.edu#include "cpu/checker/cpu.hh" 476334Sgblack@eecs.umich.edu#include "debug/Arm.hh" 486334Sgblack@eecs.umich.edu#include "debug/MiscRegs.hh" 496334Sgblack@eecs.umich.edu#include "dev/arm/generic_timer.hh" 506334Sgblack@eecs.umich.edu#include "params/ArmISA.hh" 516334Sgblack@eecs.umich.edu#include "sim/faults.hh" 526334Sgblack@eecs.umich.edu#include "sim/stat_control.hh" 536334Sgblack@eecs.umich.edu#include "sim/system.hh" 546334Sgblack@eecs.umich.edu 556334Sgblack@eecs.umich.edunamespace ArmISA 566334Sgblack@eecs.umich.edu{ 576334Sgblack@eecs.umich.edu 586334Sgblack@eecs.umich.edu 596334Sgblack@eecs.umich.edu/** 606334Sgblack@eecs.umich.edu * Some registers alias with others, and therefore need to be translated. 616334Sgblack@eecs.umich.edu * For each entry: 626334Sgblack@eecs.umich.edu * The first value is the misc register that is to be looked up 636334Sgblack@eecs.umich.edu * the second value is the lower part of the translation 646334Sgblack@eecs.umich.edu * the third the upper part 656334Sgblack@eecs.umich.edu * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 666334Sgblack@eecs.umich.edu */ 676334Sgblack@eecs.umich.educonst struct ISA::MiscRegInitializerEntry 686334Sgblack@eecs.umich.edu ISA::MiscRegSwitch[] = { 696334Sgblack@eecs.umich.edu {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}}, 706334Sgblack@eecs.umich.edu {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}}, 716334Sgblack@eecs.umich.edu {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}}, 726334Sgblack@eecs.umich.edu {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}}, 736334Sgblack@eecs.umich.edu {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}}, 746334Sgblack@eecs.umich.edu {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 756334Sgblack@eecs.umich.edu {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}}, 766334Sgblack@eecs.umich.edu {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}}, 776334Sgblack@eecs.umich.edu {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}}, 786334Sgblack@eecs.umich.edu // ESR_EL1 -> DFSR 796334Sgblack@eecs.umich.edu {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 806334Sgblack@eecs.umich.edu {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 816334Sgblack@eecs.umich.edu {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 826334Sgblack@eecs.umich.edu {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 836334Sgblack@eecs.umich.edu {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}}, 846334Sgblack@eecs.umich.edu {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 856334Sgblack@eecs.umich.edu {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}}, 866334Sgblack@eecs.umich.edu {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 876334Sgblack@eecs.umich.edu {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 886334Sgblack@eecs.umich.edu {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 896334Sgblack@eecs.umich.edu {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 908181Sksewell@umich.edu {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 916334Sgblack@eecs.umich.edu {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 928181Sksewell@umich.edu {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 938181Sksewell@umich.edu {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 946334Sgblack@eecs.umich.edu {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 956334Sgblack@eecs.umich.edu {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 966334Sgblack@eecs.umich.edu {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 976334Sgblack@eecs.umich.edu {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}}, 986334Sgblack@eecs.umich.edu {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}}, 996334Sgblack@eecs.umich.edu {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}}, 1006334Sgblack@eecs.umich.edu // RMR_EL1 -> RMR 1016334Sgblack@eecs.umich.edu // RMR_EL2 -> HRMR 1026334Sgblack@eecs.umich.edu {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}}, 1036334Sgblack@eecs.umich.edu {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}, 1046334Sgblack@eecs.umich.edu {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}}, 1056376Sgblack@eecs.umich.edu {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}}, 1066376Sgblack@eecs.umich.edu {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}}, 1076334Sgblack@eecs.umich.edu {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}}, 1086334Sgblack@eecs.umich.edu {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}}, 1096334Sgblack@eecs.umich.edu {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}}, 1106383Sgblack@eecs.umich.edu {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}}, 1116383Sgblack@eecs.umich.edu {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}}, 1126383Sgblack@eecs.umich.edu {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}}, 1136383Sgblack@eecs.umich.edu {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 1146383Sgblack@eecs.umich.edu {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 1156383Sgblack@eecs.umich.edu {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 1166383Sgblack@eecs.umich.edu {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 1176383Sgblack@eecs.umich.edu {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 1186334Sgblack@eecs.umich.edu {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */ 1196334Sgblack@eecs.umich.edu {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 1206334Sgblack@eecs.umich.edu {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 1218181Sksewell@umich.edu {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}}, 1228181Sksewell@umich.edu {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */ 1236334Sgblack@eecs.umich.edu {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}}, 1246334Sgblack@eecs.umich.edu {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */ 1256334Sgblack@eecs.umich.edu {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 1266334Sgblack@eecs.umich.edu {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */ 1276334Sgblack@eecs.umich.edu {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 1286383Sgblack@eecs.umich.edu {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */ 1296383Sgblack@eecs.umich.edu {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */ 1306383Sgblack@eecs.umich.edu {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}}, 1316383Sgblack@eecs.umich.edu {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}}, 1326383Sgblack@eecs.umich.edu {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}}, 1336383Sgblack@eecs.umich.edu {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}}, 1346334Sgblack@eecs.umich.edu {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}}, 1356334Sgblack@eecs.umich.edu {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}}, 1366334Sgblack@eecs.umich.edu {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}}, 1376334Sgblack@eecs.umich.edu {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}}, 1388181Sksewell@umich.edu {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}}, 1396334Sgblack@eecs.umich.edu {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}}, 1406334Sgblack@eecs.umich.edu {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}}, 1416334Sgblack@eecs.umich.edu {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}}, 1428181Sksewell@umich.edu {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}}, 1436334Sgblack@eecs.umich.edu {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}}, 1446334Sgblack@eecs.umich.edu {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}}, 1456334Sgblack@eecs.umich.edu // DBGDTR_EL0 -> DBGDTR{R or T}Xint 1468181Sksewell@umich.edu // DBGDTRRX_EL0 -> DBGDTRRXint 1478181Sksewell@umich.edu // DBGDTRTX_EL0 -> DBGDTRRXint 1488181Sksewell@umich.edu {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}}, 1498181Sksewell@umich.edu {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}}, 1508181Sksewell@umich.edu {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}}, 1518181Sksewell@umich.edu {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}}, 1528181Sksewell@umich.edu {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}}, 1538181Sksewell@umich.edu {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}}, 1548181Sksewell@umich.edu {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}}, 1558181Sksewell@umich.edu {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}}, 1568181Sksewell@umich.edu {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}}, 1578181Sksewell@umich.edu {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}}, 1588181Sksewell@umich.edu {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}}, 1598181Sksewell@umich.edu {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}}, 1606334Sgblack@eecs.umich.edu {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}}, 1616334Sgblack@eecs.umich.edu {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}}, 1628181Sksewell@umich.edu {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}}, 1636334Sgblack@eecs.umich.edu {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}}, 1648181Sksewell@umich.edu {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}}, 1658181Sksewell@umich.edu {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}}, 1666334Sgblack@eecs.umich.edu {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}}, 1676334Sgblack@eecs.umich.edu {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}}, 1686334Sgblack@eecs.umich.edu {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}}, 1696334Sgblack@eecs.umich.edu {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}}, 1706334Sgblack@eecs.umich.edu {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}}, 1716334Sgblack@eecs.umich.edu {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}}, 1726334Sgblack@eecs.umich.edu {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}}, 1736334Sgblack@eecs.umich.edu {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}}, 1746383Sgblack@eecs.umich.edu/* {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}}, 1756376Sgblack@eecs.umich.edu {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}}, 1766376Sgblack@eecs.umich.edu {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}}, 1776376Sgblack@eecs.umich.edu {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}}, 1786376Sgblack@eecs.umich.edu {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}}, 1796383Sgblack@eecs.umich.edu {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}}, 1806376Sgblack@eecs.umich.edu {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}}, 1816334Sgblack@eecs.umich.edu {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}}, 1826383Sgblack@eecs.umich.edu {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}}, 1836383Sgblack@eecs.umich.edu {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}}, 1846383Sgblack@eecs.umich.edu {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}}, 1856334Sgblack@eecs.umich.edu {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */ 1866334Sgblack@eecs.umich.edu {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}}, 1876383Sgblack@eecs.umich.edu {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}}, 1886376Sgblack@eecs.umich.edu// {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}}, 1896376Sgblack@eecs.umich.edu {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}}, 1906376Sgblack@eecs.umich.edu {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}}, 1916376Sgblack@eecs.umich.edu {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}}, 1926376Sgblack@eecs.umich.edu {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}}, 1936376Sgblack@eecs.umich.edu {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}}, 1946383Sgblack@eecs.umich.edu {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}}, 1956334Sgblack@eecs.umich.edu 1966334Sgblack@eecs.umich.edu // from ARM DDI 0487A.i, template text 1976376Sgblack@eecs.umich.edu // "AArch64 System register ___ can be mapped to 1986383Sgblack@eecs.umich.edu // AArch32 System register ___, but this is not 1996334Sgblack@eecs.umich.edu // architecturally mandated." 2006334Sgblack@eecs.umich.edu {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005 2016383Sgblack@eecs.umich.edu // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5) 2026376Sgblack@eecs.umich.edu {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1 2036376Sgblack@eecs.umich.edu {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2 2046376Sgblack@eecs.umich.edu {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3 2056376Sgblack@eecs.umich.edu}; 2066376Sgblack@eecs.umich.edu 2076376Sgblack@eecs.umich.edu 2086376Sgblack@eecs.umich.eduISA::ISA(Params *p) 2096376Sgblack@eecs.umich.edu : SimObject(p), 2106376Sgblack@eecs.umich.edu system(NULL), 2116376Sgblack@eecs.umich.edu _decoderFlavour(p->decoderFlavour), 2126376Sgblack@eecs.umich.edu _vecRegRenameMode(p->vecRegRenameMode), 2136376Sgblack@eecs.umich.edu pmu(p->pmu), 2146376Sgblack@eecs.umich.edu lookUpMiscReg(NUM_MISCREGS, {0,0}) 2156376Sgblack@eecs.umich.edu{ 2166383Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = 0; 2176334Sgblack@eecs.umich.edu 2186334Sgblack@eecs.umich.edu // Hook up a dummy device if we haven't been configured with a 2196376Sgblack@eecs.umich.edu // real PMU. By using a dummy device, we don't need to check that 2206383Sgblack@eecs.umich.edu // the PMU exist every time we try to access a PMU register. 2216334Sgblack@eecs.umich.edu if (!pmu) 2226334Sgblack@eecs.umich.edu pmu = &dummyDevice; 2236383Sgblack@eecs.umich.edu 2246376Sgblack@eecs.umich.edu // Give all ISA devices a pointer to this ISA 2256376Sgblack@eecs.umich.edu pmu->setISA(this); 2266376Sgblack@eecs.umich.edu 2276376Sgblack@eecs.umich.edu system = dynamic_cast<ArmSystem *>(p->system); 2286376Sgblack@eecs.umich.edu 2296376Sgblack@eecs.umich.edu // Cache system-level properties 2306376Sgblack@eecs.umich.edu if (FullSystem && system) { 2316376Sgblack@eecs.umich.edu highestELIs64 = system->highestELIs64(); 2326376Sgblack@eecs.umich.edu haveSecurity = system->haveSecurity(); 2336383Sgblack@eecs.umich.edu haveLPAE = system->haveLPAE(); 2346334Sgblack@eecs.umich.edu haveVirtualization = system->haveVirtualization(); 2356334Sgblack@eecs.umich.edu haveLargeAsid64 = system->haveLargeAsid64(); 2366376Sgblack@eecs.umich.edu physAddrRange64 = system->physAddrRange64(); 2376383Sgblack@eecs.umich.edu } else { 2386334Sgblack@eecs.umich.edu highestELIs64 = true; // ArmSystem::highestELIs64 does the same 2396334Sgblack@eecs.umich.edu haveSecurity = haveLPAE = haveVirtualization = false; 2406383Sgblack@eecs.umich.edu haveLargeAsid64 = false; 2416376Sgblack@eecs.umich.edu physAddrRange64 = 32; // dummy value 2426376Sgblack@eecs.umich.edu } 2436376Sgblack@eecs.umich.edu 2446376Sgblack@eecs.umich.edu /** Fill in the miscReg translation table */ 2456376Sgblack@eecs.umich.edu for (auto sw : MiscRegSwitch) { 2466376Sgblack@eecs.umich.edu lookUpMiscReg[sw.index] = sw.entry; 2476376Sgblack@eecs.umich.edu } 2486376Sgblack@eecs.umich.edu 2496383Sgblack@eecs.umich.edu preUnflattenMiscReg(); 2506334Sgblack@eecs.umich.edu 2516334Sgblack@eecs.umich.edu clear(); 2526376Sgblack@eecs.umich.edu} 2536383Sgblack@eecs.umich.edu 2546334Sgblack@eecs.umich.educonst ArmISAParams * 2556334Sgblack@eecs.umich.eduISA::params() const 2566383Sgblack@eecs.umich.edu{ 2576376Sgblack@eecs.umich.edu return dynamic_cast<const Params *>(_params); 2586376Sgblack@eecs.umich.edu} 2596383Sgblack@eecs.umich.edu 2606334Sgblack@eecs.umich.eduvoid 2616334Sgblack@eecs.umich.eduISA::clear() 2626334Sgblack@eecs.umich.edu{ 2636376Sgblack@eecs.umich.edu const Params *p(params()); 2646383Sgblack@eecs.umich.edu 2656334Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 2666334Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 2676383Sgblack@eecs.umich.edu 2686376Sgblack@eecs.umich.edu // Initialize configurable default values 2696383Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR] = p->midr; 2706334Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR_EL1] = p->midr; 2716334Sgblack@eecs.umich.edu miscRegs[MISCREG_VPIDR] = p->midr; 2726376Sgblack@eecs.umich.edu 2736383Sgblack@eecs.umich.edu if (FullSystem && system->highestELIs64()) { 2746334Sgblack@eecs.umich.edu // Initialize AArch64 state 2756334Sgblack@eecs.umich.edu clear64(p); 2766383Sgblack@eecs.umich.edu return; 2776376Sgblack@eecs.umich.edu } 2786376Sgblack@eecs.umich.edu 2796383Sgblack@eecs.umich.edu // Initialize AArch32 state... 2806334Sgblack@eecs.umich.edu 2816334Sgblack@eecs.umich.edu CPSR cpsr = 0; 2826376Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 2836383Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 2846334Sgblack@eecs.umich.edu updateRegMap(cpsr); 2856334Sgblack@eecs.umich.edu 2866383Sgblack@eecs.umich.edu SCTLR sctlr = 0; 2876376Sgblack@eecs.umich.edu sctlr.te = (bool) sctlr_rst.te; 2886383Sgblack@eecs.umich.edu sctlr.nmfi = (bool) sctlr_rst.nmfi; 2896334Sgblack@eecs.umich.edu sctlr.v = (bool) sctlr_rst.v; 2906334Sgblack@eecs.umich.edu sctlr.u = 1; 2916376Sgblack@eecs.umich.edu sctlr.xp = 1; 2926383Sgblack@eecs.umich.edu sctlr.rao2 = 1; 2936334Sgblack@eecs.umich.edu sctlr.rao3 = 1; 2946334Sgblack@eecs.umich.edu sctlr.rao4 = 0xf; // SCTLR[6:3] 2956383Sgblack@eecs.umich.edu sctlr.uci = 1; 2966376Sgblack@eecs.umich.edu sctlr.dze = 1; 2976376Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_NS] = sctlr; 2986383Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 2996334Sgblack@eecs.umich.edu miscRegs[MISCREG_HCPTR] = 0; 3006334Sgblack@eecs.umich.edu 3016376Sgblack@eecs.umich.edu // Start with an event in the mailbox 3026383Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 3036334Sgblack@eecs.umich.edu 3046334Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs 3056383Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 3066334Sgblack@eecs.umich.edu 3076334Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 3086376Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 3096383Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 3106334Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 3116334Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 3126383Sgblack@eecs.umich.edu mvfr0.divide = 1; 3136376Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 3146383Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 3156334Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 3166334Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 3176376Sgblack@eecs.umich.edu 3186383Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 3196334Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 3206334Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 3216383Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 3226334Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 3236334Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 3246334Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 3256334Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 3266376Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 3276334Sgblack@eecs.umich.edu 3286334Sgblack@eecs.umich.edu // Reset values of PRRR and NMRR are implementation dependent 3296376Sgblack@eecs.umich.edu 3306376Sgblack@eecs.umich.edu // @todo: PRRR and NMRR in secure state? 3316376Sgblack@eecs.umich.edu miscRegs[MISCREG_PRRR_NS] = 3326334Sgblack@eecs.umich.edu (1 << 19) | // 19 3336383Sgblack@eecs.umich.edu (0 << 18) | // 18 3346334Sgblack@eecs.umich.edu (0 << 17) | // 17 3356334Sgblack@eecs.umich.edu (1 << 16) | // 16 3366376Sgblack@eecs.umich.edu (2 << 14) | // 15:14 3376383Sgblack@eecs.umich.edu (0 << 12) | // 13:12 3386334Sgblack@eecs.umich.edu (2 << 10) | // 11:10 3396334Sgblack@eecs.umich.edu (2 << 8) | // 9:8 3406334Sgblack@eecs.umich.edu (2 << 6) | // 7:6 3416383Sgblack@eecs.umich.edu (2 << 4) | // 5:4 3426376Sgblack@eecs.umich.edu (1 << 2) | // 3:2 3438181Sksewell@umich.edu 0; // 1:0 3448181Sksewell@umich.edu miscRegs[MISCREG_NMRR_NS] = 3456383Sgblack@eecs.umich.edu (1 << 30) | // 31:30 3466334Sgblack@eecs.umich.edu (0 << 26) | // 27:26 3476334Sgblack@eecs.umich.edu (0 << 24) | // 25:24 3486383Sgblack@eecs.umich.edu (3 << 22) | // 23:22 3496376Sgblack@eecs.umich.edu (2 << 20) | // 21:20 3506383Sgblack@eecs.umich.edu (0 << 18) | // 19:18 3516334Sgblack@eecs.umich.edu (0 << 16) | // 17:16 3526334Sgblack@eecs.umich.edu (1 << 14) | // 15:14 3538181Sksewell@umich.edu (0 << 12) | // 13:12 3546383Sgblack@eecs.umich.edu (2 << 10) | // 11:10 3556376Sgblack@eecs.umich.edu (0 << 8) | // 9:8 3566383Sgblack@eecs.umich.edu (3 << 6) | // 7:6 3576334Sgblack@eecs.umich.edu (2 << 4) | // 5:4 3586334Sgblack@eecs.umich.edu (0 << 2) | // 3:2 3596383Sgblack@eecs.umich.edu 0; // 1:0 3606376Sgblack@eecs.umich.edu 3616383Sgblack@eecs.umich.edu miscRegs[MISCREG_CPACR] = 0; 3626334Sgblack@eecs.umich.edu 3636334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 3646334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 3656383Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 3666376Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 3676383Sgblack@eecs.umich.edu 3686334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 3696334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 3708181Sksewell@umich.edu miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 3716383Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 3726376Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 3736383Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 3746334Sgblack@eecs.umich.edu 3756334Sgblack@eecs.umich.edu miscRegs[MISCREG_FPSID] = p->fpsid; 3766334Sgblack@eecs.umich.edu 3776383Sgblack@eecs.umich.edu if (haveLPAE) { 3786334Sgblack@eecs.umich.edu TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 3796334Sgblack@eecs.umich.edu ttbcr.eae = 0; 3806383Sgblack@eecs.umich.edu miscRegs[MISCREG_TTBCR_NS] = ttbcr; 3816383Sgblack@eecs.umich.edu // Enforce consistency with system-level settings 3826334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 3836383Sgblack@eecs.umich.edu } 3846383Sgblack@eecs.umich.edu 3856383Sgblack@eecs.umich.edu if (haveSecurity) { 3866383Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_S] = sctlr; 3876334Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR] = 0; 3886383Sgblack@eecs.umich.edu miscRegs[MISCREG_VBAR_S] = 0; 3896383Sgblack@eecs.umich.edu } else { 3906383Sgblack@eecs.umich.edu // we're always non-secure 3916334Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR] = 1; 3926383Sgblack@eecs.umich.edu } 3936383Sgblack@eecs.umich.edu 3946383Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 3956334Sgblack@eecs.umich.edu} 3966383Sgblack@eecs.umich.edu 3976383Sgblack@eecs.umich.eduvoid 3986383Sgblack@eecs.umich.eduISA::clear64(const ArmISAParams *p) 3996383Sgblack@eecs.umich.edu{ 4006334Sgblack@eecs.umich.edu CPSR cpsr = 0; 4016383Sgblack@eecs.umich.edu Addr rvbar = system->resetAddr64(); 4026383Sgblack@eecs.umich.edu switch (system->highestEL()) { 4036383Sgblack@eecs.umich.edu // Set initial EL to highest implemented EL using associated stack 4046334Sgblack@eecs.umich.edu // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 4056334Sgblack@eecs.umich.edu // value 4066334Sgblack@eecs.umich.edu case EL3: 4076334Sgblack@eecs.umich.edu cpsr.mode = MODE_EL3H; 4086334Sgblack@eecs.umich.edu miscRegs[MISCREG_RVBAR_EL3] = rvbar; 4096334Sgblack@eecs.umich.edu break; 4106383Sgblack@eecs.umich.edu case EL2: 4116376Sgblack@eecs.umich.edu cpsr.mode = MODE_EL2H; 4126313Sgblack@eecs.umich.edu miscRegs[MISCREG_RVBAR_EL2] = rvbar; 4136313Sgblack@eecs.umich.edu break; 4146313Sgblack@eecs.umich.edu case EL1: 4156383Sgblack@eecs.umich.edu cpsr.mode = MODE_EL1H; 4166313Sgblack@eecs.umich.edu miscRegs[MISCREG_RVBAR_EL1] = rvbar; 4176334Sgblack@eecs.umich.edu break; 4186334Sgblack@eecs.umich.edu default: 4196334Sgblack@eecs.umich.edu panic("Invalid highest implemented exception level"); 4206334Sgblack@eecs.umich.edu break; 4216334Sgblack@eecs.umich.edu } 4226334Sgblack@eecs.umich.edu 4236313Sgblack@eecs.umich.edu // Initialize rest of CPSR 4246313Sgblack@eecs.umich.edu cpsr.daif = 0xf; // Mask all interrupts 4256334Sgblack@eecs.umich.edu cpsr.ss = 0; 4266334Sgblack@eecs.umich.edu cpsr.il = 0; 4276334Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 4286313Sgblack@eecs.umich.edu updateRegMap(cpsr); 4296383Sgblack@eecs.umich.edu 4306313Sgblack@eecs.umich.edu // Initialize other control registers 4316334Sgblack@eecs.umich.edu miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 4326334Sgblack@eecs.umich.edu if (haveSecurity) { 4336334Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 4346334Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 4356334Sgblack@eecs.umich.edu } else if (haveVirtualization) { 4366334Sgblack@eecs.umich.edu // also MISCREG_SCTLR_EL2 (by mapping) 4376334Sgblack@eecs.umich.edu miscRegs[MISCREG_HSCTLR] = 0x30c50830; 4386378Sgblack@eecs.umich.edu } else { 4396313Sgblack@eecs.umich.edu // also MISCREG_SCTLR_EL1 (by mapping) 4406313Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 4416313Sgblack@eecs.umich.edu // Always non-secure 4426383Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR_EL3] = 1; 4436313Sgblack@eecs.umich.edu } 4446334Sgblack@eecs.umich.edu 4456334Sgblack@eecs.umich.edu // Initialize configurable id registers 4466334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 4476334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 4486334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64DFR0_EL1] = 4496334Sgblack@eecs.umich.edu (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 4506334Sgblack@eecs.umich.edu (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 4516334Sgblack@eecs.umich.edu 4526313Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 4536313Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 4546313Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 4556383Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 4566313Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 4576334Sgblack@eecs.umich.edu 4586334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_DFR0_EL1] = 4596334Sgblack@eecs.umich.edu (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 4606334Sgblack@eecs.umich.edu 4616334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 4626334Sgblack@eecs.umich.edu 4636334Sgblack@eecs.umich.edu // Enforce consistency with system-level settings... 4646334Sgblack@eecs.umich.edu 4656334Sgblack@eecs.umich.edu // EL3 4666334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 4676334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 4686334Sgblack@eecs.umich.edu haveSecurity ? 0x2 : 0x0); 4696334Sgblack@eecs.umich.edu // EL2 4706383Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 4716334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 4726334Sgblack@eecs.umich.edu haveVirtualization ? 0x2 : 0x0); 4736334Sgblack@eecs.umich.edu // Large ASID support 4746334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 4756334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 4766334Sgblack@eecs.umich.edu haveLargeAsid64 ? 0x2 : 0x0); 4776334Sgblack@eecs.umich.edu // Physical address size 4786334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 4796334Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 4806334Sgblack@eecs.umich.edu encodePhysAddrRange64(physAddrRange64)); 4816334Sgblack@eecs.umich.edu} 4826334Sgblack@eecs.umich.edu 4836334Sgblack@eecs.umich.eduMiscReg 4846334Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int misc_reg) const 4856806Sgblack@eecs.umich.edu{ 4866334Sgblack@eecs.umich.edu assert(misc_reg < NumMiscRegs); 4876334Sgblack@eecs.umich.edu 4886334Sgblack@eecs.umich.edu auto regs = getMiscIndices(misc_reg); 4896334Sgblack@eecs.umich.edu int lower = regs.first, upper = regs.second; 4906334Sgblack@eecs.umich.edu return !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 4916334Sgblack@eecs.umich.edu |(miscRegs[upper] << 32)); 4926334Sgblack@eecs.umich.edu} 4936334Sgblack@eecs.umich.edu 4946334Sgblack@eecs.umich.edu 4956334Sgblack@eecs.umich.eduMiscReg 4966378Sgblack@eecs.umich.eduISA::readMiscReg(int misc_reg, ThreadContext *tc) 4976334Sgblack@eecs.umich.edu{ 4986378Sgblack@eecs.umich.edu CPSR cpsr = 0; 4996378Sgblack@eecs.umich.edu PCState pc = 0; 5006378Sgblack@eecs.umich.edu SCR scr = 0; 5016378Sgblack@eecs.umich.edu 5026378Sgblack@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 5036378Sgblack@eecs.umich.edu cpsr = miscRegs[misc_reg]; 5046378Sgblack@eecs.umich.edu pc = tc->pcState(); 5056378Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 5066378Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 5076378Sgblack@eecs.umich.edu return cpsr; 5086378Sgblack@eecs.umich.edu } 5096378Sgblack@eecs.umich.edu 5106378Sgblack@eecs.umich.edu#ifndef NDEBUG 5116313Sgblack@eecs.umich.edu if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 5126313Sgblack@eecs.umich.edu if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 5136313Sgblack@eecs.umich.edu warn("Unimplemented system register %s read.\n", 5146806Sgblack@eecs.umich.edu miscRegName[misc_reg]); 5156313Sgblack@eecs.umich.edu else 5166334Sgblack@eecs.umich.edu panic("Unimplemented system register %s read.\n", 5176334Sgblack@eecs.umich.edu miscRegName[misc_reg]); 5186334Sgblack@eecs.umich.edu } 5196334Sgblack@eecs.umich.edu#endif 5206334Sgblack@eecs.umich.edu 5217823Ssteve.reinhardt@amd.com switch (unflattenMiscReg(misc_reg)) { 5226334Sgblack@eecs.umich.edu case MISCREG_HCR: 5236313Sgblack@eecs.umich.edu { 5246313Sgblack@eecs.umich.edu if (!haveVirtualization) 5256313Sgblack@eecs.umich.edu return 0; 5266806Sgblack@eecs.umich.edu else 5276313Sgblack@eecs.umich.edu return readMiscRegNoEffect(MISCREG_HCR); 5286334Sgblack@eecs.umich.edu } 5296334Sgblack@eecs.umich.edu case MISCREG_CPACR: 5306334Sgblack@eecs.umich.edu { 5316334Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 5326334Sgblack@eecs.umich.edu CPACR cpacrMask = 0; 5336383Sgblack@eecs.umich.edu // Only cp10, cp11, and ase are implemented, nothing else should 5346376Sgblack@eecs.umich.edu // be readable? (straight copy from the write code) 5356334Sgblack@eecs.umich.edu cpacrMask.cp10 = ones; 5366334Sgblack@eecs.umich.edu cpacrMask.cp11 = ones; 5376383Sgblack@eecs.umich.edu cpacrMask.asedis = ones; 5386383Sgblack@eecs.umich.edu 5396334Sgblack@eecs.umich.edu // Security Extensions may limit the readability of CPACR 5406334Sgblack@eecs.umich.edu if (haveSecurity) { 5416376Sgblack@eecs.umich.edu scr = readMiscRegNoEffect(MISCREG_SCR); 5426334Sgblack@eecs.umich.edu cpsr = readMiscRegNoEffect(MISCREG_CPSR); 5436376Sgblack@eecs.umich.edu if (scr.ns && (cpsr.mode != MODE_MON)) { 5446334Sgblack@eecs.umich.edu NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 5456334Sgblack@eecs.umich.edu // NB: Skipping the full loop, here 5466334Sgblack@eecs.umich.edu if (!nsacr.cp10) cpacrMask.cp10 = 0; 5476334Sgblack@eecs.umich.edu if (!nsacr.cp11) cpacrMask.cp11 = 0; 5486376Sgblack@eecs.umich.edu } 5496334Sgblack@eecs.umich.edu } 5506334Sgblack@eecs.umich.edu MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 5516334Sgblack@eecs.umich.edu val &= cpacrMask; 5526334Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 5536334Sgblack@eecs.umich.edu miscRegName[misc_reg], val); 5546334Sgblack@eecs.umich.edu return val; 5556334Sgblack@eecs.umich.edu } 5566334Sgblack@eecs.umich.edu case MISCREG_MPIDR: 5576334Sgblack@eecs.umich.edu cpsr = readMiscRegNoEffect(MISCREG_CPSR); 5586334Sgblack@eecs.umich.edu scr = readMiscRegNoEffect(MISCREG_SCR); 5596334Sgblack@eecs.umich.edu if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 5606334Sgblack@eecs.umich.edu return getMPIDR(system, tc); 5616334Sgblack@eecs.umich.edu } else { 5626334Sgblack@eecs.umich.edu return readMiscReg(MISCREG_VMPIDR, tc); 5636334Sgblack@eecs.umich.edu } 5646806Sgblack@eecs.umich.edu break; 5656334Sgblack@eecs.umich.edu case MISCREG_MPIDR_EL1: 5666334Sgblack@eecs.umich.edu // @todo in the absence of v8 virtualization support just return MPIDR_EL1 5676334Sgblack@eecs.umich.edu return getMPIDR(system, tc) & 0xffffffff; 5686334Sgblack@eecs.umich.edu case MISCREG_VMPIDR: 5696334Sgblack@eecs.umich.edu // top bit defined as RES1 5706334Sgblack@eecs.umich.edu return readMiscRegNoEffect(misc_reg) | 0x80000000; 5716334Sgblack@eecs.umich.edu case MISCREG_ID_AFR0: // not implemented, so alias MIDR 5726334Sgblack@eecs.umich.edu case MISCREG_REVIDR: // not implemented, so alias MIDR 5736334Sgblack@eecs.umich.edu case MISCREG_MIDR: 5746334Sgblack@eecs.umich.edu cpsr = readMiscRegNoEffect(MISCREG_CPSR); 5756334Sgblack@eecs.umich.edu scr = readMiscRegNoEffect(MISCREG_SCR); 5766334Sgblack@eecs.umich.edu if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 5776334Sgblack@eecs.umich.edu return readMiscRegNoEffect(misc_reg); 5787823Ssteve.reinhardt@amd.com } else { 5796334Sgblack@eecs.umich.edu return readMiscRegNoEffect(MISCREG_VPIDR); 5806334Sgblack@eecs.umich.edu } 5816334Sgblack@eecs.umich.edu break; 5826334Sgblack@eecs.umich.edu case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 5836334Sgblack@eecs.umich.edu case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 5846334Sgblack@eecs.umich.edu case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 5856334Sgblack@eecs.umich.edu case MISCREG_AIDR: // AUX ID set to 0 5866313Sgblack@eecs.umich.edu case MISCREG_TCMTR: // No TCM's 5876313Sgblack@eecs.umich.edu return 0; 5886313Sgblack@eecs.umich.edu 589 case MISCREG_CLIDR: 590 warn_once("The clidr register always reports 0 caches.\n"); 591 warn_once("clidr LoUIS field of 0b001 to match current " 592 "ARM implementations.\n"); 593 return 0x00200000; 594 case MISCREG_CCSIDR: 595 warn_once("The ccsidr register isn't implemented and " 596 "always reads as 0.\n"); 597 break; 598 case MISCREG_CTR: // AArch32, ARMv7, top bit set 599 case MISCREG_CTR_EL0: // AArch64 600 { 601 //all caches have the same line size in gem5 602 //4 byte words in ARM 603 unsigned lineSizeWords = 604 tc->getSystemPtr()->cacheLineSize() / 4; 605 unsigned log2LineSizeWords = 0; 606 607 while (lineSizeWords >>= 1) { 608 ++log2LineSizeWords; 609 } 610 611 CTR ctr = 0; 612 //log2 of minimun i-cache line size (words) 613 ctr.iCacheLineSize = log2LineSizeWords; 614 //b11 - gem5 uses pipt 615 ctr.l1IndexPolicy = 0x3; 616 //log2 of minimum d-cache line size (words) 617 ctr.dCacheLineSize = log2LineSizeWords; 618 //log2 of max reservation size (words) 619 ctr.erg = log2LineSizeWords; 620 //log2 of max writeback size (words) 621 ctr.cwg = log2LineSizeWords; 622 //b100 - gem5 format is ARMv7 623 ctr.format = 0x4; 624 625 return ctr; 626 } 627 case MISCREG_ACTLR: 628 warn("Not doing anything for miscreg ACTLR\n"); 629 break; 630 631 case MISCREG_PMXEVTYPER_PMCCFILTR: 632 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 633 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 634 case MISCREG_PMCR ... MISCREG_PMOVSSET: 635 return pmu->readMiscReg(misc_reg); 636 637 case MISCREG_CPSR_Q: 638 panic("shouldn't be reading this register seperately\n"); 639 case MISCREG_FPSCR_QC: 640 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 641 case MISCREG_FPSCR_EXC: 642 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 643 case MISCREG_FPSR: 644 { 645 const uint32_t ones = (uint32_t)(-1); 646 FPSCR fpscrMask = 0; 647 fpscrMask.ioc = ones; 648 fpscrMask.dzc = ones; 649 fpscrMask.ofc = ones; 650 fpscrMask.ufc = ones; 651 fpscrMask.ixc = ones; 652 fpscrMask.idc = ones; 653 fpscrMask.qc = ones; 654 fpscrMask.v = ones; 655 fpscrMask.c = ones; 656 fpscrMask.z = ones; 657 fpscrMask.n = ones; 658 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 659 } 660 case MISCREG_FPCR: 661 { 662 const uint32_t ones = (uint32_t)(-1); 663 FPSCR fpscrMask = 0; 664 fpscrMask.ioe = ones; 665 fpscrMask.dze = ones; 666 fpscrMask.ofe = ones; 667 fpscrMask.ufe = ones; 668 fpscrMask.ixe = ones; 669 fpscrMask.ide = ones; 670 fpscrMask.len = ones; 671 fpscrMask.stride = ones; 672 fpscrMask.rMode = ones; 673 fpscrMask.fz = ones; 674 fpscrMask.dn = ones; 675 fpscrMask.ahp = ones; 676 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 677 } 678 case MISCREG_NZCV: 679 { 680 CPSR cpsr = 0; 681 cpsr.nz = tc->readCCReg(CCREG_NZ); 682 cpsr.c = tc->readCCReg(CCREG_C); 683 cpsr.v = tc->readCCReg(CCREG_V); 684 return cpsr; 685 } 686 case MISCREG_DAIF: 687 { 688 CPSR cpsr = 0; 689 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 690 return cpsr; 691 } 692 case MISCREG_SP_EL0: 693 { 694 return tc->readIntReg(INTREG_SP0); 695 } 696 case MISCREG_SP_EL1: 697 { 698 return tc->readIntReg(INTREG_SP1); 699 } 700 case MISCREG_SP_EL2: 701 { 702 return tc->readIntReg(INTREG_SP2); 703 } 704 case MISCREG_SPSEL: 705 { 706 return miscRegs[MISCREG_CPSR] & 0x1; 707 } 708 case MISCREG_CURRENTEL: 709 { 710 return miscRegs[MISCREG_CPSR] & 0xc; 711 } 712 case MISCREG_L2CTLR: 713 { 714 // mostly unimplemented, just set NumCPUs field from sim and return 715 L2CTLR l2ctlr = 0; 716 // b00:1CPU to b11:4CPUs 717 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 718 return l2ctlr; 719 } 720 case MISCREG_DBGDIDR: 721 /* For now just implement the version number. 722 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 723 */ 724 return 0x5 << 16; 725 case MISCREG_DBGDSCRint: 726 return 0; 727 case MISCREG_ISR: 728 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 729 readMiscRegNoEffect(MISCREG_HCR), 730 readMiscRegNoEffect(MISCREG_CPSR), 731 readMiscRegNoEffect(MISCREG_SCR)); 732 case MISCREG_ISR_EL1: 733 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 734 readMiscRegNoEffect(MISCREG_HCR_EL2), 735 readMiscRegNoEffect(MISCREG_CPSR), 736 readMiscRegNoEffect(MISCREG_SCR_EL3)); 737 case MISCREG_DCZID_EL0: 738 return 0x04; // DC ZVA clear 64-byte chunks 739 case MISCREG_HCPTR: 740 { 741 MiscReg val = readMiscRegNoEffect(misc_reg); 742 // The trap bit associated with CP14 is defined as RAZ 743 val &= ~(1 << 14); 744 // If a CP bit in NSACR is 0 then the corresponding bit in 745 // HCPTR is RAO/WI 746 bool secure_lookup = haveSecurity && 747 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 748 readMiscRegNoEffect(MISCREG_CPSR)); 749 if (!secure_lookup) { 750 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 751 val |= (mask ^ 0x7FFF) & 0xBFFF; 752 } 753 // Set the bits for unimplemented coprocessors to RAO/WI 754 val |= 0x33FF; 755 return (val); 756 } 757 case MISCREG_HDFAR: // alias for secure DFAR 758 return readMiscRegNoEffect(MISCREG_DFAR_S); 759 case MISCREG_HIFAR: // alias for secure IFAR 760 return readMiscRegNoEffect(MISCREG_IFAR_S); 761 case MISCREG_HVBAR: // bottom bits reserved 762 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 763 case MISCREG_SCTLR: 764 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 765 case MISCREG_SCTLR_EL1: 766 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 767 case MISCREG_SCTLR_EL2: 768 case MISCREG_SCTLR_EL3: 769 case MISCREG_HSCTLR: 770 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 771 772 case MISCREG_ID_PFR0: 773 // !ThumbEE | !Jazelle | Thumb | ARM 774 return 0x00000031; 775 case MISCREG_ID_PFR1: 776 { // Timer | Virti | !M Profile | TrustZone | ARMv4 777 bool haveTimer = (system->getGenericTimer() != NULL); 778 return 0x00000001 779 | (haveSecurity ? 0x00000010 : 0x0) 780 | (haveVirtualization ? 0x00001000 : 0x0) 781 | (haveTimer ? 0x00010000 : 0x0); 782 } 783 case MISCREG_ID_AA64PFR0_EL1: 784 return 0x0000000000000002 // AArch{64,32} supported at EL0 785 | 0x0000000000000020 // EL1 786 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 787 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 788 case MISCREG_ID_AA64PFR1_EL1: 789 return 0; // bits [63:0] RES0 (reserved for future use) 790 791 // Generic Timer registers 792 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 793 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 794 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 795 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 796 return getGenericTimer(tc).readMiscReg(misc_reg); 797 798 default: 799 break; 800 801 } 802 return readMiscRegNoEffect(misc_reg); 803} 804 805void 806ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 807{ 808 assert(misc_reg < NumMiscRegs); 809 810 auto regs = getMiscIndices(misc_reg); 811 int lower = regs.first, upper = regs.second; 812 if (upper > 0) { 813 miscRegs[lower] = bits(val, 31, 0); 814 miscRegs[upper] = bits(val, 63, 32); 815 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 816 misc_reg, lower, upper, val); 817 } else { 818 miscRegs[lower] = val; 819 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 820 misc_reg, lower, val); 821 } 822} 823 824void 825ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 826{ 827 828 MiscReg newVal = val; 829 int x; 830 bool secure_lookup; 831 bool hyp; 832 System *sys; 833 ThreadContext *oc; 834 uint8_t target_el; 835 uint16_t asid; 836 SCR scr; 837 838 if (misc_reg == MISCREG_CPSR) { 839 updateRegMap(val); 840 841 842 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 843 int old_mode = old_cpsr.mode; 844 CPSR cpsr = val; 845 if (old_mode != cpsr.mode) { 846 tc->getITBPtr()->invalidateMiscReg(); 847 tc->getDTBPtr()->invalidateMiscReg(); 848 } 849 850 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 851 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 852 PCState pc = tc->pcState(); 853 pc.nextThumb(cpsr.t); 854 pc.nextJazelle(cpsr.j); 855 856 // Follow slightly different semantics if a CheckerCPU object 857 // is connected 858 CheckerCPU *checker = tc->getCheckerCpuPtr(); 859 if (checker) { 860 tc->pcStateNoRecord(pc); 861 } else { 862 tc->pcState(pc); 863 } 864 } else { 865#ifndef NDEBUG 866 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 867 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 868 warn("Unimplemented system register %s write with %#x.\n", 869 miscRegName[misc_reg], val); 870 else 871 panic("Unimplemented system register %s write with %#x.\n", 872 miscRegName[misc_reg], val); 873 } 874#endif 875 switch (unflattenMiscReg(misc_reg)) { 876 case MISCREG_CPACR: 877 { 878 879 const uint32_t ones = (uint32_t)(-1); 880 CPACR cpacrMask = 0; 881 // Only cp10, cp11, and ase are implemented, nothing else should 882 // be writable 883 cpacrMask.cp10 = ones; 884 cpacrMask.cp11 = ones; 885 cpacrMask.asedis = ones; 886 887 // Security Extensions may limit the writability of CPACR 888 if (haveSecurity) { 889 scr = readMiscRegNoEffect(MISCREG_SCR); 890 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 891 if (scr.ns && (cpsr.mode != MODE_MON)) { 892 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 893 // NB: Skipping the full loop, here 894 if (!nsacr.cp10) cpacrMask.cp10 = 0; 895 if (!nsacr.cp11) cpacrMask.cp11 = 0; 896 } 897 } 898 899 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 900 newVal &= cpacrMask; 901 newVal |= old_val & ~cpacrMask; 902 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 903 miscRegName[misc_reg], newVal); 904 } 905 break; 906 case MISCREG_CPACR_EL1: 907 { 908 const uint32_t ones = (uint32_t)(-1); 909 CPACR cpacrMask = 0; 910 cpacrMask.tta = ones; 911 cpacrMask.fpen = ones; 912 newVal &= cpacrMask; 913 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 914 miscRegName[misc_reg], newVal); 915 } 916 break; 917 case MISCREG_CPTR_EL2: 918 { 919 const uint32_t ones = (uint32_t)(-1); 920 CPTR cptrMask = 0; 921 cptrMask.tcpac = ones; 922 cptrMask.tta = ones; 923 cptrMask.tfp = ones; 924 newVal &= cptrMask; 925 cptrMask = 0; 926 cptrMask.res1_13_12_el2 = ones; 927 cptrMask.res1_9_0_el2 = ones; 928 newVal |= cptrMask; 929 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 930 miscRegName[misc_reg], newVal); 931 } 932 break; 933 case MISCREG_CPTR_EL3: 934 { 935 const uint32_t ones = (uint32_t)(-1); 936 CPTR cptrMask = 0; 937 cptrMask.tcpac = ones; 938 cptrMask.tta = ones; 939 cptrMask.tfp = ones; 940 newVal &= cptrMask; 941 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 942 miscRegName[misc_reg], newVal); 943 } 944 break; 945 case MISCREG_CSSELR: 946 warn_once("The csselr register isn't implemented.\n"); 947 return; 948 949 case MISCREG_DC_ZVA_Xt: 950 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 951 return; 952 953 case MISCREG_FPSCR: 954 { 955 const uint32_t ones = (uint32_t)(-1); 956 FPSCR fpscrMask = 0; 957 fpscrMask.ioc = ones; 958 fpscrMask.dzc = ones; 959 fpscrMask.ofc = ones; 960 fpscrMask.ufc = ones; 961 fpscrMask.ixc = ones; 962 fpscrMask.idc = ones; 963 fpscrMask.ioe = ones; 964 fpscrMask.dze = ones; 965 fpscrMask.ofe = ones; 966 fpscrMask.ufe = ones; 967 fpscrMask.ixe = ones; 968 fpscrMask.ide = ones; 969 fpscrMask.len = ones; 970 fpscrMask.stride = ones; 971 fpscrMask.rMode = ones; 972 fpscrMask.fz = ones; 973 fpscrMask.dn = ones; 974 fpscrMask.ahp = ones; 975 fpscrMask.qc = ones; 976 fpscrMask.v = ones; 977 fpscrMask.c = ones; 978 fpscrMask.z = ones; 979 fpscrMask.n = ones; 980 newVal = (newVal & (uint32_t)fpscrMask) | 981 (readMiscRegNoEffect(MISCREG_FPSCR) & 982 ~(uint32_t)fpscrMask); 983 tc->getDecoderPtr()->setContext(newVal); 984 } 985 break; 986 case MISCREG_FPSR: 987 { 988 const uint32_t ones = (uint32_t)(-1); 989 FPSCR fpscrMask = 0; 990 fpscrMask.ioc = ones; 991 fpscrMask.dzc = ones; 992 fpscrMask.ofc = ones; 993 fpscrMask.ufc = ones; 994 fpscrMask.ixc = ones; 995 fpscrMask.idc = ones; 996 fpscrMask.qc = ones; 997 fpscrMask.v = ones; 998 fpscrMask.c = ones; 999 fpscrMask.z = ones; 1000 fpscrMask.n = ones; 1001 newVal = (newVal & (uint32_t)fpscrMask) | 1002 (readMiscRegNoEffect(MISCREG_FPSCR) & 1003 ~(uint32_t)fpscrMask); 1004 misc_reg = MISCREG_FPSCR; 1005 } 1006 break; 1007 case MISCREG_FPCR: 1008 { 1009 const uint32_t ones = (uint32_t)(-1); 1010 FPSCR fpscrMask = 0; 1011 fpscrMask.ioe = ones; 1012 fpscrMask.dze = ones; 1013 fpscrMask.ofe = ones; 1014 fpscrMask.ufe = ones; 1015 fpscrMask.ixe = ones; 1016 fpscrMask.ide = ones; 1017 fpscrMask.len = ones; 1018 fpscrMask.stride = ones; 1019 fpscrMask.rMode = ones; 1020 fpscrMask.fz = ones; 1021 fpscrMask.dn = ones; 1022 fpscrMask.ahp = ones; 1023 newVal = (newVal & (uint32_t)fpscrMask) | 1024 (readMiscRegNoEffect(MISCREG_FPSCR) & 1025 ~(uint32_t)fpscrMask); 1026 misc_reg = MISCREG_FPSCR; 1027 } 1028 break; 1029 case MISCREG_CPSR_Q: 1030 { 1031 assert(!(newVal & ~CpsrMaskQ)); 1032 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 1033 misc_reg = MISCREG_CPSR; 1034 } 1035 break; 1036 case MISCREG_FPSCR_QC: 1037 { 1038 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1039 (newVal & FpscrQcMask); 1040 misc_reg = MISCREG_FPSCR; 1041 } 1042 break; 1043 case MISCREG_FPSCR_EXC: 1044 { 1045 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1046 (newVal & FpscrExcMask); 1047 misc_reg = MISCREG_FPSCR; 1048 } 1049 break; 1050 case MISCREG_FPEXC: 1051 { 1052 // vfpv3 architecture, section B.6.1 of DDI04068 1053 // bit 29 - valid only if fpexc[31] is 0 1054 const uint32_t fpexcMask = 0x60000000; 1055 newVal = (newVal & fpexcMask) | 1056 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1057 } 1058 break; 1059 case MISCREG_HCR: 1060 { 1061 if (!haveVirtualization) 1062 return; 1063 } 1064 break; 1065 case MISCREG_IFSR: 1066 { 1067 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1068 const uint32_t ifsrMask = 1069 mask(31, 13) | mask(11, 11) | mask(8, 6); 1070 newVal = newVal & ~ifsrMask; 1071 } 1072 break; 1073 case MISCREG_DFSR: 1074 { 1075 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1076 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1077 newVal = newVal & ~dfsrMask; 1078 } 1079 break; 1080 case MISCREG_AMAIR0: 1081 case MISCREG_AMAIR1: 1082 { 1083 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1084 // Valid only with LPAE 1085 if (!haveLPAE) 1086 return; 1087 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1088 } 1089 break; 1090 case MISCREG_SCR: 1091 tc->getITBPtr()->invalidateMiscReg(); 1092 tc->getDTBPtr()->invalidateMiscReg(); 1093 break; 1094 case MISCREG_SCTLR: 1095 { 1096 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1097 scr = readMiscRegNoEffect(MISCREG_SCR); 1098 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns) 1099 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS; 1100 SCTLR sctlr = miscRegs[sctlr_idx]; 1101 SCTLR new_sctlr = newVal; 1102 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1103 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1104 tc->getITBPtr()->invalidateMiscReg(); 1105 tc->getDTBPtr()->invalidateMiscReg(); 1106 } 1107 case MISCREG_MIDR: 1108 case MISCREG_ID_PFR0: 1109 case MISCREG_ID_PFR1: 1110 case MISCREG_ID_DFR0: 1111 case MISCREG_ID_MMFR0: 1112 case MISCREG_ID_MMFR1: 1113 case MISCREG_ID_MMFR2: 1114 case MISCREG_ID_MMFR3: 1115 case MISCREG_ID_ISAR0: 1116 case MISCREG_ID_ISAR1: 1117 case MISCREG_ID_ISAR2: 1118 case MISCREG_ID_ISAR3: 1119 case MISCREG_ID_ISAR4: 1120 case MISCREG_ID_ISAR5: 1121 1122 case MISCREG_MPIDR: 1123 case MISCREG_FPSID: 1124 case MISCREG_TLBTR: 1125 case MISCREG_MVFR0: 1126 case MISCREG_MVFR1: 1127 1128 case MISCREG_ID_AA64AFR0_EL1: 1129 case MISCREG_ID_AA64AFR1_EL1: 1130 case MISCREG_ID_AA64DFR0_EL1: 1131 case MISCREG_ID_AA64DFR1_EL1: 1132 case MISCREG_ID_AA64ISAR0_EL1: 1133 case MISCREG_ID_AA64ISAR1_EL1: 1134 case MISCREG_ID_AA64MMFR0_EL1: 1135 case MISCREG_ID_AA64MMFR1_EL1: 1136 case MISCREG_ID_AA64PFR0_EL1: 1137 case MISCREG_ID_AA64PFR1_EL1: 1138 // ID registers are constants. 1139 return; 1140 1141 // TLBI all entries, EL0&1 inner sharable (ignored) 1142 case MISCREG_TLBIALLIS: 1143 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1144 assert32(tc); 1145 target_el = 1; // el 0 and 1 are handled together 1146 scr = readMiscReg(MISCREG_SCR, tc); 1147 secure_lookup = haveSecurity && !scr.ns; 1148 sys = tc->getSystemPtr(); 1149 for (x = 0; x < sys->numContexts(); x++) { 1150 oc = sys->getThreadContext(x); 1151 assert(oc->getITBPtr() && oc->getDTBPtr()); 1152 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1153 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1154 1155 // If CheckerCPU is connected, need to notify it of a flush 1156 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1157 if (checker) { 1158 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1159 target_el); 1160 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1161 target_el); 1162 } 1163 } 1164 return; 1165 // TLBI all entries, EL0&1, instruction side 1166 case MISCREG_ITLBIALL: 1167 assert32(tc); 1168 target_el = 1; // el 0 and 1 are handled together 1169 scr = readMiscReg(MISCREG_SCR, tc); 1170 secure_lookup = haveSecurity && !scr.ns; 1171 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1172 return; 1173 // TLBI all entries, EL0&1, data side 1174 case MISCREG_DTLBIALL: 1175 assert32(tc); 1176 target_el = 1; // el 0 and 1 are handled together 1177 scr = readMiscReg(MISCREG_SCR, tc); 1178 secure_lookup = haveSecurity && !scr.ns; 1179 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1180 return; 1181 // TLBI based on VA, EL0&1 inner sharable (ignored) 1182 case MISCREG_TLBIMVAIS: 1183 case MISCREG_TLBIMVA: 1184 assert32(tc); 1185 target_el = 1; // el 0 and 1 are handled together 1186 scr = readMiscReg(MISCREG_SCR, tc); 1187 secure_lookup = haveSecurity && !scr.ns; 1188 sys = tc->getSystemPtr(); 1189 for (x = 0; x < sys->numContexts(); x++) { 1190 oc = sys->getThreadContext(x); 1191 assert(oc->getITBPtr() && oc->getDTBPtr()); 1192 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1193 bits(newVal, 7,0), 1194 secure_lookup, target_el); 1195 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1196 bits(newVal, 7,0), 1197 secure_lookup, target_el); 1198 1199 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1200 if (checker) { 1201 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1202 bits(newVal, 7,0), secure_lookup, target_el); 1203 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1204 bits(newVal, 7,0), secure_lookup, target_el); 1205 } 1206 } 1207 return; 1208 // TLBI by ASID, EL0&1, inner sharable 1209 case MISCREG_TLBIASIDIS: 1210 case MISCREG_TLBIASID: 1211 assert32(tc); 1212 target_el = 1; // el 0 and 1 are handled together 1213 scr = readMiscReg(MISCREG_SCR, tc); 1214 secure_lookup = haveSecurity && !scr.ns; 1215 sys = tc->getSystemPtr(); 1216 for (x = 0; x < sys->numContexts(); x++) { 1217 oc = sys->getThreadContext(x); 1218 assert(oc->getITBPtr() && oc->getDTBPtr()); 1219 oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 1220 secure_lookup, target_el); 1221 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1222 secure_lookup, target_el); 1223 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1224 if (checker) { 1225 checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 1226 secure_lookup, target_el); 1227 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1228 secure_lookup, target_el); 1229 } 1230 } 1231 return; 1232 // TLBI by address, EL0&1, inner sharable (ignored) 1233 case MISCREG_TLBIMVAAIS: 1234 case MISCREG_TLBIMVAA: 1235 assert32(tc); 1236 target_el = 1; // el 0 and 1 are handled together 1237 scr = readMiscReg(MISCREG_SCR, tc); 1238 secure_lookup = haveSecurity && !scr.ns; 1239 hyp = 0; 1240 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1241 return; 1242 // TLBI by address, EL2, hypervisor mode 1243 case MISCREG_TLBIMVAH: 1244 case MISCREG_TLBIMVAHIS: 1245 assert32(tc); 1246 target_el = 1; // aarch32, use hyp bit 1247 scr = readMiscReg(MISCREG_SCR, tc); 1248 secure_lookup = haveSecurity && !scr.ns; 1249 hyp = 1; 1250 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1251 return; 1252 // TLBI by address and asid, EL0&1, instruction side only 1253 case MISCREG_ITLBIMVA: 1254 assert32(tc); 1255 target_el = 1; // el 0 and 1 are handled together 1256 scr = readMiscReg(MISCREG_SCR, tc); 1257 secure_lookup = haveSecurity && !scr.ns; 1258 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1259 bits(newVal, 7,0), secure_lookup, target_el); 1260 return; 1261 // TLBI by address and asid, EL0&1, data side only 1262 case MISCREG_DTLBIMVA: 1263 assert32(tc); 1264 target_el = 1; // el 0 and 1 are handled together 1265 scr = readMiscReg(MISCREG_SCR, tc); 1266 secure_lookup = haveSecurity && !scr.ns; 1267 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1268 bits(newVal, 7,0), secure_lookup, target_el); 1269 return; 1270 // TLBI by ASID, EL0&1, instrution side only 1271 case MISCREG_ITLBIASID: 1272 assert32(tc); 1273 target_el = 1; // el 0 and 1 are handled together 1274 scr = readMiscReg(MISCREG_SCR, tc); 1275 secure_lookup = haveSecurity && !scr.ns; 1276 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1277 target_el); 1278 return; 1279 // TLBI by ASID EL0&1 data size only 1280 case MISCREG_DTLBIASID: 1281 assert32(tc); 1282 target_el = 1; // el 0 and 1 are handled together 1283 scr = readMiscReg(MISCREG_SCR, tc); 1284 secure_lookup = haveSecurity && !scr.ns; 1285 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1286 target_el); 1287 return; 1288 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1289 case MISCREG_TLBIALLNSNH: 1290 case MISCREG_TLBIALLNSNHIS: 1291 assert32(tc); 1292 target_el = 1; // el 0 and 1 are handled together 1293 hyp = 0; 1294 tlbiALLN(tc, hyp, target_el); 1295 return; 1296 // TLBI all entries, EL2, hyp, 1297 case MISCREG_TLBIALLH: 1298 case MISCREG_TLBIALLHIS: 1299 assert32(tc); 1300 target_el = 1; // aarch32, use hyp bit 1301 hyp = 1; 1302 tlbiALLN(tc, hyp, target_el); 1303 return; 1304 // AArch64 TLBI: invalidate all entries EL3 1305 case MISCREG_TLBI_ALLE3IS: 1306 case MISCREG_TLBI_ALLE3: 1307 assert64(tc); 1308 target_el = 3; 1309 secure_lookup = true; 1310 tlbiALL(tc, secure_lookup, target_el); 1311 return; 1312 // @todo: uncomment this to enable Virtualization 1313 // case MISCREG_TLBI_ALLE2IS: 1314 // case MISCREG_TLBI_ALLE2: 1315 // TLBI all entries, EL0&1 1316 case MISCREG_TLBI_ALLE1IS: 1317 case MISCREG_TLBI_ALLE1: 1318 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1319 case MISCREG_TLBI_VMALLE1IS: 1320 case MISCREG_TLBI_VMALLE1: 1321 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1322 case MISCREG_TLBI_VMALLS12E1IS: 1323 case MISCREG_TLBI_VMALLS12E1: 1324 // @todo: handle VMID and stage 2 to enable Virtualization 1325 assert64(tc); 1326 target_el = 1; // el 0 and 1 are handled together 1327 scr = readMiscReg(MISCREG_SCR, tc); 1328 secure_lookup = haveSecurity && !scr.ns; 1329 tlbiALL(tc, secure_lookup, target_el); 1330 return; 1331 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1332 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1333 // from the last level of translation table walks 1334 // @todo: handle VMID to enable Virtualization 1335 // TLBI all entries, EL0&1 1336 case MISCREG_TLBI_VAE3IS_Xt: 1337 case MISCREG_TLBI_VAE3_Xt: 1338 // TLBI by VA, EL3 regime stage 1, last level walk 1339 case MISCREG_TLBI_VALE3IS_Xt: 1340 case MISCREG_TLBI_VALE3_Xt: 1341 assert64(tc); 1342 target_el = 3; 1343 asid = 0xbeef; // does not matter, tlbi is global 1344 secure_lookup = true; 1345 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1346 return; 1347 // TLBI by VA, EL2 1348 case MISCREG_TLBI_VAE2IS_Xt: 1349 case MISCREG_TLBI_VAE2_Xt: 1350 // TLBI by VA, EL2, stage1 last level walk 1351 case MISCREG_TLBI_VALE2IS_Xt: 1352 case MISCREG_TLBI_VALE2_Xt: 1353 assert64(tc); 1354 target_el = 2; 1355 asid = 0xbeef; // does not matter, tlbi is global 1356 scr = readMiscReg(MISCREG_SCR, tc); 1357 secure_lookup = haveSecurity && !scr.ns; 1358 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1359 return; 1360 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1361 case MISCREG_TLBI_VAE1IS_Xt: 1362 case MISCREG_TLBI_VAE1_Xt: 1363 case MISCREG_TLBI_VALE1IS_Xt: 1364 case MISCREG_TLBI_VALE1_Xt: 1365 assert64(tc); 1366 asid = bits(newVal, 63, 48); 1367 target_el = 1; // el 0 and 1 are handled together 1368 scr = readMiscReg(MISCREG_SCR, tc); 1369 secure_lookup = haveSecurity && !scr.ns; 1370 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1371 return; 1372 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1373 // @todo: handle VMID to enable Virtualization 1374 case MISCREG_TLBI_ASIDE1IS_Xt: 1375 case MISCREG_TLBI_ASIDE1_Xt: 1376 assert64(tc); 1377 target_el = 1; // el 0 and 1 are handled together 1378 scr = readMiscReg(MISCREG_SCR, tc); 1379 secure_lookup = haveSecurity && !scr.ns; 1380 sys = tc->getSystemPtr(); 1381 for (x = 0; x < sys->numContexts(); x++) { 1382 oc = sys->getThreadContext(x); 1383 assert(oc->getITBPtr() && oc->getDTBPtr()); 1384 asid = bits(newVal, 63, 48); 1385 if (!haveLargeAsid64) 1386 asid &= mask(8); 1387 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1388 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1389 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1390 if (checker) { 1391 checker->getITBPtr()->flushAsid(asid, 1392 secure_lookup, target_el); 1393 checker->getDTBPtr()->flushAsid(asid, 1394 secure_lookup, target_el); 1395 } 1396 } 1397 return; 1398 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1399 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1400 // entries from the last level of translation table walks 1401 // @todo: handle VMID to enable Virtualization 1402 case MISCREG_TLBI_VAAE1IS_Xt: 1403 case MISCREG_TLBI_VAAE1_Xt: 1404 case MISCREG_TLBI_VAALE1IS_Xt: 1405 case MISCREG_TLBI_VAALE1_Xt: 1406 assert64(tc); 1407 target_el = 1; // el 0 and 1 are handled together 1408 scr = readMiscReg(MISCREG_SCR, tc); 1409 secure_lookup = haveSecurity && !scr.ns; 1410 sys = tc->getSystemPtr(); 1411 for (x = 0; x < sys->numContexts(); x++) { 1412 // @todo: extra controls on TLBI broadcast? 1413 oc = sys->getThreadContext(x); 1414 assert(oc->getITBPtr() && oc->getDTBPtr()); 1415 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1416 oc->getITBPtr()->flushMva(va, 1417 secure_lookup, false, target_el); 1418 oc->getDTBPtr()->flushMva(va, 1419 secure_lookup, false, target_el); 1420 1421 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1422 if (checker) { 1423 checker->getITBPtr()->flushMva(va, 1424 secure_lookup, false, target_el); 1425 checker->getDTBPtr()->flushMva(va, 1426 secure_lookup, false, target_el); 1427 } 1428 } 1429 return; 1430 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1431 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1432 case MISCREG_TLBI_IPAS2LE1_Xt: 1433 case MISCREG_TLBI_IPAS2E1IS_Xt: 1434 case MISCREG_TLBI_IPAS2E1_Xt: 1435 assert64(tc); 1436 target_el = 1; // EL 0 and 1 are handled together 1437 scr = readMiscReg(MISCREG_SCR, tc); 1438 secure_lookup = haveSecurity && !scr.ns; 1439 sys = tc->getSystemPtr(); 1440 for (x = 0; x < sys->numContexts(); x++) { 1441 oc = sys->getThreadContext(x); 1442 assert(oc->getITBPtr() && oc->getDTBPtr()); 1443 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; 1444 oc->getITBPtr()->flushIpaVmid(ipa, 1445 secure_lookup, false, target_el); 1446 oc->getDTBPtr()->flushIpaVmid(ipa, 1447 secure_lookup, false, target_el); 1448 1449 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1450 if (checker) { 1451 checker->getITBPtr()->flushIpaVmid(ipa, 1452 secure_lookup, false, target_el); 1453 checker->getDTBPtr()->flushIpaVmid(ipa, 1454 secure_lookup, false, target_el); 1455 } 1456 } 1457 return; 1458 case MISCREG_ACTLR: 1459 warn("Not doing anything for write of miscreg ACTLR\n"); 1460 break; 1461 1462 case MISCREG_PMXEVTYPER_PMCCFILTR: 1463 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1464 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1465 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1466 pmu->setMiscReg(misc_reg, newVal); 1467 break; 1468 1469 1470 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1471 { 1472 HSTR hstrMask = 0; 1473 hstrMask.tjdbx = 1; 1474 newVal &= ~((uint32_t) hstrMask); 1475 break; 1476 } 1477 case MISCREG_HCPTR: 1478 { 1479 // If a CP bit in NSACR is 0 then the corresponding bit in 1480 // HCPTR is RAO/WI. Same applies to NSASEDIS 1481 secure_lookup = haveSecurity && 1482 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1483 readMiscRegNoEffect(MISCREG_CPSR)); 1484 if (!secure_lookup) { 1485 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1486 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1487 newVal = (newVal & ~mask) | (oldValue & mask); 1488 } 1489 break; 1490 } 1491 case MISCREG_HDFAR: // alias for secure DFAR 1492 misc_reg = MISCREG_DFAR_S; 1493 break; 1494 case MISCREG_HIFAR: // alias for secure IFAR 1495 misc_reg = MISCREG_IFAR_S; 1496 break; 1497 case MISCREG_ATS1CPR: 1498 case MISCREG_ATS1CPW: 1499 case MISCREG_ATS1CUR: 1500 case MISCREG_ATS1CUW: 1501 case MISCREG_ATS12NSOPR: 1502 case MISCREG_ATS12NSOPW: 1503 case MISCREG_ATS12NSOUR: 1504 case MISCREG_ATS12NSOUW: 1505 case MISCREG_ATS1HR: 1506 case MISCREG_ATS1HW: 1507 { 1508 Request::Flags flags = 0; 1509 BaseTLB::Mode mode = BaseTLB::Read; 1510 TLB::ArmTranslationType tranType = TLB::NormalTran; 1511 Fault fault; 1512 switch(misc_reg) { 1513 case MISCREG_ATS1CPR: 1514 flags = TLB::MustBeOne; 1515 tranType = TLB::S1CTran; 1516 mode = BaseTLB::Read; 1517 break; 1518 case MISCREG_ATS1CPW: 1519 flags = TLB::MustBeOne; 1520 tranType = TLB::S1CTran; 1521 mode = BaseTLB::Write; 1522 break; 1523 case MISCREG_ATS1CUR: 1524 flags = TLB::MustBeOne | TLB::UserMode; 1525 tranType = TLB::S1CTran; 1526 mode = BaseTLB::Read; 1527 break; 1528 case MISCREG_ATS1CUW: 1529 flags = TLB::MustBeOne | TLB::UserMode; 1530 tranType = TLB::S1CTran; 1531 mode = BaseTLB::Write; 1532 break; 1533 case MISCREG_ATS12NSOPR: 1534 if (!haveSecurity) 1535 panic("Security Extensions required for ATS12NSOPR"); 1536 flags = TLB::MustBeOne; 1537 tranType = TLB::S1S2NsTran; 1538 mode = BaseTLB::Read; 1539 break; 1540 case MISCREG_ATS12NSOPW: 1541 if (!haveSecurity) 1542 panic("Security Extensions required for ATS12NSOPW"); 1543 flags = TLB::MustBeOne; 1544 tranType = TLB::S1S2NsTran; 1545 mode = BaseTLB::Write; 1546 break; 1547 case MISCREG_ATS12NSOUR: 1548 if (!haveSecurity) 1549 panic("Security Extensions required for ATS12NSOUR"); 1550 flags = TLB::MustBeOne | TLB::UserMode; 1551 tranType = TLB::S1S2NsTran; 1552 mode = BaseTLB::Read; 1553 break; 1554 case MISCREG_ATS12NSOUW: 1555 if (!haveSecurity) 1556 panic("Security Extensions required for ATS12NSOUW"); 1557 flags = TLB::MustBeOne | TLB::UserMode; 1558 tranType = TLB::S1S2NsTran; 1559 mode = BaseTLB::Write; 1560 break; 1561 case MISCREG_ATS1HR: // only really useful from secure mode. 1562 flags = TLB::MustBeOne; 1563 tranType = TLB::HypMode; 1564 mode = BaseTLB::Read; 1565 break; 1566 case MISCREG_ATS1HW: 1567 flags = TLB::MustBeOne; 1568 tranType = TLB::HypMode; 1569 mode = BaseTLB::Write; 1570 break; 1571 } 1572 // If we're in timing mode then doing the translation in 1573 // functional mode then we're slightly distorting performance 1574 // results obtained from simulations. The translation should be 1575 // done in the same mode the core is running in. NOTE: This 1576 // can't be an atomic translation because that causes problems 1577 // with unexpected atomic snoop requests. 1578 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1579 Request req(0, val, 0, flags, Request::funcMasterId, 1580 tc->pcState().pc(), tc->contextId()); 1581 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 1582 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1583 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1584 1585 MiscReg newVal; 1586 if (fault == NoFault) { 1587 Addr paddr = req.getPaddr(); 1588 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1589 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1590 newVal = (paddr & mask(39, 12)) | 1591 (tc->getDTBPtr()->getAttr()); 1592 } else { 1593 newVal = (paddr & 0xfffff000) | 1594 (tc->getDTBPtr()->getAttr()); 1595 } 1596 DPRINTF(MiscRegs, 1597 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1598 val, newVal); 1599 } else { 1600 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1601 // Set fault bit and FSR 1602 FSR fsr = armFault->getFsr(tc); 1603 1604 newVal = ((fsr >> 9) & 1) << 11; 1605 if (newVal) { 1606 // LPAE - rearange fault status 1607 newVal |= ((fsr >> 0) & 0x3f) << 1; 1608 } else { 1609 // VMSA - rearange fault status 1610 newVal |= ((fsr >> 0) & 0xf) << 1; 1611 newVal |= ((fsr >> 10) & 0x1) << 5; 1612 newVal |= ((fsr >> 12) & 0x1) << 6; 1613 } 1614 newVal |= 0x1; // F bit 1615 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1616 newVal |= armFault->isStage2() ? 0x200 : 0; 1617 DPRINTF(MiscRegs, 1618 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1619 val, fsr, newVal); 1620 } 1621 setMiscRegNoEffect(MISCREG_PAR, newVal); 1622 return; 1623 } 1624 case MISCREG_TTBCR: 1625 { 1626 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1627 const uint32_t ones = (uint32_t)(-1); 1628 TTBCR ttbcrMask = 0; 1629 TTBCR ttbcrNew = newVal; 1630 1631 // ARM DDI 0406C.b, ARMv7-32 1632 ttbcrMask.n = ones; // T0SZ 1633 if (haveSecurity) { 1634 ttbcrMask.pd0 = ones; 1635 ttbcrMask.pd1 = ones; 1636 } 1637 ttbcrMask.epd0 = ones; 1638 ttbcrMask.irgn0 = ones; 1639 ttbcrMask.orgn0 = ones; 1640 ttbcrMask.sh0 = ones; 1641 ttbcrMask.ps = ones; // T1SZ 1642 ttbcrMask.a1 = ones; 1643 ttbcrMask.epd1 = ones; 1644 ttbcrMask.irgn1 = ones; 1645 ttbcrMask.orgn1 = ones; 1646 ttbcrMask.sh1 = ones; 1647 if (haveLPAE) 1648 ttbcrMask.eae = ones; 1649 1650 if (haveLPAE && ttbcrNew.eae) { 1651 newVal = newVal & ttbcrMask; 1652 } else { 1653 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1654 } 1655 } 1656 case MISCREG_TTBR0: 1657 case MISCREG_TTBR1: 1658 { 1659 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1660 if (haveLPAE) { 1661 if (ttbcr.eae) { 1662 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1663 // ARMv8 AArch32 bit 63-56 only 1664 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1665 newVal = (newVal & (~ttbrMask)); 1666 } 1667 } 1668 } 1669 case MISCREG_SCTLR_EL1: 1670 { 1671 tc->getITBPtr()->invalidateMiscReg(); 1672 tc->getDTBPtr()->invalidateMiscReg(); 1673 setMiscRegNoEffect(misc_reg, newVal); 1674 } 1675 case MISCREG_CONTEXTIDR: 1676 case MISCREG_PRRR: 1677 case MISCREG_NMRR: 1678 case MISCREG_MAIR0: 1679 case MISCREG_MAIR1: 1680 case MISCREG_DACR: 1681 case MISCREG_VTTBR: 1682 case MISCREG_SCR_EL3: 1683 case MISCREG_HCR_EL2: 1684 case MISCREG_TCR_EL1: 1685 case MISCREG_TCR_EL2: 1686 case MISCREG_TCR_EL3: 1687 case MISCREG_SCTLR_EL2: 1688 case MISCREG_SCTLR_EL3: 1689 case MISCREG_HSCTLR: 1690 case MISCREG_TTBR0_EL1: 1691 case MISCREG_TTBR1_EL1: 1692 case MISCREG_TTBR0_EL2: 1693 case MISCREG_TTBR0_EL3: 1694 tc->getITBPtr()->invalidateMiscReg(); 1695 tc->getDTBPtr()->invalidateMiscReg(); 1696 break; 1697 case MISCREG_NZCV: 1698 { 1699 CPSR cpsr = val; 1700 1701 tc->setCCReg(CCREG_NZ, cpsr.nz); 1702 tc->setCCReg(CCREG_C, cpsr.c); 1703 tc->setCCReg(CCREG_V, cpsr.v); 1704 } 1705 break; 1706 case MISCREG_DAIF: 1707 { 1708 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1709 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1710 newVal = cpsr; 1711 misc_reg = MISCREG_CPSR; 1712 } 1713 break; 1714 case MISCREG_SP_EL0: 1715 tc->setIntReg(INTREG_SP0, newVal); 1716 break; 1717 case MISCREG_SP_EL1: 1718 tc->setIntReg(INTREG_SP1, newVal); 1719 break; 1720 case MISCREG_SP_EL2: 1721 tc->setIntReg(INTREG_SP2, newVal); 1722 break; 1723 case MISCREG_SPSEL: 1724 { 1725 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1726 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1727 newVal = cpsr; 1728 misc_reg = MISCREG_CPSR; 1729 } 1730 break; 1731 case MISCREG_CURRENTEL: 1732 { 1733 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1734 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1735 newVal = cpsr; 1736 misc_reg = MISCREG_CPSR; 1737 } 1738 break; 1739 case MISCREG_AT_S1E1R_Xt: 1740 case MISCREG_AT_S1E1W_Xt: 1741 case MISCREG_AT_S1E0R_Xt: 1742 case MISCREG_AT_S1E0W_Xt: 1743 case MISCREG_AT_S1E2R_Xt: 1744 case MISCREG_AT_S1E2W_Xt: 1745 case MISCREG_AT_S12E1R_Xt: 1746 case MISCREG_AT_S12E1W_Xt: 1747 case MISCREG_AT_S12E0R_Xt: 1748 case MISCREG_AT_S12E0W_Xt: 1749 case MISCREG_AT_S1E3R_Xt: 1750 case MISCREG_AT_S1E3W_Xt: 1751 { 1752 RequestPtr req = new Request; 1753 Request::Flags flags = 0; 1754 BaseTLB::Mode mode = BaseTLB::Read; 1755 TLB::ArmTranslationType tranType = TLB::NormalTran; 1756 Fault fault; 1757 switch(misc_reg) { 1758 case MISCREG_AT_S1E1R_Xt: 1759 flags = TLB::MustBeOne; 1760 tranType = TLB::S1E1Tran; 1761 mode = BaseTLB::Read; 1762 break; 1763 case MISCREG_AT_S1E1W_Xt: 1764 flags = TLB::MustBeOne; 1765 tranType = TLB::S1E1Tran; 1766 mode = BaseTLB::Write; 1767 break; 1768 case MISCREG_AT_S1E0R_Xt: 1769 flags = TLB::MustBeOne | TLB::UserMode; 1770 tranType = TLB::S1E0Tran; 1771 mode = BaseTLB::Read; 1772 break; 1773 case MISCREG_AT_S1E0W_Xt: 1774 flags = TLB::MustBeOne | TLB::UserMode; 1775 tranType = TLB::S1E0Tran; 1776 mode = BaseTLB::Write; 1777 break; 1778 case MISCREG_AT_S1E2R_Xt: 1779 flags = TLB::MustBeOne; 1780 tranType = TLB::S1E2Tran; 1781 mode = BaseTLB::Read; 1782 break; 1783 case MISCREG_AT_S1E2W_Xt: 1784 flags = TLB::MustBeOne; 1785 tranType = TLB::S1E2Tran; 1786 mode = BaseTLB::Write; 1787 break; 1788 case MISCREG_AT_S12E0R_Xt: 1789 flags = TLB::MustBeOne | TLB::UserMode; 1790 tranType = TLB::S12E0Tran; 1791 mode = BaseTLB::Read; 1792 break; 1793 case MISCREG_AT_S12E0W_Xt: 1794 flags = TLB::MustBeOne | TLB::UserMode; 1795 tranType = TLB::S12E0Tran; 1796 mode = BaseTLB::Write; 1797 break; 1798 case MISCREG_AT_S12E1R_Xt: 1799 flags = TLB::MustBeOne; 1800 tranType = TLB::S12E1Tran; 1801 mode = BaseTLB::Read; 1802 break; 1803 case MISCREG_AT_S12E1W_Xt: 1804 flags = TLB::MustBeOne; 1805 tranType = TLB::S12E1Tran; 1806 mode = BaseTLB::Write; 1807 break; 1808 case MISCREG_AT_S1E3R_Xt: 1809 flags = TLB::MustBeOne; 1810 tranType = TLB::S1E3Tran; 1811 mode = BaseTLB::Read; 1812 break; 1813 case MISCREG_AT_S1E3W_Xt: 1814 flags = TLB::MustBeOne; 1815 tranType = TLB::S1E3Tran; 1816 mode = BaseTLB::Write; 1817 break; 1818 } 1819 // If we're in timing mode then doing the translation in 1820 // functional mode then we're slightly distorting performance 1821 // results obtained from simulations. The translation should be 1822 // done in the same mode the core is running in. NOTE: This 1823 // can't be an atomic translation because that causes problems 1824 // with unexpected atomic snoop requests. 1825 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1826 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1827 tc->pcState().pc()); 1828 req->setContext(tc->contextId()); 1829 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1830 tranType); 1831 1832 MiscReg newVal; 1833 if (fault == NoFault) { 1834 Addr paddr = req->getPaddr(); 1835 uint64_t attr = tc->getDTBPtr()->getAttr(); 1836 uint64_t attr1 = attr >> 56; 1837 if (!attr1 || attr1 ==0x44) { 1838 attr |= 0x100; 1839 attr &= ~ uint64_t(0x80); 1840 } 1841 newVal = (paddr & mask(47, 12)) | attr; 1842 DPRINTF(MiscRegs, 1843 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1844 val, newVal); 1845 } else { 1846 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1847 // Set fault bit and FSR 1848 FSR fsr = armFault->getFsr(tc); 1849 1850 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1851 if (cpsr.width) { // AArch32 1852 newVal = ((fsr >> 9) & 1) << 11; 1853 // rearrange fault status 1854 newVal |= ((fsr >> 0) & 0x3f) << 1; 1855 newVal |= 0x1; // F bit 1856 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1857 newVal |= armFault->isStage2() ? 0x200 : 0; 1858 } else { // AArch64 1859 newVal = 1; // F bit 1860 newVal |= fsr << 1; // FST 1861 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1862 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1863 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1864 newVal |= 1 << 11; // RES1 1865 } 1866 DPRINTF(MiscRegs, 1867 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1868 val, fsr, newVal); 1869 } 1870 delete req; 1871 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1872 return; 1873 } 1874 case MISCREG_SPSR_EL3: 1875 case MISCREG_SPSR_EL2: 1876 case MISCREG_SPSR_EL1: 1877 // Force bits 23:21 to 0 1878 newVal = val & ~(0x7 << 21); 1879 break; 1880 case MISCREG_L2CTLR: 1881 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1882 miscRegName[misc_reg], uint32_t(val)); 1883 break; 1884 1885 // Generic Timer registers 1886 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1887 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1888 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1889 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1890 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1891 break; 1892 } 1893 } 1894 setMiscRegNoEffect(misc_reg, newVal); 1895} 1896 1897void 1898ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 1899 bool secure_lookup, uint8_t target_el) 1900{ 1901 if (!haveLargeAsid64) 1902 asid &= mask(8); 1903 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1904 System *sys = tc->getSystemPtr(); 1905 for (int x = 0; x < sys->numContexts(); x++) { 1906 ThreadContext *oc = sys->getThreadContext(x); 1907 assert(oc->getITBPtr() && oc->getDTBPtr()); 1908 oc->getITBPtr()->flushMvaAsid(va, asid, 1909 secure_lookup, target_el); 1910 oc->getDTBPtr()->flushMvaAsid(va, asid, 1911 secure_lookup, target_el); 1912 1913 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1914 if (checker) { 1915 checker->getITBPtr()->flushMvaAsid( 1916 va, asid, secure_lookup, target_el); 1917 checker->getDTBPtr()->flushMvaAsid( 1918 va, asid, secure_lookup, target_el); 1919 } 1920 } 1921} 1922 1923void 1924ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1925{ 1926 System *sys = tc->getSystemPtr(); 1927 for (int x = 0; x < sys->numContexts(); x++) { 1928 ThreadContext *oc = sys->getThreadContext(x); 1929 assert(oc->getITBPtr() && oc->getDTBPtr()); 1930 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1931 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1932 1933 // If CheckerCPU is connected, need to notify it of a flush 1934 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1935 if (checker) { 1936 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1937 target_el); 1938 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1939 target_el); 1940 } 1941 } 1942} 1943 1944void 1945ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1946{ 1947 System *sys = tc->getSystemPtr(); 1948 for (int x = 0; x < sys->numContexts(); x++) { 1949 ThreadContext *oc = sys->getThreadContext(x); 1950 assert(oc->getITBPtr() && oc->getDTBPtr()); 1951 oc->getITBPtr()->flushAllNs(hyp, target_el); 1952 oc->getDTBPtr()->flushAllNs(hyp, target_el); 1953 1954 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1955 if (checker) { 1956 checker->getITBPtr()->flushAllNs(hyp, target_el); 1957 checker->getDTBPtr()->flushAllNs(hyp, target_el); 1958 } 1959 } 1960} 1961 1962void 1963ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 1964 uint8_t target_el) 1965{ 1966 System *sys = tc->getSystemPtr(); 1967 for (int x = 0; x < sys->numContexts(); x++) { 1968 ThreadContext *oc = sys->getThreadContext(x); 1969 assert(oc->getITBPtr() && oc->getDTBPtr()); 1970 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 1971 secure_lookup, hyp, target_el); 1972 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1973 secure_lookup, hyp, target_el); 1974 1975 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1976 if (checker) { 1977 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 1978 secure_lookup, hyp, target_el); 1979 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1980 secure_lookup, hyp, target_el); 1981 } 1982 } 1983} 1984 1985BaseISADevice & 1986ISA::getGenericTimer(ThreadContext *tc) 1987{ 1988 // We only need to create an ISA interface the first time we try 1989 // to access the timer. 1990 if (timer) 1991 return *timer.get(); 1992 1993 assert(system); 1994 GenericTimer *generic_timer(system->getGenericTimer()); 1995 if (!generic_timer) { 1996 panic("Trying to get a generic timer from a system that hasn't " 1997 "been configured to use a generic timer.\n"); 1998 } 1999 2000 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2001 return *timer.get(); 2002} 2003 2004} 2005 2006ArmISA::ISA * 2007ArmISAParams::create() 2008{ 2009 return new ArmISA::ISA(this); 2010} 2011