isa.cc revision 11809
17405SAli.Saidi@ARM.com/* 211573SDylan.Johnson@ARM.com * Copyright (c) 2010-2016 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4211793Sbrandon.potter@amd.com 4310461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 449050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 4511793Sbrandon.potter@amd.com#include "cpu/base.hh" 468887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 478232Snate@binkert.org#include "debug/Arm.hh" 488232Snate@binkert.org#include "debug/MiscRegs.hh" 4910844Sandreas.sandberg@arm.com#include "dev/arm/generic_timer.hh" 509384SAndreas.Sandberg@arm.com#include "params/ArmISA.hh" 517678Sgblack@eecs.umich.edu#include "sim/faults.hh" 528059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 538284SAli.Saidi@ARM.com#include "sim/system.hh" 547405SAli.Saidi@ARM.com 557405SAli.Saidi@ARM.comnamespace ArmISA 567405SAli.Saidi@ARM.com{ 577405SAli.Saidi@ARM.com 5810037SARM gem5 Developers 5910037SARM gem5 Developers/** 6011768SCurtis.Dunham@arm.com * Some registers alias with others, and therefore need to be translated. 6110037SARM gem5 Developers * For each entry: 6210037SARM gem5 Developers * The first value is the misc register that is to be looked up 6310037SARM gem5 Developers * the second value is the lower part of the translation 6410037SARM gem5 Developers * the third the upper part 6511768SCurtis.Dunham@arm.com * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 6610037SARM gem5 Developers */ 6710037SARM gem5 Developersconst struct ISA::MiscRegInitializerEntry 6811768SCurtis.Dunham@arm.com ISA::MiscRegSwitch[] = { 6911768SCurtis.Dunham@arm.com {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}}, 7011768SCurtis.Dunham@arm.com {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}}, 7111768SCurtis.Dunham@arm.com {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}}, 7211768SCurtis.Dunham@arm.com {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}}, 7311768SCurtis.Dunham@arm.com {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}}, 7411768SCurtis.Dunham@arm.com {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 7511768SCurtis.Dunham@arm.com {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}}, 7611768SCurtis.Dunham@arm.com {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}}, 7711768SCurtis.Dunham@arm.com {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}}, 7811768SCurtis.Dunham@arm.com // ESR_EL1 -> DFSR 7911768SCurtis.Dunham@arm.com {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 8010037SARM gem5 Developers {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 8110037SARM gem5 Developers {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 8210037SARM gem5 Developers {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 8311768SCurtis.Dunham@arm.com {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}}, 8411768SCurtis.Dunham@arm.com {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 8511768SCurtis.Dunham@arm.com {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}}, 8611768SCurtis.Dunham@arm.com {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 8711768SCurtis.Dunham@arm.com {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 8811768SCurtis.Dunham@arm.com {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 8911768SCurtis.Dunham@arm.com {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 9011768SCurtis.Dunham@arm.com {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 9110037SARM gem5 Developers {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 9211768SCurtis.Dunham@arm.com {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 9311768SCurtis.Dunham@arm.com {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 9411768SCurtis.Dunham@arm.com {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 9511768SCurtis.Dunham@arm.com {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 9610037SARM gem5 Developers {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 9711768SCurtis.Dunham@arm.com {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}}, 9811768SCurtis.Dunham@arm.com {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}}, 9911768SCurtis.Dunham@arm.com {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}}, 10011768SCurtis.Dunham@arm.com // RMR_EL1 -> RMR 10111768SCurtis.Dunham@arm.com // RMR_EL2 -> HRMR 10211768SCurtis.Dunham@arm.com {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}}, 10311768SCurtis.Dunham@arm.com {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}, 10411768SCurtis.Dunham@arm.com {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}}, 10511768SCurtis.Dunham@arm.com {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}}, 10611768SCurtis.Dunham@arm.com {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}}, 10711768SCurtis.Dunham@arm.com {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}}, 10811768SCurtis.Dunham@arm.com {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}}, 10911768SCurtis.Dunham@arm.com {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}}, 11011768SCurtis.Dunham@arm.com {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}}, 11111768SCurtis.Dunham@arm.com {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}}, 11211768SCurtis.Dunham@arm.com {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}}, 11311768SCurtis.Dunham@arm.com {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 11411768SCurtis.Dunham@arm.com {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 11510037SARM gem5 Developers {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 11611768SCurtis.Dunham@arm.com {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 11711768SCurtis.Dunham@arm.com {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 11811768SCurtis.Dunham@arm.com {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */ 11911768SCurtis.Dunham@arm.com {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 12010037SARM gem5 Developers {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 12111768SCurtis.Dunham@arm.com {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}}, 12211768SCurtis.Dunham@arm.com {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */ 12311768SCurtis.Dunham@arm.com {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}}, 12411768SCurtis.Dunham@arm.com {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */ 12511768SCurtis.Dunham@arm.com {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 12611768SCurtis.Dunham@arm.com {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */ 12710037SARM gem5 Developers {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 12811768SCurtis.Dunham@arm.com {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */ 12911768SCurtis.Dunham@arm.com {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */ 13011768SCurtis.Dunham@arm.com {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}}, 13111768SCurtis.Dunham@arm.com {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}}, 13211768SCurtis.Dunham@arm.com {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}}, 13311768SCurtis.Dunham@arm.com {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}}, 13411768SCurtis.Dunham@arm.com {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}}, 13511768SCurtis.Dunham@arm.com {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}}, 13611768SCurtis.Dunham@arm.com {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}}, 13711768SCurtis.Dunham@arm.com {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}}, 13811768SCurtis.Dunham@arm.com {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}}, 13911768SCurtis.Dunham@arm.com {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}}, 14011768SCurtis.Dunham@arm.com {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}}, 14111768SCurtis.Dunham@arm.com {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}}, 14211768SCurtis.Dunham@arm.com {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}}, 14311768SCurtis.Dunham@arm.com {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}}, 14411768SCurtis.Dunham@arm.com {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}}, 14511768SCurtis.Dunham@arm.com // DBGDTR_EL0 -> DBGDTR{R or T}Xint 14611768SCurtis.Dunham@arm.com // DBGDTRRX_EL0 -> DBGDTRRXint 14711768SCurtis.Dunham@arm.com // DBGDTRTX_EL0 -> DBGDTRRXint 14811768SCurtis.Dunham@arm.com {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}}, 14911768SCurtis.Dunham@arm.com {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}}, 15011768SCurtis.Dunham@arm.com {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}}, 15111768SCurtis.Dunham@arm.com {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}}, 15211768SCurtis.Dunham@arm.com {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}}, 15311768SCurtis.Dunham@arm.com {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}}, 15411768SCurtis.Dunham@arm.com {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}}, 15511768SCurtis.Dunham@arm.com {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}}, 15611768SCurtis.Dunham@arm.com {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}}, 15711768SCurtis.Dunham@arm.com {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}}, 15811768SCurtis.Dunham@arm.com {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}}, 15911768SCurtis.Dunham@arm.com {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}}, 16011768SCurtis.Dunham@arm.com {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}}, 16111768SCurtis.Dunham@arm.com {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}}, 16211768SCurtis.Dunham@arm.com {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}}, 16311768SCurtis.Dunham@arm.com {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}}, 16411768SCurtis.Dunham@arm.com {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}}, 16511768SCurtis.Dunham@arm.com {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}}, 16611768SCurtis.Dunham@arm.com {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}}, 16711768SCurtis.Dunham@arm.com {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}}, 16811768SCurtis.Dunham@arm.com {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}}, 16911768SCurtis.Dunham@arm.com {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}}, 17011768SCurtis.Dunham@arm.com {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}}, 17111768SCurtis.Dunham@arm.com {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}}, 17211768SCurtis.Dunham@arm.com {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}}, 17311768SCurtis.Dunham@arm.com {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}}, 17411768SCurtis.Dunham@arm.com/* {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}}, 17511768SCurtis.Dunham@arm.com {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}}, 17611768SCurtis.Dunham@arm.com {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}}, 17711768SCurtis.Dunham@arm.com {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}}, 17811768SCurtis.Dunham@arm.com {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}}, 17911768SCurtis.Dunham@arm.com {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}}, 18011768SCurtis.Dunham@arm.com {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}}, 18111768SCurtis.Dunham@arm.com {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}}, 18211768SCurtis.Dunham@arm.com {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}}, 18311768SCurtis.Dunham@arm.com {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}}, 18411768SCurtis.Dunham@arm.com {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}}, 18511768SCurtis.Dunham@arm.com {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */ 18611768SCurtis.Dunham@arm.com {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}}, 18711768SCurtis.Dunham@arm.com {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}}, 18811768SCurtis.Dunham@arm.com// {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}}, 18911768SCurtis.Dunham@arm.com {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}}, 19011768SCurtis.Dunham@arm.com {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}}, 19111768SCurtis.Dunham@arm.com {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}}, 19211768SCurtis.Dunham@arm.com {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}}, 19311768SCurtis.Dunham@arm.com {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}}, 19411768SCurtis.Dunham@arm.com {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}}, 19511768SCurtis.Dunham@arm.com 19611768SCurtis.Dunham@arm.com // from ARM DDI 0487A.i, template text 19711768SCurtis.Dunham@arm.com // "AArch64 System register ___ can be mapped to 19811768SCurtis.Dunham@arm.com // AArch32 System register ___, but this is not 19911768SCurtis.Dunham@arm.com // architecturally mandated." 20011768SCurtis.Dunham@arm.com {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005 20111768SCurtis.Dunham@arm.com // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5) 20211768SCurtis.Dunham@arm.com {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1 20311768SCurtis.Dunham@arm.com {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2 20411768SCurtis.Dunham@arm.com {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3 20510037SARM gem5 Developers}; 20610037SARM gem5 Developers 20710037SARM gem5 Developers 2089384SAndreas.Sandberg@arm.comISA::ISA(Params *p) 20910461SAndreas.Sandberg@ARM.com : SimObject(p), 21010461SAndreas.Sandberg@ARM.com system(NULL), 21111165SRekai.GonzalezAlberquilla@arm.com _decoderFlavour(p->decoderFlavour), 21210461SAndreas.Sandberg@ARM.com pmu(p->pmu), 21310461SAndreas.Sandberg@ARM.com lookUpMiscReg(NUM_MISCREGS, {0,0}) 2149384SAndreas.Sandberg@arm.com{ 21511770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_RST] = 0; 21610037SARM gem5 Developers 21710461SAndreas.Sandberg@ARM.com // Hook up a dummy device if we haven't been configured with a 21810461SAndreas.Sandberg@ARM.com // real PMU. By using a dummy device, we don't need to check that 21910461SAndreas.Sandberg@ARM.com // the PMU exist every time we try to access a PMU register. 22010461SAndreas.Sandberg@ARM.com if (!pmu) 22110461SAndreas.Sandberg@ARM.com pmu = &dummyDevice; 22210461SAndreas.Sandberg@ARM.com 22310609Sandreas.sandberg@arm.com // Give all ISA devices a pointer to this ISA 22410609Sandreas.sandberg@arm.com pmu->setISA(this); 22510609Sandreas.sandberg@arm.com 22610037SARM gem5 Developers system = dynamic_cast<ArmSystem *>(p->system); 22710037SARM gem5 Developers 22810037SARM gem5 Developers // Cache system-level properties 22910037SARM gem5 Developers if (FullSystem && system) { 23011771SCurtis.Dunham@arm.com highestELIs64 = system->highestELIs64(); 23110037SARM gem5 Developers haveSecurity = system->haveSecurity(); 23210037SARM gem5 Developers haveLPAE = system->haveLPAE(); 23310037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 23410037SARM gem5 Developers haveLargeAsid64 = system->haveLargeAsid64(); 23510037SARM gem5 Developers physAddrRange64 = system->physAddrRange64(); 23610037SARM gem5 Developers } else { 23711771SCurtis.Dunham@arm.com highestELIs64 = true; // ArmSystem::highestELIs64 does the same 23810037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 23910037SARM gem5 Developers haveLargeAsid64 = false; 24010037SARM gem5 Developers physAddrRange64 = 32; // dummy value 24110037SARM gem5 Developers } 24210037SARM gem5 Developers 24310037SARM gem5 Developers /** Fill in the miscReg translation table */ 24411768SCurtis.Dunham@arm.com for (auto sw : MiscRegSwitch) { 24511768SCurtis.Dunham@arm.com lookUpMiscReg[sw.index] = sw.entry; 24610037SARM gem5 Developers } 24710037SARM gem5 Developers 24810037SARM gem5 Developers preUnflattenMiscReg(); 24910037SARM gem5 Developers 2509384SAndreas.Sandberg@arm.com clear(); 2519384SAndreas.Sandberg@arm.com} 2529384SAndreas.Sandberg@arm.com 2539384SAndreas.Sandberg@arm.comconst ArmISAParams * 2549384SAndreas.Sandberg@arm.comISA::params() const 2559384SAndreas.Sandberg@arm.com{ 2569384SAndreas.Sandberg@arm.com return dynamic_cast<const Params *>(_params); 2579384SAndreas.Sandberg@arm.com} 2589384SAndreas.Sandberg@arm.com 2597427Sgblack@eecs.umich.eduvoid 2607427Sgblack@eecs.umich.eduISA::clear() 2617427Sgblack@eecs.umich.edu{ 2629385SAndreas.Sandberg@arm.com const Params *p(params()); 2639385SAndreas.Sandberg@arm.com 2647427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 2657427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 26610037SARM gem5 Developers 26710037SARM gem5 Developers // Initialize configurable default values 26810037SARM gem5 Developers miscRegs[MISCREG_MIDR] = p->midr; 26910037SARM gem5 Developers miscRegs[MISCREG_MIDR_EL1] = p->midr; 27010037SARM gem5 Developers miscRegs[MISCREG_VPIDR] = p->midr; 27110037SARM gem5 Developers 27210037SARM gem5 Developers if (FullSystem && system->highestELIs64()) { 27310037SARM gem5 Developers // Initialize AArch64 state 27410037SARM gem5 Developers clear64(p); 27510037SARM gem5 Developers return; 27610037SARM gem5 Developers } 27710037SARM gem5 Developers 27810037SARM gem5 Developers // Initialize AArch32 state... 27910037SARM gem5 Developers 2807427Sgblack@eecs.umich.edu CPSR cpsr = 0; 2817427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 2827427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 2837427Sgblack@eecs.umich.edu updateRegMap(cpsr); 2847427Sgblack@eecs.umich.edu 2857427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 28610037SARM gem5 Developers sctlr.te = (bool) sctlr_rst.te; 28710037SARM gem5 Developers sctlr.nmfi = (bool) sctlr_rst.nmfi; 28810037SARM gem5 Developers sctlr.v = (bool) sctlr_rst.v; 28910037SARM gem5 Developers sctlr.u = 1; 2907427Sgblack@eecs.umich.edu sctlr.xp = 1; 2917427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 2927427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 29310037SARM gem5 Developers sctlr.rao4 = 0xf; // SCTLR[6:3] 29410204SAli.Saidi@ARM.com sctlr.uci = 1; 29510204SAli.Saidi@ARM.com sctlr.dze = 1; 29610037SARM gem5 Developers miscRegs[MISCREG_SCTLR_NS] = sctlr; 2977427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 29810037SARM gem5 Developers miscRegs[MISCREG_HCPTR] = 0; 2997427Sgblack@eecs.umich.edu 30010037SARM gem5 Developers // Start with an event in the mailbox 3017427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 3027427Sgblack@eecs.umich.edu 30310037SARM gem5 Developers // Separate Instruction and Data TLBs 3047427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 3057427Sgblack@eecs.umich.edu 3067427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 3077427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 3087427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 3097427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 3107427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 3117427Sgblack@eecs.umich.edu mvfr0.divide = 1; 3127427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 3137427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 3147427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 3157427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 3167427Sgblack@eecs.umich.edu 3177427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 3187427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 3197427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 3207427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 3217427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 3227427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 3237427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 3247427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 3257427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 3267427Sgblack@eecs.umich.edu 3277436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 3287436Sdam.sunwoo@arm.com 32910037SARM gem5 Developers // @todo: PRRR and NMRR in secure state? 33010037SARM gem5 Developers miscRegs[MISCREG_PRRR_NS] = 3317436Sdam.sunwoo@arm.com (1 << 19) | // 19 3327436Sdam.sunwoo@arm.com (0 << 18) | // 18 3337436Sdam.sunwoo@arm.com (0 << 17) | // 17 3347436Sdam.sunwoo@arm.com (1 << 16) | // 16 3357436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 3367436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 3377436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 3387436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 3397436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 3407436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 3417436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 3427436Sdam.sunwoo@arm.com 0; // 1:0 34310037SARM gem5 Developers miscRegs[MISCREG_NMRR_NS] = 3447436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 3457436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 3467436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 3477436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 3487436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 3497436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 3507436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 3517436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 3527436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 3537436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 3547436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 3557436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 3567436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 3577436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 3587436Sdam.sunwoo@arm.com 0; // 1:0 3597436Sdam.sunwoo@arm.com 3607644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 3618147SAli.Saidi@ARM.com 3629385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 3639385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 3649385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 3659385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 3669385SAndreas.Sandberg@arm.com 3679385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 3689385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 3699385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 3709385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 3719385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 3729385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 3739385SAndreas.Sandberg@arm.com 3749385SAndreas.Sandberg@arm.com miscRegs[MISCREG_FPSID] = p->fpsid; 3759385SAndreas.Sandberg@arm.com 37610037SARM gem5 Developers if (haveLPAE) { 37710037SARM gem5 Developers TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 37810037SARM gem5 Developers ttbcr.eae = 0; 37910037SARM gem5 Developers miscRegs[MISCREG_TTBCR_NS] = ttbcr; 38010037SARM gem5 Developers // Enforce consistency with system-level settings 38110037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 38210037SARM gem5 Developers } 38310037SARM gem5 Developers 38410037SARM gem5 Developers if (haveSecurity) { 38510037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] = sctlr; 38610037SARM gem5 Developers miscRegs[MISCREG_SCR] = 0; 38710037SARM gem5 Developers miscRegs[MISCREG_VBAR_S] = 0; 38810037SARM gem5 Developers } else { 38910037SARM gem5 Developers // we're always non-secure 39010037SARM gem5 Developers miscRegs[MISCREG_SCR] = 1; 39110037SARM gem5 Developers } 3928147SAli.Saidi@ARM.com 3937427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 3947427Sgblack@eecs.umich.edu} 3957427Sgblack@eecs.umich.edu 39610037SARM gem5 Developersvoid 39710037SARM gem5 DevelopersISA::clear64(const ArmISAParams *p) 39810037SARM gem5 Developers{ 39910037SARM gem5 Developers CPSR cpsr = 0; 40010037SARM gem5 Developers Addr rvbar = system->resetAddr64(); 40110037SARM gem5 Developers switch (system->highestEL()) { 40210037SARM gem5 Developers // Set initial EL to highest implemented EL using associated stack 40310037SARM gem5 Developers // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 40410037SARM gem5 Developers // value 40510037SARM gem5 Developers case EL3: 40610037SARM gem5 Developers cpsr.mode = MODE_EL3H; 40710037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL3] = rvbar; 40810037SARM gem5 Developers break; 40910037SARM gem5 Developers case EL2: 41010037SARM gem5 Developers cpsr.mode = MODE_EL2H; 41110037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL2] = rvbar; 41210037SARM gem5 Developers break; 41310037SARM gem5 Developers case EL1: 41410037SARM gem5 Developers cpsr.mode = MODE_EL1H; 41510037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL1] = rvbar; 41610037SARM gem5 Developers break; 41710037SARM gem5 Developers default: 41810037SARM gem5 Developers panic("Invalid highest implemented exception level"); 41910037SARM gem5 Developers break; 42010037SARM gem5 Developers } 42110037SARM gem5 Developers 42210037SARM gem5 Developers // Initialize rest of CPSR 42310037SARM gem5 Developers cpsr.daif = 0xf; // Mask all interrupts 42410037SARM gem5 Developers cpsr.ss = 0; 42510037SARM gem5 Developers cpsr.il = 0; 42610037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 42710037SARM gem5 Developers updateRegMap(cpsr); 42810037SARM gem5 Developers 42910037SARM gem5 Developers // Initialize other control registers 43010037SARM gem5 Developers miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 43110037SARM gem5 Developers if (haveSecurity) { 43211770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 43310037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 43411574SCurtis.Dunham@arm.com } else if (haveVirtualization) { 43511770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL2 (by mapping) 43611770SCurtis.Dunham@arm.com miscRegs[MISCREG_HSCTLR] = 0x30c50830; 43710037SARM gem5 Developers } else { 43811770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL1 (by mapping) 43911770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 44010037SARM gem5 Developers // Always non-secure 44110037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 1; 44210037SARM gem5 Developers } 44310037SARM gem5 Developers 44410037SARM gem5 Developers // Initialize configurable id registers 44510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 44610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 44710461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 44810461SAndreas.Sandberg@ARM.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 44910461SAndreas.Sandberg@ARM.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 45010461SAndreas.Sandberg@ARM.com 45110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 45210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 45310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 45410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 45510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 45610037SARM gem5 Developers 45710461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0_EL1] = 45810461SAndreas.Sandberg@ARM.com (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 45910461SAndreas.Sandberg@ARM.com 46010461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 46110461SAndreas.Sandberg@ARM.com 46210037SARM gem5 Developers // Enforce consistency with system-level settings... 46310037SARM gem5 Developers 46410037SARM gem5 Developers // EL3 46510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 46610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 46711574SCurtis.Dunham@arm.com haveSecurity ? 0x2 : 0x0); 46810037SARM gem5 Developers // EL2 46910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 47010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 47111574SCurtis.Dunham@arm.com haveVirtualization ? 0x2 : 0x0); 47210037SARM gem5 Developers // Large ASID support 47310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 47410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 47510037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 47610037SARM gem5 Developers // Physical address size 47710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 47810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 47910037SARM gem5 Developers encodePhysAddrRange64(physAddrRange64)); 48010037SARM gem5 Developers} 48110037SARM gem5 Developers 4827405SAli.Saidi@ARM.comMiscReg 48310035Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg) const 4847405SAli.Saidi@ARM.com{ 4857405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 4867614Sminkyu.jeong@arm.com 48711771SCurtis.Dunham@arm.com auto regs = getMiscIndices(misc_reg); 48811771SCurtis.Dunham@arm.com int lower = regs.first, upper = regs.second; 48911771SCurtis.Dunham@arm.com return !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 49011771SCurtis.Dunham@arm.com |(miscRegs[upper] << 32)); 4917405SAli.Saidi@ARM.com} 4927405SAli.Saidi@ARM.com 4937405SAli.Saidi@ARM.com 4947405SAli.Saidi@ARM.comMiscReg 4957405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 4967405SAli.Saidi@ARM.com{ 49710037SARM gem5 Developers CPSR cpsr = 0; 49810037SARM gem5 Developers PCState pc = 0; 49910037SARM gem5 Developers SCR scr = 0; 5009050Schander.sudanthi@arm.com 5017405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 50210037SARM gem5 Developers cpsr = miscRegs[misc_reg]; 50310037SARM gem5 Developers pc = tc->pcState(); 5047720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 5057720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 5067405SAli.Saidi@ARM.com return cpsr; 5077405SAli.Saidi@ARM.com } 5087757SAli.Saidi@ARM.com 50910037SARM gem5 Developers#ifndef NDEBUG 51010037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 51110037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 51210037SARM gem5 Developers warn("Unimplemented system register %s read.\n", 51310037SARM gem5 Developers miscRegName[misc_reg]); 51410037SARM gem5 Developers else 51510037SARM gem5 Developers panic("Unimplemented system register %s read.\n", 51610037SARM gem5 Developers miscRegName[misc_reg]); 51710037SARM gem5 Developers } 51810037SARM gem5 Developers#endif 51910037SARM gem5 Developers 52010037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 52110037SARM gem5 Developers case MISCREG_HCR: 52210037SARM gem5 Developers { 52310037SARM gem5 Developers if (!haveVirtualization) 52410037SARM gem5 Developers return 0; 52510037SARM gem5 Developers else 52610037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HCR); 52710037SARM gem5 Developers } 52810037SARM gem5 Developers case MISCREG_CPACR: 52910037SARM gem5 Developers { 53010037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 53110037SARM gem5 Developers CPACR cpacrMask = 0; 53210037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 53310037SARM gem5 Developers // be readable? (straight copy from the write code) 53410037SARM gem5 Developers cpacrMask.cp10 = ones; 53510037SARM gem5 Developers cpacrMask.cp11 = ones; 53610037SARM gem5 Developers cpacrMask.asedis = ones; 53710037SARM gem5 Developers 53810037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 53910037SARM gem5 Developers if (haveSecurity) { 54010037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 54110037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 54210037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON)) { 54310037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 54410037SARM gem5 Developers // NB: Skipping the full loop, here 54510037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 54610037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 54710037SARM gem5 Developers } 54810037SARM gem5 Developers } 54910037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 55010037SARM gem5 Developers val &= cpacrMask; 55110037SARM gem5 Developers DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 55210037SARM gem5 Developers miscRegName[misc_reg], val); 55310037SARM gem5 Developers return val; 55410037SARM gem5 Developers } 5558284SAli.Saidi@ARM.com case MISCREG_MPIDR: 55610037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 55710037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 55810037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 55910037SARM gem5 Developers return getMPIDR(system, tc); 5609050Schander.sudanthi@arm.com } else { 56110037SARM gem5 Developers return readMiscReg(MISCREG_VMPIDR, tc); 56210037SARM gem5 Developers } 56310037SARM gem5 Developers break; 56410037SARM gem5 Developers case MISCREG_MPIDR_EL1: 56510037SARM gem5 Developers // @todo in the absence of v8 virtualization support just return MPIDR_EL1 56610037SARM gem5 Developers return getMPIDR(system, tc) & 0xffffffff; 56710037SARM gem5 Developers case MISCREG_VMPIDR: 56810037SARM gem5 Developers // top bit defined as RES1 56910037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 57010037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 57110037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 57210037SARM gem5 Developers case MISCREG_MIDR: 57310037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 57410037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 57510037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 57610037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 57710037SARM gem5 Developers } else { 57810037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_VPIDR); 5799050Schander.sudanthi@arm.com } 5808284SAli.Saidi@ARM.com break; 58110037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 58210037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 58310037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 58410037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 58510037SARM gem5 Developers case MISCREG_TCMTR: // No TCM's 58610037SARM gem5 Developers return 0; 58710037SARM gem5 Developers 5887405SAli.Saidi@ARM.com case MISCREG_CLIDR: 5897731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 5908468Swade.walker@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 5918468Swade.walker@arm.com "ARM implementations.\n"); 5928468Swade.walker@arm.com return 0x00200000; 5937405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 5947731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 5957405SAli.Saidi@ARM.com "always reads as 0.\n"); 5967405SAli.Saidi@ARM.com break; 59711809Sbaz21@cam.ac.uk case MISCREG_CTR: // AArch32, ARMv7, top bit set 59811809Sbaz21@cam.ac.uk case MISCREG_CTR_EL0: // AArch64 5999130Satgutier@umich.edu { 6009130Satgutier@umich.edu //all caches have the same line size in gem5 6019130Satgutier@umich.edu //4 byte words in ARM 6029130Satgutier@umich.edu unsigned lineSizeWords = 6039814Sandreas.hansson@arm.com tc->getSystemPtr()->cacheLineSize() / 4; 6049130Satgutier@umich.edu unsigned log2LineSizeWords = 0; 6059130Satgutier@umich.edu 6069130Satgutier@umich.edu while (lineSizeWords >>= 1) { 6079130Satgutier@umich.edu ++log2LineSizeWords; 6089130Satgutier@umich.edu } 6099130Satgutier@umich.edu 6109130Satgutier@umich.edu CTR ctr = 0; 6119130Satgutier@umich.edu //log2 of minimun i-cache line size (words) 6129130Satgutier@umich.edu ctr.iCacheLineSize = log2LineSizeWords; 6139130Satgutier@umich.edu //b11 - gem5 uses pipt 6149130Satgutier@umich.edu ctr.l1IndexPolicy = 0x3; 6159130Satgutier@umich.edu //log2 of minimum d-cache line size (words) 6169130Satgutier@umich.edu ctr.dCacheLineSize = log2LineSizeWords; 6179130Satgutier@umich.edu //log2 of max reservation size (words) 6189130Satgutier@umich.edu ctr.erg = log2LineSizeWords; 6199130Satgutier@umich.edu //log2 of max writeback size (words) 6209130Satgutier@umich.edu ctr.cwg = log2LineSizeWords; 6219130Satgutier@umich.edu //b100 - gem5 format is ARMv7 6229130Satgutier@umich.edu ctr.format = 0x4; 6239130Satgutier@umich.edu 6249130Satgutier@umich.edu return ctr; 6259130Satgutier@umich.edu } 6267583SAli.Saidi@arm.com case MISCREG_ACTLR: 6277583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 6287583SAli.Saidi@arm.com break; 62910461SAndreas.Sandberg@ARM.com 63010461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 63110461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 63210461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 63310461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 63410461SAndreas.Sandberg@ARM.com return pmu->readMiscReg(misc_reg); 63510461SAndreas.Sandberg@ARM.com 6368302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 6378302SAli.Saidi@ARM.com panic("shouldn't be reading this register seperately\n"); 6387783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 6397783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 6407783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 6417783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 64210037SARM gem5 Developers case MISCREG_FPSR: 64310037SARM gem5 Developers { 64410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 64510037SARM gem5 Developers FPSCR fpscrMask = 0; 64610037SARM gem5 Developers fpscrMask.ioc = ones; 64710037SARM gem5 Developers fpscrMask.dzc = ones; 64810037SARM gem5 Developers fpscrMask.ofc = ones; 64910037SARM gem5 Developers fpscrMask.ufc = ones; 65010037SARM gem5 Developers fpscrMask.ixc = ones; 65110037SARM gem5 Developers fpscrMask.idc = ones; 65210037SARM gem5 Developers fpscrMask.qc = ones; 65310037SARM gem5 Developers fpscrMask.v = ones; 65410037SARM gem5 Developers fpscrMask.c = ones; 65510037SARM gem5 Developers fpscrMask.z = ones; 65610037SARM gem5 Developers fpscrMask.n = ones; 65710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 65810037SARM gem5 Developers } 65910037SARM gem5 Developers case MISCREG_FPCR: 66010037SARM gem5 Developers { 66110037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 66210037SARM gem5 Developers FPSCR fpscrMask = 0; 66310037SARM gem5 Developers fpscrMask.ioe = ones; 66410037SARM gem5 Developers fpscrMask.dze = ones; 66510037SARM gem5 Developers fpscrMask.ofe = ones; 66610037SARM gem5 Developers fpscrMask.ufe = ones; 66710037SARM gem5 Developers fpscrMask.ixe = ones; 66810037SARM gem5 Developers fpscrMask.ide = ones; 66910037SARM gem5 Developers fpscrMask.len = ones; 67010037SARM gem5 Developers fpscrMask.stride = ones; 67110037SARM gem5 Developers fpscrMask.rMode = ones; 67210037SARM gem5 Developers fpscrMask.fz = ones; 67310037SARM gem5 Developers fpscrMask.dn = ones; 67410037SARM gem5 Developers fpscrMask.ahp = ones; 67510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 67610037SARM gem5 Developers } 67710037SARM gem5 Developers case MISCREG_NZCV: 67810037SARM gem5 Developers { 67910037SARM gem5 Developers CPSR cpsr = 0; 68010338SCurtis.Dunham@arm.com cpsr.nz = tc->readCCReg(CCREG_NZ); 68110338SCurtis.Dunham@arm.com cpsr.c = tc->readCCReg(CCREG_C); 68210338SCurtis.Dunham@arm.com cpsr.v = tc->readCCReg(CCREG_V); 68310037SARM gem5 Developers return cpsr; 68410037SARM gem5 Developers } 68510037SARM gem5 Developers case MISCREG_DAIF: 68610037SARM gem5 Developers { 68710037SARM gem5 Developers CPSR cpsr = 0; 68810037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 68910037SARM gem5 Developers return cpsr; 69010037SARM gem5 Developers } 69110037SARM gem5 Developers case MISCREG_SP_EL0: 69210037SARM gem5 Developers { 69310037SARM gem5 Developers return tc->readIntReg(INTREG_SP0); 69410037SARM gem5 Developers } 69510037SARM gem5 Developers case MISCREG_SP_EL1: 69610037SARM gem5 Developers { 69710037SARM gem5 Developers return tc->readIntReg(INTREG_SP1); 69810037SARM gem5 Developers } 69910037SARM gem5 Developers case MISCREG_SP_EL2: 70010037SARM gem5 Developers { 70110037SARM gem5 Developers return tc->readIntReg(INTREG_SP2); 70210037SARM gem5 Developers } 70310037SARM gem5 Developers case MISCREG_SPSEL: 70410037SARM gem5 Developers { 70510037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0x1; 70610037SARM gem5 Developers } 70710037SARM gem5 Developers case MISCREG_CURRENTEL: 70810037SARM gem5 Developers { 70910037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0xc; 71010037SARM gem5 Developers } 7118549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 7128868SMatt.Horsnell@arm.com { 7138868SMatt.Horsnell@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 7148868SMatt.Horsnell@arm.com L2CTLR l2ctlr = 0; 7158868SMatt.Horsnell@arm.com // b00:1CPU to b11:4CPUs 7168868SMatt.Horsnell@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 7178868SMatt.Horsnell@arm.com return l2ctlr; 7188868SMatt.Horsnell@arm.com } 7198868SMatt.Horsnell@arm.com case MISCREG_DBGDIDR: 7208868SMatt.Horsnell@arm.com /* For now just implement the version number. 72110461SAndreas.Sandberg@ARM.com * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 7228868SMatt.Horsnell@arm.com */ 72310461SAndreas.Sandberg@ARM.com return 0x5 << 16; 72410037SARM gem5 Developers case MISCREG_DBGDSCRint: 7258868SMatt.Horsnell@arm.com return 0; 72610037SARM gem5 Developers case MISCREG_ISR: 72711150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 72810037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR), 72910037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 73010037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR)); 73110037SARM gem5 Developers case MISCREG_ISR_EL1: 73211150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 73310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR_EL2), 73410037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 73510037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR_EL3)); 73610037SARM gem5 Developers case MISCREG_DCZID_EL0: 73710037SARM gem5 Developers return 0x04; // DC ZVA clear 64-byte chunks 73810037SARM gem5 Developers case MISCREG_HCPTR: 73910037SARM gem5 Developers { 74010037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(misc_reg); 74110037SARM gem5 Developers // The trap bit associated with CP14 is defined as RAZ 74210037SARM gem5 Developers val &= ~(1 << 14); 74310037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 74410037SARM gem5 Developers // HCPTR is RAO/WI 74510037SARM gem5 Developers bool secure_lookup = haveSecurity && 74610037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 74710037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 74810037SARM gem5 Developers if (!secure_lookup) { 74910037SARM gem5 Developers MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 75010037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 75110037SARM gem5 Developers } 75210037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 75310037SARM gem5 Developers val |= 0x33FF; 75410037SARM gem5 Developers return (val); 75510037SARM gem5 Developers } 75610037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 75710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 75810037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 75910037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 76010037SARM gem5 Developers case MISCREG_HVBAR: // bottom bits reserved 76110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 76211769SCurtis.Dunham@arm.com case MISCREG_SCTLR: 76311769SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 76410037SARM gem5 Developers case MISCREG_SCTLR_EL1: 76511770SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 76611770SCurtis.Dunham@arm.com case MISCREG_SCTLR_EL2: 76710037SARM gem5 Developers case MISCREG_SCTLR_EL3: 76811770SCurtis.Dunham@arm.com case MISCREG_HSCTLR: 76911769SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 77010844Sandreas.sandberg@arm.com 77111772SCurtis.Dunham@arm.com case MISCREG_ID_PFR0: 77211772SCurtis.Dunham@arm.com // !ThumbEE | !Jazelle | Thumb | ARM 77311772SCurtis.Dunham@arm.com return 0x00000031; 77411772SCurtis.Dunham@arm.com case MISCREG_ID_PFR1: 77511774SCurtis.Dunham@arm.com { // Timer | Virti | !M Profile | TrustZone | ARMv4 77611774SCurtis.Dunham@arm.com bool haveTimer = (system->getGenericTimer() != NULL); 77711774SCurtis.Dunham@arm.com return 0x00000001 77811774SCurtis.Dunham@arm.com | (haveSecurity ? 0x00000010 : 0x0) 77911774SCurtis.Dunham@arm.com | (haveVirtualization ? 0x00001000 : 0x0) 78011774SCurtis.Dunham@arm.com | (haveTimer ? 0x00010000 : 0x0); 78111774SCurtis.Dunham@arm.com } 78211773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR0_EL1: 78311773SCurtis.Dunham@arm.com return 0x0000000000000002 // AArch{64,32} supported at EL0 78411773SCurtis.Dunham@arm.com | 0x0000000000000020 // EL1 78511773SCurtis.Dunham@arm.com | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 78611773SCurtis.Dunham@arm.com | (haveSecurity ? 0x0000000000002000 : 0); // EL3 78711773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR1_EL1: 78811773SCurtis.Dunham@arm.com return 0; // bits [63:0] RES0 (reserved for future use) 78911772SCurtis.Dunham@arm.com 79010037SARM gem5 Developers // Generic Timer registers 79110844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 79210844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 79310844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 79410844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 79510844Sandreas.sandberg@arm.com return getGenericTimer(tc).readMiscReg(misc_reg); 79610844Sandreas.sandberg@arm.com 79710188Sgeoffrey.blake@arm.com default: 79810037SARM gem5 Developers break; 79910037SARM gem5 Developers 8007405SAli.Saidi@ARM.com } 8017405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 8027405SAli.Saidi@ARM.com} 8037405SAli.Saidi@ARM.com 8047405SAli.Saidi@ARM.comvoid 8057405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 8067405SAli.Saidi@ARM.com{ 8077405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 8087614Sminkyu.jeong@arm.com 80911771SCurtis.Dunham@arm.com auto regs = getMiscIndices(misc_reg); 81011771SCurtis.Dunham@arm.com int lower = regs.first, upper = regs.second; 81111771SCurtis.Dunham@arm.com if (upper > 0) { 81211771SCurtis.Dunham@arm.com miscRegs[lower] = bits(val, 31, 0); 81311771SCurtis.Dunham@arm.com miscRegs[upper] = bits(val, 63, 32); 81410037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 81511771SCurtis.Dunham@arm.com misc_reg, lower, upper, val); 81610037SARM gem5 Developers } else { 81711771SCurtis.Dunham@arm.com miscRegs[lower] = val; 81810037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 81911771SCurtis.Dunham@arm.com misc_reg, lower, val); 82010037SARM gem5 Developers } 8217405SAli.Saidi@ARM.com} 8227405SAli.Saidi@ARM.com 8237405SAli.Saidi@ARM.comvoid 8247405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 8257405SAli.Saidi@ARM.com{ 8267749SAli.Saidi@ARM.com 8277405SAli.Saidi@ARM.com MiscReg newVal = val; 8288284SAli.Saidi@ARM.com int x; 82910037SARM gem5 Developers bool secure_lookup; 83010037SARM gem5 Developers bool hyp; 8318284SAli.Saidi@ARM.com System *sys; 8328284SAli.Saidi@ARM.com ThreadContext *oc; 83310037SARM gem5 Developers uint8_t target_el; 83410037SARM gem5 Developers uint16_t asid; 83510037SARM gem5 Developers SCR scr; 8368284SAli.Saidi@ARM.com 8377405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 8387405SAli.Saidi@ARM.com updateRegMap(val); 8397749SAli.Saidi@ARM.com 8407749SAli.Saidi@ARM.com 8417749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 8427749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 8437405SAli.Saidi@ARM.com CPSR cpsr = val; 8447749SAli.Saidi@ARM.com if (old_mode != cpsr.mode) { 8457749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 8467749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 8477749SAli.Saidi@ARM.com } 8487749SAli.Saidi@ARM.com 8497614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 8507614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 8517720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 8527720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 8537720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 8548887Sgeoffrey.blake@arm.com 8558887Sgeoffrey.blake@arm.com // Follow slightly different semantics if a CheckerCPU object 8568887Sgeoffrey.blake@arm.com // is connected 8578887Sgeoffrey.blake@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 8588887Sgeoffrey.blake@arm.com if (checker) { 8598887Sgeoffrey.blake@arm.com tc->pcStateNoRecord(pc); 8608887Sgeoffrey.blake@arm.com } else { 8618887Sgeoffrey.blake@arm.com tc->pcState(pc); 8628887Sgeoffrey.blake@arm.com } 8637408Sgblack@eecs.umich.edu } else { 86410037SARM gem5 Developers#ifndef NDEBUG 86510037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 86610037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 86710037SARM gem5 Developers warn("Unimplemented system register %s write with %#x.\n", 86810037SARM gem5 Developers miscRegName[misc_reg], val); 86910037SARM gem5 Developers else 87010037SARM gem5 Developers panic("Unimplemented system register %s write with %#x.\n", 87110037SARM gem5 Developers miscRegName[misc_reg], val); 87210037SARM gem5 Developers } 87310037SARM gem5 Developers#endif 87410037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 8757408Sgblack@eecs.umich.edu case MISCREG_CPACR: 8767408Sgblack@eecs.umich.edu { 8778206SWilliam.Wang@arm.com 8788206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 8798206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 8808206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 8818206SWilliam.Wang@arm.com // be writable 8828206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 8838206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 8848206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 88510037SARM gem5 Developers 88610037SARM gem5 Developers // Security Extensions may limit the writability of CPACR 88710037SARM gem5 Developers if (haveSecurity) { 88810037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 88910037SARM gem5 Developers CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 89010037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON)) { 89110037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 89210037SARM gem5 Developers // NB: Skipping the full loop, here 89310037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 89410037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 89510037SARM gem5 Developers } 89610037SARM gem5 Developers } 89710037SARM gem5 Developers 89810037SARM gem5 Developers MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 8998206SWilliam.Wang@arm.com newVal &= cpacrMask; 90010037SARM gem5 Developers newVal |= old_val & ~cpacrMask; 90110037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 90210037SARM gem5 Developers miscRegName[misc_reg], newVal); 90310037SARM gem5 Developers } 90410037SARM gem5 Developers break; 90510037SARM gem5 Developers case MISCREG_CPACR_EL1: 90610037SARM gem5 Developers { 90710037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 90810037SARM gem5 Developers CPACR cpacrMask = 0; 90910037SARM gem5 Developers cpacrMask.tta = ones; 91010037SARM gem5 Developers cpacrMask.fpen = ones; 91110037SARM gem5 Developers newVal &= cpacrMask; 91210037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 91310037SARM gem5 Developers miscRegName[misc_reg], newVal); 91410037SARM gem5 Developers } 91510037SARM gem5 Developers break; 91610037SARM gem5 Developers case MISCREG_CPTR_EL2: 91710037SARM gem5 Developers { 91810037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 91910037SARM gem5 Developers CPTR cptrMask = 0; 92010037SARM gem5 Developers cptrMask.tcpac = ones; 92110037SARM gem5 Developers cptrMask.tta = ones; 92210037SARM gem5 Developers cptrMask.tfp = ones; 92310037SARM gem5 Developers newVal &= cptrMask; 92410037SARM gem5 Developers cptrMask = 0; 92510037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 92610037SARM gem5 Developers cptrMask.res1_9_0_el2 = ones; 92710037SARM gem5 Developers newVal |= cptrMask; 92810037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 92910037SARM gem5 Developers miscRegName[misc_reg], newVal); 93010037SARM gem5 Developers } 93110037SARM gem5 Developers break; 93210037SARM gem5 Developers case MISCREG_CPTR_EL3: 93310037SARM gem5 Developers { 93410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 93510037SARM gem5 Developers CPTR cptrMask = 0; 93610037SARM gem5 Developers cptrMask.tcpac = ones; 93710037SARM gem5 Developers cptrMask.tta = ones; 93810037SARM gem5 Developers cptrMask.tfp = ones; 93910037SARM gem5 Developers newVal &= cptrMask; 9408206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 9418206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 9427408Sgblack@eecs.umich.edu } 9437408Sgblack@eecs.umich.edu break; 9447408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 9457731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 9468206SWilliam.Wang@arm.com return; 94710037SARM gem5 Developers 94810037SARM gem5 Developers case MISCREG_DC_ZVA_Xt: 94910037SARM gem5 Developers warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 95010037SARM gem5 Developers return; 95110037SARM gem5 Developers 9527408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 9537408Sgblack@eecs.umich.edu { 9547408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 9557408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 9567408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 9577408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 9587408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 9597408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 9607408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 9617408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 96210037SARM gem5 Developers fpscrMask.ioe = ones; 96310037SARM gem5 Developers fpscrMask.dze = ones; 96410037SARM gem5 Developers fpscrMask.ofe = ones; 96510037SARM gem5 Developers fpscrMask.ufe = ones; 96610037SARM gem5 Developers fpscrMask.ixe = ones; 96710037SARM gem5 Developers fpscrMask.ide = ones; 9687408Sgblack@eecs.umich.edu fpscrMask.len = ones; 9697408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 9707408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 9717408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 9727408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 9737408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 9747408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 9757408Sgblack@eecs.umich.edu fpscrMask.v = ones; 9767408Sgblack@eecs.umich.edu fpscrMask.c = ones; 9777408Sgblack@eecs.umich.edu fpscrMask.z = ones; 9787408Sgblack@eecs.umich.edu fpscrMask.n = ones; 9797408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 98010037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 98110037SARM gem5 Developers ~(uint32_t)fpscrMask); 9829377Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(newVal); 9837408Sgblack@eecs.umich.edu } 9847408Sgblack@eecs.umich.edu break; 98510037SARM gem5 Developers case MISCREG_FPSR: 98610037SARM gem5 Developers { 98710037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 98810037SARM gem5 Developers FPSCR fpscrMask = 0; 98910037SARM gem5 Developers fpscrMask.ioc = ones; 99010037SARM gem5 Developers fpscrMask.dzc = ones; 99110037SARM gem5 Developers fpscrMask.ofc = ones; 99210037SARM gem5 Developers fpscrMask.ufc = ones; 99310037SARM gem5 Developers fpscrMask.ixc = ones; 99410037SARM gem5 Developers fpscrMask.idc = ones; 99510037SARM gem5 Developers fpscrMask.qc = ones; 99610037SARM gem5 Developers fpscrMask.v = ones; 99710037SARM gem5 Developers fpscrMask.c = ones; 99810037SARM gem5 Developers fpscrMask.z = ones; 99910037SARM gem5 Developers fpscrMask.n = ones; 100010037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 100110037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 100210037SARM gem5 Developers ~(uint32_t)fpscrMask); 100310037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 100410037SARM gem5 Developers } 100510037SARM gem5 Developers break; 100610037SARM gem5 Developers case MISCREG_FPCR: 100710037SARM gem5 Developers { 100810037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 100910037SARM gem5 Developers FPSCR fpscrMask = 0; 101010037SARM gem5 Developers fpscrMask.ioe = ones; 101110037SARM gem5 Developers fpscrMask.dze = ones; 101210037SARM gem5 Developers fpscrMask.ofe = ones; 101310037SARM gem5 Developers fpscrMask.ufe = ones; 101410037SARM gem5 Developers fpscrMask.ixe = ones; 101510037SARM gem5 Developers fpscrMask.ide = ones; 101610037SARM gem5 Developers fpscrMask.len = ones; 101710037SARM gem5 Developers fpscrMask.stride = ones; 101810037SARM gem5 Developers fpscrMask.rMode = ones; 101910037SARM gem5 Developers fpscrMask.fz = ones; 102010037SARM gem5 Developers fpscrMask.dn = ones; 102110037SARM gem5 Developers fpscrMask.ahp = ones; 102210037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 102310037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 102410037SARM gem5 Developers ~(uint32_t)fpscrMask); 102510037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 102610037SARM gem5 Developers } 102710037SARM gem5 Developers break; 10288302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 10298302SAli.Saidi@ARM.com { 10308302SAli.Saidi@ARM.com assert(!(newVal & ~CpsrMaskQ)); 103110037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 10328302SAli.Saidi@ARM.com misc_reg = MISCREG_CPSR; 10338302SAli.Saidi@ARM.com } 10348302SAli.Saidi@ARM.com break; 10357783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 10367783SGiacomo.Gabrielli@arm.com { 103710037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 103810037SARM gem5 Developers (newVal & FpscrQcMask); 10397783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 10407783SGiacomo.Gabrielli@arm.com } 10417783SGiacomo.Gabrielli@arm.com break; 10427783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 10437783SGiacomo.Gabrielli@arm.com { 104410037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 104510037SARM gem5 Developers (newVal & FpscrExcMask); 10467783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 10477783SGiacomo.Gabrielli@arm.com } 10487783SGiacomo.Gabrielli@arm.com break; 10497408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 10507408Sgblack@eecs.umich.edu { 10518206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 10528206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 10537408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 10547408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 105510037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 10567408Sgblack@eecs.umich.edu } 10577408Sgblack@eecs.umich.edu break; 105810037SARM gem5 Developers case MISCREG_HCR: 105910037SARM gem5 Developers { 106010037SARM gem5 Developers if (!haveVirtualization) 106110037SARM gem5 Developers return; 106210037SARM gem5 Developers } 106310037SARM gem5 Developers break; 106410037SARM gem5 Developers case MISCREG_IFSR: 106510037SARM gem5 Developers { 106610037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.96 106710037SARM gem5 Developers const uint32_t ifsrMask = 106810037SARM gem5 Developers mask(31, 13) | mask(11, 11) | mask(8, 6); 106910037SARM gem5 Developers newVal = newVal & ~ifsrMask; 107010037SARM gem5 Developers } 107110037SARM gem5 Developers break; 107210037SARM gem5 Developers case MISCREG_DFSR: 107310037SARM gem5 Developers { 107410037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.52 107510037SARM gem5 Developers const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 107610037SARM gem5 Developers newVal = newVal & ~dfsrMask; 107710037SARM gem5 Developers } 107810037SARM gem5 Developers break; 107910037SARM gem5 Developers case MISCREG_AMAIR0: 108010037SARM gem5 Developers case MISCREG_AMAIR1: 108110037SARM gem5 Developers { 108210037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 108310037SARM gem5 Developers // Valid only with LPAE 108410037SARM gem5 Developers if (!haveLPAE) 108510037SARM gem5 Developers return; 108610037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 108710037SARM gem5 Developers } 108810037SARM gem5 Developers break; 108910037SARM gem5 Developers case MISCREG_SCR: 109010037SARM gem5 Developers tc->getITBPtr()->invalidateMiscReg(); 109110037SARM gem5 Developers tc->getDTBPtr()->invalidateMiscReg(); 109210037SARM gem5 Developers break; 10937408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 10947408Sgblack@eecs.umich.edu { 10957408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 109610037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 109711769SCurtis.Dunham@arm.com MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns) 109811769SCurtis.Dunham@arm.com ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS; 109910037SARM gem5 Developers SCTLR sctlr = miscRegs[sctlr_idx]; 11007408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 110110037SARM gem5 Developers new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 110210037SARM gem5 Developers miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 11037749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 11047749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 11057408Sgblack@eecs.umich.edu } 11069385SAndreas.Sandberg@arm.com case MISCREG_MIDR: 11079385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR0: 11089385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR1: 110910461SAndreas.Sandberg@ARM.com case MISCREG_ID_DFR0: 11109385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR0: 11119385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR1: 11129385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR2: 11139385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR3: 11149385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR0: 11159385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR1: 11169385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR2: 11179385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR3: 11189385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR4: 11199385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR5: 11209385SAndreas.Sandberg@arm.com 11219385SAndreas.Sandberg@arm.com case MISCREG_MPIDR: 11229385SAndreas.Sandberg@arm.com case MISCREG_FPSID: 11237408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 11247408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 11257408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 112610037SARM gem5 Developers 112710037SARM gem5 Developers case MISCREG_ID_AA64AFR0_EL1: 112810037SARM gem5 Developers case MISCREG_ID_AA64AFR1_EL1: 112910037SARM gem5 Developers case MISCREG_ID_AA64DFR0_EL1: 113010037SARM gem5 Developers case MISCREG_ID_AA64DFR1_EL1: 113110037SARM gem5 Developers case MISCREG_ID_AA64ISAR0_EL1: 113210037SARM gem5 Developers case MISCREG_ID_AA64ISAR1_EL1: 113310037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 113410037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 113510037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 113610037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 11379385SAndreas.Sandberg@arm.com // ID registers are constants. 11387408Sgblack@eecs.umich.edu return; 11399385SAndreas.Sandberg@arm.com 114010037SARM gem5 Developers // TLBI all entries, EL0&1 inner sharable (ignored) 11417408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 114210037SARM gem5 Developers case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 114310037SARM gem5 Developers assert32(tc); 114410037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 114510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 114610037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 11478284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 11488284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 11498284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 11508284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 115110037SARM gem5 Developers oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 115210037SARM gem5 Developers oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 11538887Sgeoffrey.blake@arm.com 11548887Sgeoffrey.blake@arm.com // If CheckerCPU is connected, need to notify it of a flush 11558887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 11568733Sgeoffrey.blake@arm.com if (checker) { 115710037SARM gem5 Developers checker->getITBPtr()->flushAllSecurity(secure_lookup, 115810037SARM gem5 Developers target_el); 115910037SARM gem5 Developers checker->getDTBPtr()->flushAllSecurity(secure_lookup, 116010037SARM gem5 Developers target_el); 11618733Sgeoffrey.blake@arm.com } 11628284SAli.Saidi@ARM.com } 11637408Sgblack@eecs.umich.edu return; 116410037SARM gem5 Developers // TLBI all entries, EL0&1, instruction side 11657408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 116610037SARM gem5 Developers assert32(tc); 116710037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 116810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 116910037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 117010037SARM gem5 Developers tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 11717408Sgblack@eecs.umich.edu return; 117210037SARM gem5 Developers // TLBI all entries, EL0&1, data side 11737408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 117410037SARM gem5 Developers assert32(tc); 117510037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 117610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 117710037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 117810037SARM gem5 Developers tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 11797408Sgblack@eecs.umich.edu return; 118010037SARM gem5 Developers // TLBI based on VA, EL0&1 inner sharable (ignored) 11817408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 11827408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 118310037SARM gem5 Developers assert32(tc); 118410037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 118510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 118610037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 11878284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 11888284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 11898284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 11908284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 11918284SAli.Saidi@ARM.com oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 119210037SARM gem5 Developers bits(newVal, 7,0), 119310037SARM gem5 Developers secure_lookup, target_el); 11948284SAli.Saidi@ARM.com oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 119510037SARM gem5 Developers bits(newVal, 7,0), 119610037SARM gem5 Developers secure_lookup, target_el); 11978887Sgeoffrey.blake@arm.com 11988887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 11998733Sgeoffrey.blake@arm.com if (checker) { 12008733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 120110037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 12028733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 120310037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 12048733Sgeoffrey.blake@arm.com } 12058284SAli.Saidi@ARM.com } 12067408Sgblack@eecs.umich.edu return; 120710037SARM gem5 Developers // TLBI by ASID, EL0&1, inner sharable 12087408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 12097408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 121010037SARM gem5 Developers assert32(tc); 121110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 121210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 121310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 12148284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 12158284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 12168284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 12178284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 121810037SARM gem5 Developers oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 121910037SARM gem5 Developers secure_lookup, target_el); 122010037SARM gem5 Developers oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 122110037SARM gem5 Developers secure_lookup, target_el); 12228887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 12238733Sgeoffrey.blake@arm.com if (checker) { 122410037SARM gem5 Developers checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 122510037SARM gem5 Developers secure_lookup, target_el); 122610037SARM gem5 Developers checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 122710037SARM gem5 Developers secure_lookup, target_el); 12288733Sgeoffrey.blake@arm.com } 12298284SAli.Saidi@ARM.com } 12307408Sgblack@eecs.umich.edu return; 123110037SARM gem5 Developers // TLBI by address, EL0&1, inner sharable (ignored) 12327408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 12337408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 123410037SARM gem5 Developers assert32(tc); 123510037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 123610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 123710037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 123810037SARM gem5 Developers hyp = 0; 123910037SARM gem5 Developers tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 124010037SARM gem5 Developers return; 124110037SARM gem5 Developers // TLBI by address, EL2, hypervisor mode 124210037SARM gem5 Developers case MISCREG_TLBIMVAH: 124310037SARM gem5 Developers case MISCREG_TLBIMVAHIS: 124410037SARM gem5 Developers assert32(tc); 124510037SARM gem5 Developers target_el = 1; // aarch32, use hyp bit 124610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 124710037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 124810037SARM gem5 Developers hyp = 1; 124910037SARM gem5 Developers tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 125010037SARM gem5 Developers return; 125110037SARM gem5 Developers // TLBI by address and asid, EL0&1, instruction side only 125210037SARM gem5 Developers case MISCREG_ITLBIMVA: 125310037SARM gem5 Developers assert32(tc); 125410037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 125510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 125610037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 125710037SARM gem5 Developers tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 125810037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 125910037SARM gem5 Developers return; 126010037SARM gem5 Developers // TLBI by address and asid, EL0&1, data side only 126110037SARM gem5 Developers case MISCREG_DTLBIMVA: 126210037SARM gem5 Developers assert32(tc); 126310037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 126410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 126510037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 126610037SARM gem5 Developers tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 126710037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 126810037SARM gem5 Developers return; 126910037SARM gem5 Developers // TLBI by ASID, EL0&1, instrution side only 127010037SARM gem5 Developers case MISCREG_ITLBIASID: 127110037SARM gem5 Developers assert32(tc); 127210037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 127310037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 127410037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 127510037SARM gem5 Developers tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 127610037SARM gem5 Developers target_el); 127710037SARM gem5 Developers return; 127810037SARM gem5 Developers // TLBI by ASID EL0&1 data size only 127910037SARM gem5 Developers case MISCREG_DTLBIASID: 128010037SARM gem5 Developers assert32(tc); 128110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 128210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 128310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 128410037SARM gem5 Developers tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 128510037SARM gem5 Developers target_el); 128610037SARM gem5 Developers return; 128710037SARM gem5 Developers // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 128810037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 128910037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 129010037SARM gem5 Developers assert32(tc); 129110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 129210037SARM gem5 Developers hyp = 0; 129310037SARM gem5 Developers tlbiALLN(tc, hyp, target_el); 129410037SARM gem5 Developers return; 129510037SARM gem5 Developers // TLBI all entries, EL2, hyp, 129610037SARM gem5 Developers case MISCREG_TLBIALLH: 129710037SARM gem5 Developers case MISCREG_TLBIALLHIS: 129810037SARM gem5 Developers assert32(tc); 129910037SARM gem5 Developers target_el = 1; // aarch32, use hyp bit 130010037SARM gem5 Developers hyp = 1; 130110037SARM gem5 Developers tlbiALLN(tc, hyp, target_el); 130210037SARM gem5 Developers return; 130310037SARM gem5 Developers // AArch64 TLBI: invalidate all entries EL3 130410037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 130510037SARM gem5 Developers case MISCREG_TLBI_ALLE3: 130610037SARM gem5 Developers assert64(tc); 130710037SARM gem5 Developers target_el = 3; 130810037SARM gem5 Developers secure_lookup = true; 130910037SARM gem5 Developers tlbiALL(tc, secure_lookup, target_el); 131010037SARM gem5 Developers return; 131110037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 131210037SARM gem5 Developers // case MISCREG_TLBI_ALLE2IS: 131310037SARM gem5 Developers // case MISCREG_TLBI_ALLE2: 131410037SARM gem5 Developers // TLBI all entries, EL0&1 131510037SARM gem5 Developers case MISCREG_TLBI_ALLE1IS: 131610037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 131710037SARM gem5 Developers // AArch64 TLBI: invalidate all entries, stage 1, current VMID 131810037SARM gem5 Developers case MISCREG_TLBI_VMALLE1IS: 131910037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 132010037SARM gem5 Developers // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 132110037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1IS: 132210037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 132310037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 132410037SARM gem5 Developers assert64(tc); 132510037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 132610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 132710037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 132810037SARM gem5 Developers tlbiALL(tc, secure_lookup, target_el); 132910037SARM gem5 Developers return; 133010037SARM gem5 Developers // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 133110037SARM gem5 Developers // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 133210037SARM gem5 Developers // from the last level of translation table walks 133310037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 133410037SARM gem5 Developers // TLBI all entries, EL0&1 133510037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 133610037SARM gem5 Developers case MISCREG_TLBI_VAE3_Xt: 133710037SARM gem5 Developers // TLBI by VA, EL3 regime stage 1, last level walk 133810037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 133910037SARM gem5 Developers case MISCREG_TLBI_VALE3_Xt: 134010037SARM gem5 Developers assert64(tc); 134110037SARM gem5 Developers target_el = 3; 134210037SARM gem5 Developers asid = 0xbeef; // does not matter, tlbi is global 134310037SARM gem5 Developers secure_lookup = true; 134410037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 134510037SARM gem5 Developers return; 134610037SARM gem5 Developers // TLBI by VA, EL2 134710037SARM gem5 Developers case MISCREG_TLBI_VAE2IS_Xt: 134810037SARM gem5 Developers case MISCREG_TLBI_VAE2_Xt: 134910037SARM gem5 Developers // TLBI by VA, EL2, stage1 last level walk 135010037SARM gem5 Developers case MISCREG_TLBI_VALE2IS_Xt: 135110037SARM gem5 Developers case MISCREG_TLBI_VALE2_Xt: 135210037SARM gem5 Developers assert64(tc); 135310037SARM gem5 Developers target_el = 2; 135410037SARM gem5 Developers asid = 0xbeef; // does not matter, tlbi is global 135510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 135610037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 135710037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 135810037SARM gem5 Developers return; 135910037SARM gem5 Developers // TLBI by VA EL1 & 0, stage1, ASID, current VMID 136010037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 136110037SARM gem5 Developers case MISCREG_TLBI_VAE1_Xt: 136210037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 136310037SARM gem5 Developers case MISCREG_TLBI_VALE1_Xt: 136410037SARM gem5 Developers assert64(tc); 136510037SARM gem5 Developers asid = bits(newVal, 63, 48); 136610037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 136710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 136810037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 136910037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 137010037SARM gem5 Developers return; 137110037SARM gem5 Developers // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 137210037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 137310037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 137410037SARM gem5 Developers case MISCREG_TLBI_ASIDE1_Xt: 137510037SARM gem5 Developers assert64(tc); 137610037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 137710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 137810037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 13798284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 13808284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 13818284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 13828284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 138310037SARM gem5 Developers asid = bits(newVal, 63, 48); 138410709SAndreas.Sandberg@ARM.com if (!haveLargeAsid64) 138510037SARM gem5 Developers asid &= mask(8); 138610037SARM gem5 Developers oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 138710037SARM gem5 Developers oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 138810037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 138910037SARM gem5 Developers if (checker) { 139010037SARM gem5 Developers checker->getITBPtr()->flushAsid(asid, 139110037SARM gem5 Developers secure_lookup, target_el); 139210037SARM gem5 Developers checker->getDTBPtr()->flushAsid(asid, 139310037SARM gem5 Developers secure_lookup, target_el); 139410037SARM gem5 Developers } 139510037SARM gem5 Developers } 139610037SARM gem5 Developers return; 139710037SARM gem5 Developers // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 139810037SARM gem5 Developers // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 139910037SARM gem5 Developers // entries from the last level of translation table walks 140010037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 140110037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 140210037SARM gem5 Developers case MISCREG_TLBI_VAAE1_Xt: 140310037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 140410037SARM gem5 Developers case MISCREG_TLBI_VAALE1_Xt: 140510037SARM gem5 Developers assert64(tc); 140610037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 140710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 140810037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 140910037SARM gem5 Developers sys = tc->getSystemPtr(); 141010037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 141110037SARM gem5 Developers // @todo: extra controls on TLBI broadcast? 141210037SARM gem5 Developers oc = sys->getThreadContext(x); 141310037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 141410037SARM gem5 Developers Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 141510037SARM gem5 Developers oc->getITBPtr()->flushMva(va, 141610037SARM gem5 Developers secure_lookup, false, target_el); 141710037SARM gem5 Developers oc->getDTBPtr()->flushMva(va, 141810037SARM gem5 Developers secure_lookup, false, target_el); 14198887Sgeoffrey.blake@arm.com 14208887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 14218733Sgeoffrey.blake@arm.com if (checker) { 142210037SARM gem5 Developers checker->getITBPtr()->flushMva(va, 142310037SARM gem5 Developers secure_lookup, false, target_el); 142410037SARM gem5 Developers checker->getDTBPtr()->flushMva(va, 142510037SARM gem5 Developers secure_lookup, false, target_el); 14268733Sgeoffrey.blake@arm.com } 14278284SAli.Saidi@ARM.com } 14287408Sgblack@eecs.umich.edu return; 142910037SARM gem5 Developers // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 143010037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1IS_Xt: 143110037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1_Xt: 143210037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1IS_Xt: 143310037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1_Xt: 143410037SARM gem5 Developers assert64(tc); 143511584SDylan.Johnson@ARM.com target_el = 1; // EL 0 and 1 are handled together 143611584SDylan.Johnson@ARM.com scr = readMiscReg(MISCREG_SCR, tc); 143711584SDylan.Johnson@ARM.com secure_lookup = haveSecurity && !scr.ns; 143811584SDylan.Johnson@ARM.com sys = tc->getSystemPtr(); 143911584SDylan.Johnson@ARM.com for (x = 0; x < sys->numContexts(); x++) { 144011584SDylan.Johnson@ARM.com oc = sys->getThreadContext(x); 144111584SDylan.Johnson@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 144211584SDylan.Johnson@ARM.com Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; 144311584SDylan.Johnson@ARM.com oc->getITBPtr()->flushIpaVmid(ipa, 144411584SDylan.Johnson@ARM.com secure_lookup, false, target_el); 144511584SDylan.Johnson@ARM.com oc->getDTBPtr()->flushIpaVmid(ipa, 144611584SDylan.Johnson@ARM.com secure_lookup, false, target_el); 144711584SDylan.Johnson@ARM.com 144811584SDylan.Johnson@ARM.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 144911584SDylan.Johnson@ARM.com if (checker) { 145011584SDylan.Johnson@ARM.com checker->getITBPtr()->flushIpaVmid(ipa, 145111584SDylan.Johnson@ARM.com secure_lookup, false, target_el); 145211584SDylan.Johnson@ARM.com checker->getDTBPtr()->flushIpaVmid(ipa, 145311584SDylan.Johnson@ARM.com secure_lookup, false, target_el); 145411584SDylan.Johnson@ARM.com } 145511584SDylan.Johnson@ARM.com } 14567405SAli.Saidi@ARM.com return; 14577583SAli.Saidi@arm.com case MISCREG_ACTLR: 14587583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 14597583SAli.Saidi@arm.com break; 146010461SAndreas.Sandberg@ARM.com 146110461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 146210461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 146310461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 146410461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 146510461SAndreas.Sandberg@ARM.com pmu->setMiscReg(misc_reg, newVal); 14667583SAli.Saidi@arm.com break; 146710461SAndreas.Sandberg@ARM.com 146810461SAndreas.Sandberg@ARM.com 146910037SARM gem5 Developers case MISCREG_HSTR: // TJDBX, now redifined to be RES0 147010037SARM gem5 Developers { 147110037SARM gem5 Developers HSTR hstrMask = 0; 147210037SARM gem5 Developers hstrMask.tjdbx = 1; 147310037SARM gem5 Developers newVal &= ~((uint32_t) hstrMask); 147410037SARM gem5 Developers break; 147510037SARM gem5 Developers } 147610037SARM gem5 Developers case MISCREG_HCPTR: 147710037SARM gem5 Developers { 147810037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 147910037SARM gem5 Developers // HCPTR is RAO/WI. Same applies to NSASEDIS 148010037SARM gem5 Developers secure_lookup = haveSecurity && 148110037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 148210037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 148310037SARM gem5 Developers if (!secure_lookup) { 148410037SARM gem5 Developers MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 148510037SARM gem5 Developers MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 148610037SARM gem5 Developers newVal = (newVal & ~mask) | (oldValue & mask); 148710037SARM gem5 Developers } 148810037SARM gem5 Developers break; 148910037SARM gem5 Developers } 149010037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 149110037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 149210037SARM gem5 Developers break; 149310037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 149410037SARM gem5 Developers misc_reg = MISCREG_IFAR_S; 149510037SARM gem5 Developers break; 149610037SARM gem5 Developers case MISCREG_ATS1CPR: 149710037SARM gem5 Developers case MISCREG_ATS1CPW: 149810037SARM gem5 Developers case MISCREG_ATS1CUR: 149910037SARM gem5 Developers case MISCREG_ATS1CUW: 150010037SARM gem5 Developers case MISCREG_ATS12NSOPR: 150110037SARM gem5 Developers case MISCREG_ATS12NSOPW: 150210037SARM gem5 Developers case MISCREG_ATS12NSOUR: 150310037SARM gem5 Developers case MISCREG_ATS12NSOUW: 150410037SARM gem5 Developers case MISCREG_ATS1HR: 150510037SARM gem5 Developers case MISCREG_ATS1HW: 15067436Sdam.sunwoo@arm.com { 150711608Snikos.nikoleris@arm.com Request::Flags flags = 0; 150810037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 150910037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 15107436Sdam.sunwoo@arm.com Fault fault; 15117436Sdam.sunwoo@arm.com switch(misc_reg) { 151210037SARM gem5 Developers case MISCREG_ATS1CPR: 151310037SARM gem5 Developers flags = TLB::MustBeOne; 151410037SARM gem5 Developers tranType = TLB::S1CTran; 151510037SARM gem5 Developers mode = BaseTLB::Read; 151610037SARM gem5 Developers break; 151710037SARM gem5 Developers case MISCREG_ATS1CPW: 151810037SARM gem5 Developers flags = TLB::MustBeOne; 151910037SARM gem5 Developers tranType = TLB::S1CTran; 152010037SARM gem5 Developers mode = BaseTLB::Write; 152110037SARM gem5 Developers break; 152210037SARM gem5 Developers case MISCREG_ATS1CUR: 152310037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 152410037SARM gem5 Developers tranType = TLB::S1CTran; 152510037SARM gem5 Developers mode = BaseTLB::Read; 152610037SARM gem5 Developers break; 152710037SARM gem5 Developers case MISCREG_ATS1CUW: 152810037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 152910037SARM gem5 Developers tranType = TLB::S1CTran; 153010037SARM gem5 Developers mode = BaseTLB::Write; 153110037SARM gem5 Developers break; 153210037SARM gem5 Developers case MISCREG_ATS12NSOPR: 153310037SARM gem5 Developers if (!haveSecurity) 153410037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 153510037SARM gem5 Developers flags = TLB::MustBeOne; 153610037SARM gem5 Developers tranType = TLB::S1S2NsTran; 153710037SARM gem5 Developers mode = BaseTLB::Read; 153810037SARM gem5 Developers break; 153910037SARM gem5 Developers case MISCREG_ATS12NSOPW: 154010037SARM gem5 Developers if (!haveSecurity) 154110037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPW"); 154210037SARM gem5 Developers flags = TLB::MustBeOne; 154310037SARM gem5 Developers tranType = TLB::S1S2NsTran; 154410037SARM gem5 Developers mode = BaseTLB::Write; 154510037SARM gem5 Developers break; 154610037SARM gem5 Developers case MISCREG_ATS12NSOUR: 154710037SARM gem5 Developers if (!haveSecurity) 154810037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 154910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 155010037SARM gem5 Developers tranType = TLB::S1S2NsTran; 155110037SARM gem5 Developers mode = BaseTLB::Read; 155210037SARM gem5 Developers break; 155310037SARM gem5 Developers case MISCREG_ATS12NSOUW: 155410037SARM gem5 Developers if (!haveSecurity) 155510037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 155610037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 155710037SARM gem5 Developers tranType = TLB::S1S2NsTran; 155810037SARM gem5 Developers mode = BaseTLB::Write; 155910037SARM gem5 Developers break; 156010037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 156110037SARM gem5 Developers flags = TLB::MustBeOne; 156210037SARM gem5 Developers tranType = TLB::HypMode; 156310037SARM gem5 Developers mode = BaseTLB::Read; 156410037SARM gem5 Developers break; 156510037SARM gem5 Developers case MISCREG_ATS1HW: 156610037SARM gem5 Developers flags = TLB::MustBeOne; 156710037SARM gem5 Developers tranType = TLB::HypMode; 156810037SARM gem5 Developers mode = BaseTLB::Write; 156910037SARM gem5 Developers break; 15707436Sdam.sunwoo@arm.com } 157110037SARM gem5 Developers // If we're in timing mode then doing the translation in 157210037SARM gem5 Developers // functional mode then we're slightly distorting performance 157310037SARM gem5 Developers // results obtained from simulations. The translation should be 157410037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 157510037SARM gem5 Developers // can't be an atomic translation because that causes problems 157610037SARM gem5 Developers // with unexpected atomic snoop requests. 157710037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 157811560Sandreas.sandberg@arm.com Request req(0, val, 0, flags, Request::funcMasterId, 157911435Smitch.hayenga@arm.com tc->pcState().pc(), tc->contextId()); 158010653Sandreas.hansson@arm.com fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 158110037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 158210037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 158310037SARM gem5 Developers 158410037SARM gem5 Developers MiscReg newVal; 15857436Sdam.sunwoo@arm.com if (fault == NoFault) { 158610653Sandreas.hansson@arm.com Addr paddr = req.getPaddr(); 158710037SARM gem5 Developers if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 158810037SARM gem5 Developers ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 158910037SARM gem5 Developers newVal = (paddr & mask(39, 12)) | 159010037SARM gem5 Developers (tc->getDTBPtr()->getAttr()); 159110037SARM gem5 Developers } else { 159210037SARM gem5 Developers newVal = (paddr & 0xfffff000) | 159310037SARM gem5 Developers (tc->getDTBPtr()->getAttr()); 159410037SARM gem5 Developers } 15957436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 15967436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 159710037SARM gem5 Developers val, newVal); 159810037SARM gem5 Developers } else { 159910037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 160010037SARM gem5 Developers // Set fault bit and FSR 160110037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 160210037SARM gem5 Developers 160310037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 160410037SARM gem5 Developers if (newVal) { 160510037SARM gem5 Developers // LPAE - rearange fault status 160610037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 160710037SARM gem5 Developers } else { 160810037SARM gem5 Developers // VMSA - rearange fault status 160910037SARM gem5 Developers newVal |= ((fsr >> 0) & 0xf) << 1; 161010037SARM gem5 Developers newVal |= ((fsr >> 10) & 0x1) << 5; 161110037SARM gem5 Developers newVal |= ((fsr >> 12) & 0x1) << 6; 161210037SARM gem5 Developers } 161310037SARM gem5 Developers newVal |= 0x1; // F bit 161410037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 161510037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 161610037SARM gem5 Developers DPRINTF(MiscRegs, 161710037SARM gem5 Developers "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 161810037SARM gem5 Developers val, fsr, newVal); 16197436Sdam.sunwoo@arm.com } 162010037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 16217436Sdam.sunwoo@arm.com return; 16227436Sdam.sunwoo@arm.com } 162310037SARM gem5 Developers case MISCREG_TTBCR: 162410037SARM gem5 Developers { 162510037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 162610037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 162710037SARM gem5 Developers TTBCR ttbcrMask = 0; 162810037SARM gem5 Developers TTBCR ttbcrNew = newVal; 162910037SARM gem5 Developers 163010037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 163110037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 163210037SARM gem5 Developers if (haveSecurity) { 163310037SARM gem5 Developers ttbcrMask.pd0 = ones; 163410037SARM gem5 Developers ttbcrMask.pd1 = ones; 163510037SARM gem5 Developers } 163610037SARM gem5 Developers ttbcrMask.epd0 = ones; 163710037SARM gem5 Developers ttbcrMask.irgn0 = ones; 163810037SARM gem5 Developers ttbcrMask.orgn0 = ones; 163910037SARM gem5 Developers ttbcrMask.sh0 = ones; 164010037SARM gem5 Developers ttbcrMask.ps = ones; // T1SZ 164110037SARM gem5 Developers ttbcrMask.a1 = ones; 164210037SARM gem5 Developers ttbcrMask.epd1 = ones; 164310037SARM gem5 Developers ttbcrMask.irgn1 = ones; 164410037SARM gem5 Developers ttbcrMask.orgn1 = ones; 164510037SARM gem5 Developers ttbcrMask.sh1 = ones; 164610037SARM gem5 Developers if (haveLPAE) 164710037SARM gem5 Developers ttbcrMask.eae = ones; 164810037SARM gem5 Developers 164910037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 165010037SARM gem5 Developers newVal = newVal & ttbcrMask; 165110037SARM gem5 Developers } else { 165210037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 165310037SARM gem5 Developers } 165410037SARM gem5 Developers } 165510037SARM gem5 Developers case MISCREG_TTBR0: 165610037SARM gem5 Developers case MISCREG_TTBR1: 165710037SARM gem5 Developers { 165810037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 165910037SARM gem5 Developers if (haveLPAE) { 166010037SARM gem5 Developers if (ttbcr.eae) { 166110037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 166210037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 166310037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 166410037SARM gem5 Developers newVal = (newVal & (~ttbrMask)); 166510037SARM gem5 Developers } 166610037SARM gem5 Developers } 166710037SARM gem5 Developers } 166810508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL1: 166910508SAli.Saidi@ARM.com { 167010508SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 167110508SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 167210508SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 167310508SAli.Saidi@ARM.com } 16747749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 16757749SAli.Saidi@ARM.com case MISCREG_PRRR: 16767749SAli.Saidi@ARM.com case MISCREG_NMRR: 167710037SARM gem5 Developers case MISCREG_MAIR0: 167810037SARM gem5 Developers case MISCREG_MAIR1: 16797749SAli.Saidi@ARM.com case MISCREG_DACR: 168010037SARM gem5 Developers case MISCREG_VTTBR: 168110037SARM gem5 Developers case MISCREG_SCR_EL3: 168211575SDylan.Johnson@ARM.com case MISCREG_HCR_EL2: 168310037SARM gem5 Developers case MISCREG_TCR_EL1: 168410037SARM gem5 Developers case MISCREG_TCR_EL2: 168510037SARM gem5 Developers case MISCREG_TCR_EL3: 168610508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL2: 168710508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL3: 168811573SDylan.Johnson@ARM.com case MISCREG_HSCTLR: 168910037SARM gem5 Developers case MISCREG_TTBR0_EL1: 169010037SARM gem5 Developers case MISCREG_TTBR1_EL1: 169110037SARM gem5 Developers case MISCREG_TTBR0_EL2: 169210037SARM gem5 Developers case MISCREG_TTBR0_EL3: 16937749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 16947749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 16957749SAli.Saidi@ARM.com break; 169610037SARM gem5 Developers case MISCREG_NZCV: 169710037SARM gem5 Developers { 169810037SARM gem5 Developers CPSR cpsr = val; 169910037SARM gem5 Developers 170010338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_NZ, cpsr.nz); 170110338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_C, cpsr.c); 170210338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_V, cpsr.v); 170310037SARM gem5 Developers } 170410037SARM gem5 Developers break; 170510037SARM gem5 Developers case MISCREG_DAIF: 170610037SARM gem5 Developers { 170710037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 170810037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 170910037SARM gem5 Developers newVal = cpsr; 171010037SARM gem5 Developers misc_reg = MISCREG_CPSR; 171110037SARM gem5 Developers } 171210037SARM gem5 Developers break; 171310037SARM gem5 Developers case MISCREG_SP_EL0: 171410037SARM gem5 Developers tc->setIntReg(INTREG_SP0, newVal); 171510037SARM gem5 Developers break; 171610037SARM gem5 Developers case MISCREG_SP_EL1: 171710037SARM gem5 Developers tc->setIntReg(INTREG_SP1, newVal); 171810037SARM gem5 Developers break; 171910037SARM gem5 Developers case MISCREG_SP_EL2: 172010037SARM gem5 Developers tc->setIntReg(INTREG_SP2, newVal); 172110037SARM gem5 Developers break; 172210037SARM gem5 Developers case MISCREG_SPSEL: 172310037SARM gem5 Developers { 172410037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 172510037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 172610037SARM gem5 Developers newVal = cpsr; 172710037SARM gem5 Developers misc_reg = MISCREG_CPSR; 172810037SARM gem5 Developers } 172910037SARM gem5 Developers break; 173010037SARM gem5 Developers case MISCREG_CURRENTEL: 173110037SARM gem5 Developers { 173210037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 173310037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 173410037SARM gem5 Developers newVal = cpsr; 173510037SARM gem5 Developers misc_reg = MISCREG_CPSR; 173610037SARM gem5 Developers } 173710037SARM gem5 Developers break; 173810037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 173910037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 174010037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 174110037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 174210037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 174310037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 174410037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 174510037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 174610037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 174710037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 174810037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 174910037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 175010037SARM gem5 Developers { 175110037SARM gem5 Developers RequestPtr req = new Request; 175211608Snikos.nikoleris@arm.com Request::Flags flags = 0; 175310037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 175410037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 175510037SARM gem5 Developers Fault fault; 175610037SARM gem5 Developers switch(misc_reg) { 175710037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 175810037SARM gem5 Developers flags = TLB::MustBeOne; 175911577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 176010037SARM gem5 Developers mode = BaseTLB::Read; 176110037SARM gem5 Developers break; 176210037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 176310037SARM gem5 Developers flags = TLB::MustBeOne; 176411577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 176510037SARM gem5 Developers mode = BaseTLB::Write; 176610037SARM gem5 Developers break; 176710037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 176810037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 176911577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 177010037SARM gem5 Developers mode = BaseTLB::Read; 177110037SARM gem5 Developers break; 177210037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 177310037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 177411577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 177510037SARM gem5 Developers mode = BaseTLB::Write; 177610037SARM gem5 Developers break; 177710037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 177810037SARM gem5 Developers flags = TLB::MustBeOne; 177911577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 178010037SARM gem5 Developers mode = BaseTLB::Read; 178110037SARM gem5 Developers break; 178210037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 178310037SARM gem5 Developers flags = TLB::MustBeOne; 178411577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 178510037SARM gem5 Developers mode = BaseTLB::Write; 178610037SARM gem5 Developers break; 178710037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 178810037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 178911577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 179010037SARM gem5 Developers mode = BaseTLB::Read; 179110037SARM gem5 Developers break; 179210037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 179310037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 179411577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 179510037SARM gem5 Developers mode = BaseTLB::Write; 179610037SARM gem5 Developers break; 179710037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 179810037SARM gem5 Developers flags = TLB::MustBeOne; 179911577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 180010037SARM gem5 Developers mode = BaseTLB::Read; 180110037SARM gem5 Developers break; 180210037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 180310037SARM gem5 Developers flags = TLB::MustBeOne; 180411577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 180510037SARM gem5 Developers mode = BaseTLB::Write; 180610037SARM gem5 Developers break; 180710037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 180810037SARM gem5 Developers flags = TLB::MustBeOne; 180911577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 181010037SARM gem5 Developers mode = BaseTLB::Read; 181110037SARM gem5 Developers break; 181210037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 181310037SARM gem5 Developers flags = TLB::MustBeOne; 181411577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 181510037SARM gem5 Developers mode = BaseTLB::Write; 181610037SARM gem5 Developers break; 181710037SARM gem5 Developers } 181810037SARM gem5 Developers // If we're in timing mode then doing the translation in 181910037SARM gem5 Developers // functional mode then we're slightly distorting performance 182010037SARM gem5 Developers // results obtained from simulations. The translation should be 182110037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 182210037SARM gem5 Developers // can't be an atomic translation because that causes problems 182310037SARM gem5 Developers // with unexpected atomic snoop requests. 182410037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 182511560Sandreas.sandberg@arm.com req->setVirt(0, val, 0, flags, Request::funcMasterId, 182610037SARM gem5 Developers tc->pcState().pc()); 182711435Smitch.hayenga@arm.com req->setContext(tc->contextId()); 182810037SARM gem5 Developers fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 182910037SARM gem5 Developers tranType); 183010037SARM gem5 Developers 183110037SARM gem5 Developers MiscReg newVal; 183210037SARM gem5 Developers if (fault == NoFault) { 183310037SARM gem5 Developers Addr paddr = req->getPaddr(); 183410037SARM gem5 Developers uint64_t attr = tc->getDTBPtr()->getAttr(); 183510037SARM gem5 Developers uint64_t attr1 = attr >> 56; 183610037SARM gem5 Developers if (!attr1 || attr1 ==0x44) { 183710037SARM gem5 Developers attr |= 0x100; 183810037SARM gem5 Developers attr &= ~ uint64_t(0x80); 183910037SARM gem5 Developers } 184010037SARM gem5 Developers newVal = (paddr & mask(47, 12)) | attr; 184110037SARM gem5 Developers DPRINTF(MiscRegs, 184210037SARM gem5 Developers "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 184310037SARM gem5 Developers val, newVal); 184410037SARM gem5 Developers } else { 184510037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 184610037SARM gem5 Developers // Set fault bit and FSR 184710037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 184810037SARM gem5 Developers 184911577SDylan.Johnson@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 185011577SDylan.Johnson@ARM.com if (cpsr.width) { // AArch32 185111577SDylan.Johnson@ARM.com newVal = ((fsr >> 9) & 1) << 11; 185211577SDylan.Johnson@ARM.com // rearrange fault status 185311577SDylan.Johnson@ARM.com newVal |= ((fsr >> 0) & 0x3f) << 1; 185411577SDylan.Johnson@ARM.com newVal |= 0x1; // F bit 185511577SDylan.Johnson@ARM.com newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 185611577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 0x200 : 0; 185711577SDylan.Johnson@ARM.com } else { // AArch64 185811577SDylan.Johnson@ARM.com newVal = 1; // F bit 185911577SDylan.Johnson@ARM.com newVal |= fsr << 1; // FST 186011577SDylan.Johnson@ARM.com // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 186111577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 186211577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 186311577SDylan.Johnson@ARM.com newVal |= 1 << 11; // RES1 186411577SDylan.Johnson@ARM.com } 186510037SARM gem5 Developers DPRINTF(MiscRegs, 186610037SARM gem5 Developers "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 186710037SARM gem5 Developers val, fsr, newVal); 186810037SARM gem5 Developers } 186910037SARM gem5 Developers delete req; 187010037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 187110037SARM gem5 Developers return; 187210037SARM gem5 Developers } 187310037SARM gem5 Developers case MISCREG_SPSR_EL3: 187410037SARM gem5 Developers case MISCREG_SPSR_EL2: 187510037SARM gem5 Developers case MISCREG_SPSR_EL1: 187610037SARM gem5 Developers // Force bits 23:21 to 0 187710037SARM gem5 Developers newVal = val & ~(0x7 << 21); 187810037SARM gem5 Developers break; 18798549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 18808549Sdaniel.johnson@arm.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 18818549Sdaniel.johnson@arm.com miscRegName[misc_reg], uint32_t(val)); 188210037SARM gem5 Developers break; 188310037SARM gem5 Developers 188410037SARM gem5 Developers // Generic Timer registers 188510844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 188610844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 188710844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 188810844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 188910844Sandreas.sandberg@arm.com getGenericTimer(tc).setMiscReg(misc_reg, newVal); 189010037SARM gem5 Developers break; 18917405SAli.Saidi@ARM.com } 18927405SAli.Saidi@ARM.com } 18937405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 18947405SAli.Saidi@ARM.com} 18957405SAli.Saidi@ARM.com 189610037SARM gem5 Developersvoid 189710709SAndreas.Sandberg@ARM.comISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 189810709SAndreas.Sandberg@ARM.com bool secure_lookup, uint8_t target_el) 189910037SARM gem5 Developers{ 190010709SAndreas.Sandberg@ARM.com if (!haveLargeAsid64) 190110037SARM gem5 Developers asid &= mask(8); 190210037SARM gem5 Developers Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 190310037SARM gem5 Developers System *sys = tc->getSystemPtr(); 190410037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 190510037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 190610037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 190710037SARM gem5 Developers oc->getITBPtr()->flushMvaAsid(va, asid, 190810037SARM gem5 Developers secure_lookup, target_el); 190910037SARM gem5 Developers oc->getDTBPtr()->flushMvaAsid(va, asid, 191010037SARM gem5 Developers secure_lookup, target_el); 191110037SARM gem5 Developers 191210037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 191310037SARM gem5 Developers if (checker) { 191410037SARM gem5 Developers checker->getITBPtr()->flushMvaAsid( 191510037SARM gem5 Developers va, asid, secure_lookup, target_el); 191610037SARM gem5 Developers checker->getDTBPtr()->flushMvaAsid( 191710037SARM gem5 Developers va, asid, secure_lookup, target_el); 191810037SARM gem5 Developers } 191910037SARM gem5 Developers } 192010037SARM gem5 Developers} 192110037SARM gem5 Developers 192210037SARM gem5 Developersvoid 192310037SARM gem5 DevelopersISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 192410037SARM gem5 Developers{ 192510037SARM gem5 Developers System *sys = tc->getSystemPtr(); 192610037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 192710037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 192810037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 192910037SARM gem5 Developers oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 193010037SARM gem5 Developers oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 193110037SARM gem5 Developers 193210037SARM gem5 Developers // If CheckerCPU is connected, need to notify it of a flush 193310037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 193410037SARM gem5 Developers if (checker) { 193510037SARM gem5 Developers checker->getITBPtr()->flushAllSecurity(secure_lookup, 193610037SARM gem5 Developers target_el); 193710037SARM gem5 Developers checker->getDTBPtr()->flushAllSecurity(secure_lookup, 193810037SARM gem5 Developers target_el); 193910037SARM gem5 Developers } 194010037SARM gem5 Developers } 194110037SARM gem5 Developers} 194210037SARM gem5 Developers 194310037SARM gem5 Developersvoid 194410037SARM gem5 DevelopersISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 194510037SARM gem5 Developers{ 194610037SARM gem5 Developers System *sys = tc->getSystemPtr(); 194710037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 194810037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 194910037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 195010037SARM gem5 Developers oc->getITBPtr()->flushAllNs(hyp, target_el); 195110037SARM gem5 Developers oc->getDTBPtr()->flushAllNs(hyp, target_el); 195210037SARM gem5 Developers 195310037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 195410037SARM gem5 Developers if (checker) { 195510037SARM gem5 Developers checker->getITBPtr()->flushAllNs(hyp, target_el); 195610037SARM gem5 Developers checker->getDTBPtr()->flushAllNs(hyp, target_el); 195710037SARM gem5 Developers } 195810037SARM gem5 Developers } 195910037SARM gem5 Developers} 196010037SARM gem5 Developers 196110037SARM gem5 Developersvoid 196210037SARM gem5 DevelopersISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 196310037SARM gem5 Developers uint8_t target_el) 196410037SARM gem5 Developers{ 196510037SARM gem5 Developers System *sys = tc->getSystemPtr(); 196610037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 196710037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 196810037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 196910037SARM gem5 Developers oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 197010037SARM gem5 Developers secure_lookup, hyp, target_el); 197110037SARM gem5 Developers oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 197210037SARM gem5 Developers secure_lookup, hyp, target_el); 197310037SARM gem5 Developers 197410037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 197510037SARM gem5 Developers if (checker) { 197610037SARM gem5 Developers checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 197710037SARM gem5 Developers secure_lookup, hyp, target_el); 197810037SARM gem5 Developers checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 197910037SARM gem5 Developers secure_lookup, hyp, target_el); 198010037SARM gem5 Developers } 198110037SARM gem5 Developers } 198210037SARM gem5 Developers} 198310037SARM gem5 Developers 198410844Sandreas.sandberg@arm.comBaseISADevice & 198510844Sandreas.sandberg@arm.comISA::getGenericTimer(ThreadContext *tc) 198610037SARM gem5 Developers{ 198710844Sandreas.sandberg@arm.com // We only need to create an ISA interface the first time we try 198810844Sandreas.sandberg@arm.com // to access the timer. 198910844Sandreas.sandberg@arm.com if (timer) 199010844Sandreas.sandberg@arm.com return *timer.get(); 199110844Sandreas.sandberg@arm.com 199210844Sandreas.sandberg@arm.com assert(system); 199310844Sandreas.sandberg@arm.com GenericTimer *generic_timer(system->getGenericTimer()); 199410844Sandreas.sandberg@arm.com if (!generic_timer) { 199510844Sandreas.sandberg@arm.com panic("Trying to get a generic timer from a system that hasn't " 199610844Sandreas.sandberg@arm.com "been configured to use a generic timer.\n"); 199710037SARM gem5 Developers } 199810037SARM gem5 Developers 199911150Smitch.hayenga@arm.com timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 200010844Sandreas.sandberg@arm.com return *timer.get(); 200110037SARM gem5 Developers} 200210037SARM gem5 Developers 20037405SAli.Saidi@ARM.com} 20049384SAndreas.Sandberg@arm.com 20059384SAndreas.Sandberg@arm.comArmISA::ISA * 20069384SAndreas.Sandberg@arm.comArmISAParams::create() 20079384SAndreas.Sandberg@arm.com{ 20089384SAndreas.Sandberg@arm.com return new ArmISA::ISA(this); 20099384SAndreas.Sandberg@arm.com} 2010