isa.cc revision 11771
15222Sksewell@umich.edu/* 25222Sksewell@umich.edu * Copyright (c) 2010-2016 ARM Limited 35222Sksewell@umich.edu * All rights reserved 45222Sksewell@umich.edu * 55222Sksewell@umich.edu * The license below extends only to copyright in the software and shall 65222Sksewell@umich.edu * not be construed as granting a license to any other intellectual 75222Sksewell@umich.edu * property including but not limited to intellectual property relating 85222Sksewell@umich.edu * to a hardware implementation of the functionality of the software 95222Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 105222Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 115222Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 125222Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 135222Sksewell@umich.edu * 145222Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 155222Sksewell@umich.edu * modification, are permitted provided that the following conditions are 165222Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 175222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 185222Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 195222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 205222Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 215222Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 225222Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 235222Sksewell@umich.edu * this software without specific prior written permission. 245222Sksewell@umich.edu * 255222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 265222Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 275222Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 285222Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 295222Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 305222Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 315222Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 325222Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 335222Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 345222Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 355222Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 365222Sksewell@umich.edu * 375222Sksewell@umich.edu * Authors: Gabe Black 385222Sksewell@umich.edu * Ali Saidi 395222Sksewell@umich.edu */ 405222Sksewell@umich.edu 415222Sksewell@umich.edu#include "arch/arm/isa.hh" 425222Sksewell@umich.edu#include "arch/arm/pmu.hh" 436379Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 445222Sksewell@umich.edu#include "cpu/checker/cpu.hh" 456658Snate@binkert.org#include "cpu/base.hh" 465222Sksewell@umich.edu#include "debug/Arm.hh" 475222Sksewell@umich.edu#include "debug/MiscRegs.hh" 485222Sksewell@umich.edu#include "dev/arm/generic_timer.hh" 495222Sksewell@umich.edu#include "params/ArmISA.hh" 505222Sksewell@umich.edu#include "sim/faults.hh" 515222Sksewell@umich.edu#include "sim/stat_control.hh" 525222Sksewell@umich.edu#include "sim/system.hh" 535222Sksewell@umich.edu 545222Sksewell@umich.edunamespace ArmISA 555222Sksewell@umich.edu{ 565222Sksewell@umich.edu 575222Sksewell@umich.edu 585222Sksewell@umich.edu/** 595222Sksewell@umich.edu * Some registers alias with others, and therefore need to be translated. 606379Sgblack@eecs.umich.edu * For each entry: 616379Sgblack@eecs.umich.edu * The first value is the misc register that is to be looked up 626379Sgblack@eecs.umich.edu * the second value is the lower part of the translation 635222Sksewell@umich.edu * the third the upper part 645222Sksewell@umich.edu * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 655222Sksewell@umich.edu */ 666379Sgblack@eecs.umich.educonst struct ISA::MiscRegInitializerEntry 676379Sgblack@eecs.umich.edu ISA::MiscRegSwitch[] = { 686379Sgblack@eecs.umich.edu {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}}, 695222Sksewell@umich.edu {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}}, 705222Sksewell@umich.edu {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}}, 715222Sksewell@umich.edu {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}}, 725222Sksewell@umich.edu {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}}, 735222Sksewell@umich.edu {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 745222Sksewell@umich.edu {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}}, 755222Sksewell@umich.edu {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}}, 765222Sksewell@umich.edu {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}}, 775222Sksewell@umich.edu // ESR_EL1 -> DFSR 785222Sksewell@umich.edu {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 795222Sksewell@umich.edu {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 805222Sksewell@umich.edu {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 815222Sksewell@umich.edu {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 825222Sksewell@umich.edu {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}}, 837064Snate@binkert.org {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 845222Sksewell@umich.edu {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}}, 855222Sksewell@umich.edu {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 865222Sksewell@umich.edu {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 875222Sksewell@umich.edu {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 885222Sksewell@umich.edu {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 896379Sgblack@eecs.umich.edu {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 905222Sksewell@umich.edu {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 915222Sksewell@umich.edu {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 925222Sksewell@umich.edu {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 935222Sksewell@umich.edu {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 945222Sksewell@umich.edu {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 955222Sksewell@umich.edu {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 966379Sgblack@eecs.umich.edu {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}}, 975222Sksewell@umich.edu {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}}, 985222Sksewell@umich.edu {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}}, 995222Sksewell@umich.edu // RMR_EL1 -> RMR 1005222Sksewell@umich.edu // RMR_EL2 -> HRMR 1015222Sksewell@umich.edu {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}}, 1025222Sksewell@umich.edu {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}, 1035222Sksewell@umich.edu {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}}, 1045222Sksewell@umich.edu {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}}, 1055222Sksewell@umich.edu {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}}, 1065222Sksewell@umich.edu {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}}, 1075222Sksewell@umich.edu {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}}, 1085222Sksewell@umich.edu {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}}, 1095222Sksewell@umich.edu {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}}, 1105222Sksewell@umich.edu {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}}, 1116379Sgblack@eecs.umich.edu {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}}, 1125222Sksewell@umich.edu {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 1135222Sksewell@umich.edu {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 1145222Sksewell@umich.edu {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 1155222Sksewell@umich.edu {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 1165222Sksewell@umich.edu {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 1175222Sksewell@umich.edu {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */ 1185222Sksewell@umich.edu {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 1195222Sksewell@umich.edu {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 1205222Sksewell@umich.edu {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}}, 1215222Sksewell@umich.edu {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */ 1225222Sksewell@umich.edu {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}}, 1235222Sksewell@umich.edu {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */ 1245222Sksewell@umich.edu {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 1255222Sksewell@umich.edu {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */ 1265222Sksewell@umich.edu {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 1275222Sksewell@umich.edu {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */ 1285222Sksewell@umich.edu {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */ 1295222Sksewell@umich.edu {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}}, 1305222Sksewell@umich.edu {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}}, 1315222Sksewell@umich.edu {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}}, 1325222Sksewell@umich.edu {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}}, 1335222Sksewell@umich.edu {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}}, 1345222Sksewell@umich.edu {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}}, 1355222Sksewell@umich.edu {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}}, 1365222Sksewell@umich.edu {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}}, 1375222Sksewell@umich.edu {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}}, 1385222Sksewell@umich.edu {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}}, 1395222Sksewell@umich.edu {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}}, 1405222Sksewell@umich.edu {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}}, 1415222Sksewell@umich.edu {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}}, 1425222Sksewell@umich.edu {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}}, 1435222Sksewell@umich.edu {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}}, 1445222Sksewell@umich.edu // DBGDTR_EL0 -> DBGDTR{R or T}Xint 1455222Sksewell@umich.edu // DBGDTRRX_EL0 -> DBGDTRRXint 1465222Sksewell@umich.edu // DBGDTRTX_EL0 -> DBGDTRRXint 1475222Sksewell@umich.edu {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}}, 1485222Sksewell@umich.edu {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}}, 1495222Sksewell@umich.edu {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}}, 1505222Sksewell@umich.edu {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}}, 151 {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}}, 152 {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}}, 153 {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}}, 154 {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}}, 155 {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}}, 156 {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}}, 157 {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}}, 158 {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}}, 159 {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}}, 160 {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}}, 161 {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}}, 162 {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}}, 163 {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}}, 164 {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}}, 165 {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}}, 166 {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}}, 167 {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}}, 168 {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}}, 169 {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}}, 170 {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}}, 171 {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}}, 172 {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}}, 173/* {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}}, 174 {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}}, 175 {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}}, 176 {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}}, 177 {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}}, 178 {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}}, 179 {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}}, 180 {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}}, 181 {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}}, 182 {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}}, 183 {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}}, 184 {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */ 185 {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}}, 186 {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}}, 187// {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}}, 188 {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}}, 189 {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}}, 190 {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}}, 191 {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}}, 192 {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}}, 193 {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}}, 194 195 // from ARM DDI 0487A.i, template text 196 // "AArch64 System register ___ can be mapped to 197 // AArch32 System register ___, but this is not 198 // architecturally mandated." 199 {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005 200 // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5) 201 {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1 202 {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2 203 {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3 204}; 205 206 207ISA::ISA(Params *p) 208 : SimObject(p), 209 system(NULL), 210 _decoderFlavour(p->decoderFlavour), 211 pmu(p->pmu), 212 lookUpMiscReg(NUM_MISCREGS, {0,0}) 213{ 214 miscRegs[MISCREG_SCTLR_RST] = 0; 215 216 // Hook up a dummy device if we haven't been configured with a 217 // real PMU. By using a dummy device, we don't need to check that 218 // the PMU exist every time we try to access a PMU register. 219 if (!pmu) 220 pmu = &dummyDevice; 221 222 // Give all ISA devices a pointer to this ISA 223 pmu->setISA(this); 224 225 system = dynamic_cast<ArmSystem *>(p->system); 226 227 // Cache system-level properties 228 if (FullSystem && system) { 229 highestELIs64 = system->highestELIs64(); 230 haveSecurity = system->haveSecurity(); 231 haveLPAE = system->haveLPAE(); 232 haveVirtualization = system->haveVirtualization(); 233 haveLargeAsid64 = system->haveLargeAsid64(); 234 physAddrRange64 = system->physAddrRange64(); 235 } else { 236 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 237 haveSecurity = haveLPAE = haveVirtualization = false; 238 haveLargeAsid64 = false; 239 physAddrRange64 = 32; // dummy value 240 } 241 242 /** Fill in the miscReg translation table */ 243 for (auto sw : MiscRegSwitch) { 244 lookUpMiscReg[sw.index] = sw.entry; 245 } 246 247 preUnflattenMiscReg(); 248 249 clear(); 250} 251 252const ArmISAParams * 253ISA::params() const 254{ 255 return dynamic_cast<const Params *>(_params); 256} 257 258void 259ISA::clear() 260{ 261 const Params *p(params()); 262 263 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 264 memset(miscRegs, 0, sizeof(miscRegs)); 265 266 // Initialize configurable default values 267 miscRegs[MISCREG_MIDR] = p->midr; 268 miscRegs[MISCREG_MIDR_EL1] = p->midr; 269 miscRegs[MISCREG_VPIDR] = p->midr; 270 271 if (FullSystem && system->highestELIs64()) { 272 // Initialize AArch64 state 273 clear64(p); 274 return; 275 } 276 277 // Initialize AArch32 state... 278 279 CPSR cpsr = 0; 280 cpsr.mode = MODE_USER; 281 miscRegs[MISCREG_CPSR] = cpsr; 282 updateRegMap(cpsr); 283 284 SCTLR sctlr = 0; 285 sctlr.te = (bool) sctlr_rst.te; 286 sctlr.nmfi = (bool) sctlr_rst.nmfi; 287 sctlr.v = (bool) sctlr_rst.v; 288 sctlr.u = 1; 289 sctlr.xp = 1; 290 sctlr.rao2 = 1; 291 sctlr.rao3 = 1; 292 sctlr.rao4 = 0xf; // SCTLR[6:3] 293 sctlr.uci = 1; 294 sctlr.dze = 1; 295 miscRegs[MISCREG_SCTLR_NS] = sctlr; 296 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 297 miscRegs[MISCREG_HCPTR] = 0; 298 299 // Start with an event in the mailbox 300 miscRegs[MISCREG_SEV_MAILBOX] = 1; 301 302 // Separate Instruction and Data TLBs 303 miscRegs[MISCREG_TLBTR] = 1; 304 305 MVFR0 mvfr0 = 0; 306 mvfr0.advSimdRegisters = 2; 307 mvfr0.singlePrecision = 2; 308 mvfr0.doublePrecision = 2; 309 mvfr0.vfpExceptionTrapping = 0; 310 mvfr0.divide = 1; 311 mvfr0.squareRoot = 1; 312 mvfr0.shortVectors = 1; 313 mvfr0.roundingModes = 1; 314 miscRegs[MISCREG_MVFR0] = mvfr0; 315 316 MVFR1 mvfr1 = 0; 317 mvfr1.flushToZero = 1; 318 mvfr1.defaultNaN = 1; 319 mvfr1.advSimdLoadStore = 1; 320 mvfr1.advSimdInteger = 1; 321 mvfr1.advSimdSinglePrecision = 1; 322 mvfr1.advSimdHalfPrecision = 1; 323 mvfr1.vfpHalfPrecision = 1; 324 miscRegs[MISCREG_MVFR1] = mvfr1; 325 326 // Reset values of PRRR and NMRR are implementation dependent 327 328 // @todo: PRRR and NMRR in secure state? 329 miscRegs[MISCREG_PRRR_NS] = 330 (1 << 19) | // 19 331 (0 << 18) | // 18 332 (0 << 17) | // 17 333 (1 << 16) | // 16 334 (2 << 14) | // 15:14 335 (0 << 12) | // 13:12 336 (2 << 10) | // 11:10 337 (2 << 8) | // 9:8 338 (2 << 6) | // 7:6 339 (2 << 4) | // 5:4 340 (1 << 2) | // 3:2 341 0; // 1:0 342 miscRegs[MISCREG_NMRR_NS] = 343 (1 << 30) | // 31:30 344 (0 << 26) | // 27:26 345 (0 << 24) | // 25:24 346 (3 << 22) | // 23:22 347 (2 << 20) | // 21:20 348 (0 << 18) | // 19:18 349 (0 << 16) | // 17:16 350 (1 << 14) | // 15:14 351 (0 << 12) | // 13:12 352 (2 << 10) | // 11:10 353 (0 << 8) | // 9:8 354 (3 << 6) | // 7:6 355 (2 << 4) | // 5:4 356 (0 << 2) | // 3:2 357 0; // 1:0 358 359 miscRegs[MISCREG_CPACR] = 0; 360 361 362 miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 363 miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 364 365 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 366 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 367 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 368 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 369 370 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 371 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 372 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 373 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 374 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 375 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 376 377 miscRegs[MISCREG_FPSID] = p->fpsid; 378 379 if (haveLPAE) { 380 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 381 ttbcr.eae = 0; 382 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 383 // Enforce consistency with system-level settings 384 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 385 } 386 387 if (haveSecurity) { 388 miscRegs[MISCREG_SCTLR_S] = sctlr; 389 miscRegs[MISCREG_SCR] = 0; 390 miscRegs[MISCREG_VBAR_S] = 0; 391 } else { 392 // we're always non-secure 393 miscRegs[MISCREG_SCR] = 1; 394 } 395 396 //XXX We need to initialize the rest of the state. 397} 398 399void 400ISA::clear64(const ArmISAParams *p) 401{ 402 CPSR cpsr = 0; 403 Addr rvbar = system->resetAddr64(); 404 switch (system->highestEL()) { 405 // Set initial EL to highest implemented EL using associated stack 406 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 407 // value 408 case EL3: 409 cpsr.mode = MODE_EL3H; 410 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 411 break; 412 case EL2: 413 cpsr.mode = MODE_EL2H; 414 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 415 break; 416 case EL1: 417 cpsr.mode = MODE_EL1H; 418 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 419 break; 420 default: 421 panic("Invalid highest implemented exception level"); 422 break; 423 } 424 425 // Initialize rest of CPSR 426 cpsr.daif = 0xf; // Mask all interrupts 427 cpsr.ss = 0; 428 cpsr.il = 0; 429 miscRegs[MISCREG_CPSR] = cpsr; 430 updateRegMap(cpsr); 431 432 // Initialize other control registers 433 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 434 if (haveSecurity) { 435 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 436 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 437 } else if (haveVirtualization) { 438 // also MISCREG_SCTLR_EL2 (by mapping) 439 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 440 } else { 441 // also MISCREG_SCTLR_EL1 (by mapping) 442 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 443 // Always non-secure 444 miscRegs[MISCREG_SCR_EL3] = 1; 445 } 446 447 // Initialize configurable id registers 448 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 449 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 450 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 451 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 452 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 453 454 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 455 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 456 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 457 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 458 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 459 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 460 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; 461 462 miscRegs[MISCREG_ID_DFR0_EL1] = 463 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 464 465 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 466 467 // Enforce consistency with system-level settings... 468 469 // EL3 470 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 471 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 472 haveSecurity ? 0x2 : 0x0); 473 // EL2 474 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 475 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 476 haveVirtualization ? 0x2 : 0x0); 477 // Large ASID support 478 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 479 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 480 haveLargeAsid64 ? 0x2 : 0x0); 481 // Physical address size 482 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 483 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 484 encodePhysAddrRange64(physAddrRange64)); 485} 486 487MiscReg 488ISA::readMiscRegNoEffect(int misc_reg) const 489{ 490 assert(misc_reg < NumMiscRegs); 491 492 auto regs = getMiscIndices(misc_reg); 493 int lower = regs.first, upper = regs.second; 494 return !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 495 |(miscRegs[upper] << 32)); 496} 497 498 499MiscReg 500ISA::readMiscReg(int misc_reg, ThreadContext *tc) 501{ 502 CPSR cpsr = 0; 503 PCState pc = 0; 504 SCR scr = 0; 505 506 if (misc_reg == MISCREG_CPSR) { 507 cpsr = miscRegs[misc_reg]; 508 pc = tc->pcState(); 509 cpsr.j = pc.jazelle() ? 1 : 0; 510 cpsr.t = pc.thumb() ? 1 : 0; 511 return cpsr; 512 } 513 514#ifndef NDEBUG 515 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 516 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 517 warn("Unimplemented system register %s read.\n", 518 miscRegName[misc_reg]); 519 else 520 panic("Unimplemented system register %s read.\n", 521 miscRegName[misc_reg]); 522 } 523#endif 524 525 switch (unflattenMiscReg(misc_reg)) { 526 case MISCREG_HCR: 527 { 528 if (!haveVirtualization) 529 return 0; 530 else 531 return readMiscRegNoEffect(MISCREG_HCR); 532 } 533 case MISCREG_CPACR: 534 { 535 const uint32_t ones = (uint32_t)(-1); 536 CPACR cpacrMask = 0; 537 // Only cp10, cp11, and ase are implemented, nothing else should 538 // be readable? (straight copy from the write code) 539 cpacrMask.cp10 = ones; 540 cpacrMask.cp11 = ones; 541 cpacrMask.asedis = ones; 542 543 // Security Extensions may limit the readability of CPACR 544 if (haveSecurity) { 545 scr = readMiscRegNoEffect(MISCREG_SCR); 546 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 547 if (scr.ns && (cpsr.mode != MODE_MON)) { 548 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 549 // NB: Skipping the full loop, here 550 if (!nsacr.cp10) cpacrMask.cp10 = 0; 551 if (!nsacr.cp11) cpacrMask.cp11 = 0; 552 } 553 } 554 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 555 val &= cpacrMask; 556 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 557 miscRegName[misc_reg], val); 558 return val; 559 } 560 case MISCREG_MPIDR: 561 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 562 scr = readMiscRegNoEffect(MISCREG_SCR); 563 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 564 return getMPIDR(system, tc); 565 } else { 566 return readMiscReg(MISCREG_VMPIDR, tc); 567 } 568 break; 569 case MISCREG_MPIDR_EL1: 570 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 571 return getMPIDR(system, tc) & 0xffffffff; 572 case MISCREG_VMPIDR: 573 // top bit defined as RES1 574 return readMiscRegNoEffect(misc_reg) | 0x80000000; 575 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 576 case MISCREG_REVIDR: // not implemented, so alias MIDR 577 case MISCREG_MIDR: 578 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 579 scr = readMiscRegNoEffect(MISCREG_SCR); 580 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 581 return readMiscRegNoEffect(misc_reg); 582 } else { 583 return readMiscRegNoEffect(MISCREG_VPIDR); 584 } 585 break; 586 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 587 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 588 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 589 case MISCREG_AIDR: // AUX ID set to 0 590 case MISCREG_TCMTR: // No TCM's 591 return 0; 592 593 case MISCREG_CLIDR: 594 warn_once("The clidr register always reports 0 caches.\n"); 595 warn_once("clidr LoUIS field of 0b001 to match current " 596 "ARM implementations.\n"); 597 return 0x00200000; 598 case MISCREG_CCSIDR: 599 warn_once("The ccsidr register isn't implemented and " 600 "always reads as 0.\n"); 601 break; 602 case MISCREG_CTR: 603 { 604 //all caches have the same line size in gem5 605 //4 byte words in ARM 606 unsigned lineSizeWords = 607 tc->getSystemPtr()->cacheLineSize() / 4; 608 unsigned log2LineSizeWords = 0; 609 610 while (lineSizeWords >>= 1) { 611 ++log2LineSizeWords; 612 } 613 614 CTR ctr = 0; 615 //log2 of minimun i-cache line size (words) 616 ctr.iCacheLineSize = log2LineSizeWords; 617 //b11 - gem5 uses pipt 618 ctr.l1IndexPolicy = 0x3; 619 //log2 of minimum d-cache line size (words) 620 ctr.dCacheLineSize = log2LineSizeWords; 621 //log2 of max reservation size (words) 622 ctr.erg = log2LineSizeWords; 623 //log2 of max writeback size (words) 624 ctr.cwg = log2LineSizeWords; 625 //b100 - gem5 format is ARMv7 626 ctr.format = 0x4; 627 628 return ctr; 629 } 630 case MISCREG_ACTLR: 631 warn("Not doing anything for miscreg ACTLR\n"); 632 break; 633 634 case MISCREG_PMXEVTYPER_PMCCFILTR: 635 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 636 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 637 case MISCREG_PMCR ... MISCREG_PMOVSSET: 638 return pmu->readMiscReg(misc_reg); 639 640 case MISCREG_CPSR_Q: 641 panic("shouldn't be reading this register seperately\n"); 642 case MISCREG_FPSCR_QC: 643 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 644 case MISCREG_FPSCR_EXC: 645 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 646 case MISCREG_FPSR: 647 { 648 const uint32_t ones = (uint32_t)(-1); 649 FPSCR fpscrMask = 0; 650 fpscrMask.ioc = ones; 651 fpscrMask.dzc = ones; 652 fpscrMask.ofc = ones; 653 fpscrMask.ufc = ones; 654 fpscrMask.ixc = ones; 655 fpscrMask.idc = ones; 656 fpscrMask.qc = ones; 657 fpscrMask.v = ones; 658 fpscrMask.c = ones; 659 fpscrMask.z = ones; 660 fpscrMask.n = ones; 661 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 662 } 663 case MISCREG_FPCR: 664 { 665 const uint32_t ones = (uint32_t)(-1); 666 FPSCR fpscrMask = 0; 667 fpscrMask.ioe = ones; 668 fpscrMask.dze = ones; 669 fpscrMask.ofe = ones; 670 fpscrMask.ufe = ones; 671 fpscrMask.ixe = ones; 672 fpscrMask.ide = ones; 673 fpscrMask.len = ones; 674 fpscrMask.stride = ones; 675 fpscrMask.rMode = ones; 676 fpscrMask.fz = ones; 677 fpscrMask.dn = ones; 678 fpscrMask.ahp = ones; 679 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 680 } 681 case MISCREG_NZCV: 682 { 683 CPSR cpsr = 0; 684 cpsr.nz = tc->readCCReg(CCREG_NZ); 685 cpsr.c = tc->readCCReg(CCREG_C); 686 cpsr.v = tc->readCCReg(CCREG_V); 687 return cpsr; 688 } 689 case MISCREG_DAIF: 690 { 691 CPSR cpsr = 0; 692 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 693 return cpsr; 694 } 695 case MISCREG_SP_EL0: 696 { 697 return tc->readIntReg(INTREG_SP0); 698 } 699 case MISCREG_SP_EL1: 700 { 701 return tc->readIntReg(INTREG_SP1); 702 } 703 case MISCREG_SP_EL2: 704 { 705 return tc->readIntReg(INTREG_SP2); 706 } 707 case MISCREG_SPSEL: 708 { 709 return miscRegs[MISCREG_CPSR] & 0x1; 710 } 711 case MISCREG_CURRENTEL: 712 { 713 return miscRegs[MISCREG_CPSR] & 0xc; 714 } 715 case MISCREG_L2CTLR: 716 { 717 // mostly unimplemented, just set NumCPUs field from sim and return 718 L2CTLR l2ctlr = 0; 719 // b00:1CPU to b11:4CPUs 720 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 721 return l2ctlr; 722 } 723 case MISCREG_DBGDIDR: 724 /* For now just implement the version number. 725 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 726 */ 727 return 0x5 << 16; 728 case MISCREG_DBGDSCRint: 729 return 0; 730 case MISCREG_ISR: 731 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 732 readMiscRegNoEffect(MISCREG_HCR), 733 readMiscRegNoEffect(MISCREG_CPSR), 734 readMiscRegNoEffect(MISCREG_SCR)); 735 case MISCREG_ISR_EL1: 736 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 737 readMiscRegNoEffect(MISCREG_HCR_EL2), 738 readMiscRegNoEffect(MISCREG_CPSR), 739 readMiscRegNoEffect(MISCREG_SCR_EL3)); 740 case MISCREG_DCZID_EL0: 741 return 0x04; // DC ZVA clear 64-byte chunks 742 case MISCREG_HCPTR: 743 { 744 MiscReg val = readMiscRegNoEffect(misc_reg); 745 // The trap bit associated with CP14 is defined as RAZ 746 val &= ~(1 << 14); 747 // If a CP bit in NSACR is 0 then the corresponding bit in 748 // HCPTR is RAO/WI 749 bool secure_lookup = haveSecurity && 750 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 751 readMiscRegNoEffect(MISCREG_CPSR)); 752 if (!secure_lookup) { 753 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 754 val |= (mask ^ 0x7FFF) & 0xBFFF; 755 } 756 // Set the bits for unimplemented coprocessors to RAO/WI 757 val |= 0x33FF; 758 return (val); 759 } 760 case MISCREG_HDFAR: // alias for secure DFAR 761 return readMiscRegNoEffect(MISCREG_DFAR_S); 762 case MISCREG_HIFAR: // alias for secure IFAR 763 return readMiscRegNoEffect(MISCREG_IFAR_S); 764 case MISCREG_HVBAR: // bottom bits reserved 765 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 766 case MISCREG_SCTLR: 767 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 768 case MISCREG_SCTLR_EL1: 769 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 770 case MISCREG_SCTLR_EL2: 771 case MISCREG_SCTLR_EL3: 772 case MISCREG_HSCTLR: 773 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 774 775 // Generic Timer registers 776 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 777 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 778 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 779 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 780 return getGenericTimer(tc).readMiscReg(misc_reg); 781 782 default: 783 break; 784 785 } 786 return readMiscRegNoEffect(misc_reg); 787} 788 789void 790ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 791{ 792 assert(misc_reg < NumMiscRegs); 793 794 auto regs = getMiscIndices(misc_reg); 795 int lower = regs.first, upper = regs.second; 796 if (upper > 0) { 797 miscRegs[lower] = bits(val, 31, 0); 798 miscRegs[upper] = bits(val, 63, 32); 799 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 800 misc_reg, lower, upper, val); 801 } else { 802 miscRegs[lower] = val; 803 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 804 misc_reg, lower, val); 805 } 806} 807 808void 809ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 810{ 811 812 MiscReg newVal = val; 813 int x; 814 bool secure_lookup; 815 bool hyp; 816 System *sys; 817 ThreadContext *oc; 818 uint8_t target_el; 819 uint16_t asid; 820 SCR scr; 821 822 if (misc_reg == MISCREG_CPSR) { 823 updateRegMap(val); 824 825 826 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 827 int old_mode = old_cpsr.mode; 828 CPSR cpsr = val; 829 if (old_mode != cpsr.mode) { 830 tc->getITBPtr()->invalidateMiscReg(); 831 tc->getDTBPtr()->invalidateMiscReg(); 832 } 833 834 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 835 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 836 PCState pc = tc->pcState(); 837 pc.nextThumb(cpsr.t); 838 pc.nextJazelle(cpsr.j); 839 840 // Follow slightly different semantics if a CheckerCPU object 841 // is connected 842 CheckerCPU *checker = tc->getCheckerCpuPtr(); 843 if (checker) { 844 tc->pcStateNoRecord(pc); 845 } else { 846 tc->pcState(pc); 847 } 848 } else { 849#ifndef NDEBUG 850 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 851 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 852 warn("Unimplemented system register %s write with %#x.\n", 853 miscRegName[misc_reg], val); 854 else 855 panic("Unimplemented system register %s write with %#x.\n", 856 miscRegName[misc_reg], val); 857 } 858#endif 859 switch (unflattenMiscReg(misc_reg)) { 860 case MISCREG_CPACR: 861 { 862 863 const uint32_t ones = (uint32_t)(-1); 864 CPACR cpacrMask = 0; 865 // Only cp10, cp11, and ase are implemented, nothing else should 866 // be writable 867 cpacrMask.cp10 = ones; 868 cpacrMask.cp11 = ones; 869 cpacrMask.asedis = ones; 870 871 // Security Extensions may limit the writability of CPACR 872 if (haveSecurity) { 873 scr = readMiscRegNoEffect(MISCREG_SCR); 874 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 875 if (scr.ns && (cpsr.mode != MODE_MON)) { 876 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 877 // NB: Skipping the full loop, here 878 if (!nsacr.cp10) cpacrMask.cp10 = 0; 879 if (!nsacr.cp11) cpacrMask.cp11 = 0; 880 } 881 } 882 883 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 884 newVal &= cpacrMask; 885 newVal |= old_val & ~cpacrMask; 886 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 887 miscRegName[misc_reg], newVal); 888 } 889 break; 890 case MISCREG_CPACR_EL1: 891 { 892 const uint32_t ones = (uint32_t)(-1); 893 CPACR cpacrMask = 0; 894 cpacrMask.tta = ones; 895 cpacrMask.fpen = ones; 896 newVal &= cpacrMask; 897 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 898 miscRegName[misc_reg], newVal); 899 } 900 break; 901 case MISCREG_CPTR_EL2: 902 { 903 const uint32_t ones = (uint32_t)(-1); 904 CPTR cptrMask = 0; 905 cptrMask.tcpac = ones; 906 cptrMask.tta = ones; 907 cptrMask.tfp = ones; 908 newVal &= cptrMask; 909 cptrMask = 0; 910 cptrMask.res1_13_12_el2 = ones; 911 cptrMask.res1_9_0_el2 = ones; 912 newVal |= cptrMask; 913 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 914 miscRegName[misc_reg], newVal); 915 } 916 break; 917 case MISCREG_CPTR_EL3: 918 { 919 const uint32_t ones = (uint32_t)(-1); 920 CPTR cptrMask = 0; 921 cptrMask.tcpac = ones; 922 cptrMask.tta = ones; 923 cptrMask.tfp = ones; 924 newVal &= cptrMask; 925 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 926 miscRegName[misc_reg], newVal); 927 } 928 break; 929 case MISCREG_CSSELR: 930 warn_once("The csselr register isn't implemented.\n"); 931 return; 932 933 case MISCREG_DC_ZVA_Xt: 934 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 935 return; 936 937 case MISCREG_FPSCR: 938 { 939 const uint32_t ones = (uint32_t)(-1); 940 FPSCR fpscrMask = 0; 941 fpscrMask.ioc = ones; 942 fpscrMask.dzc = ones; 943 fpscrMask.ofc = ones; 944 fpscrMask.ufc = ones; 945 fpscrMask.ixc = ones; 946 fpscrMask.idc = ones; 947 fpscrMask.ioe = ones; 948 fpscrMask.dze = ones; 949 fpscrMask.ofe = ones; 950 fpscrMask.ufe = ones; 951 fpscrMask.ixe = ones; 952 fpscrMask.ide = ones; 953 fpscrMask.len = ones; 954 fpscrMask.stride = ones; 955 fpscrMask.rMode = ones; 956 fpscrMask.fz = ones; 957 fpscrMask.dn = ones; 958 fpscrMask.ahp = ones; 959 fpscrMask.qc = ones; 960 fpscrMask.v = ones; 961 fpscrMask.c = ones; 962 fpscrMask.z = ones; 963 fpscrMask.n = ones; 964 newVal = (newVal & (uint32_t)fpscrMask) | 965 (readMiscRegNoEffect(MISCREG_FPSCR) & 966 ~(uint32_t)fpscrMask); 967 tc->getDecoderPtr()->setContext(newVal); 968 } 969 break; 970 case MISCREG_FPSR: 971 { 972 const uint32_t ones = (uint32_t)(-1); 973 FPSCR fpscrMask = 0; 974 fpscrMask.ioc = ones; 975 fpscrMask.dzc = ones; 976 fpscrMask.ofc = ones; 977 fpscrMask.ufc = ones; 978 fpscrMask.ixc = ones; 979 fpscrMask.idc = ones; 980 fpscrMask.qc = ones; 981 fpscrMask.v = ones; 982 fpscrMask.c = ones; 983 fpscrMask.z = ones; 984 fpscrMask.n = ones; 985 newVal = (newVal & (uint32_t)fpscrMask) | 986 (readMiscRegNoEffect(MISCREG_FPSCR) & 987 ~(uint32_t)fpscrMask); 988 misc_reg = MISCREG_FPSCR; 989 } 990 break; 991 case MISCREG_FPCR: 992 { 993 const uint32_t ones = (uint32_t)(-1); 994 FPSCR fpscrMask = 0; 995 fpscrMask.ioe = ones; 996 fpscrMask.dze = ones; 997 fpscrMask.ofe = ones; 998 fpscrMask.ufe = ones; 999 fpscrMask.ixe = ones; 1000 fpscrMask.ide = ones; 1001 fpscrMask.len = ones; 1002 fpscrMask.stride = ones; 1003 fpscrMask.rMode = ones; 1004 fpscrMask.fz = ones; 1005 fpscrMask.dn = ones; 1006 fpscrMask.ahp = ones; 1007 newVal = (newVal & (uint32_t)fpscrMask) | 1008 (readMiscRegNoEffect(MISCREG_FPSCR) & 1009 ~(uint32_t)fpscrMask); 1010 misc_reg = MISCREG_FPSCR; 1011 } 1012 break; 1013 case MISCREG_CPSR_Q: 1014 { 1015 assert(!(newVal & ~CpsrMaskQ)); 1016 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 1017 misc_reg = MISCREG_CPSR; 1018 } 1019 break; 1020 case MISCREG_FPSCR_QC: 1021 { 1022 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1023 (newVal & FpscrQcMask); 1024 misc_reg = MISCREG_FPSCR; 1025 } 1026 break; 1027 case MISCREG_FPSCR_EXC: 1028 { 1029 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1030 (newVal & FpscrExcMask); 1031 misc_reg = MISCREG_FPSCR; 1032 } 1033 break; 1034 case MISCREG_FPEXC: 1035 { 1036 // vfpv3 architecture, section B.6.1 of DDI04068 1037 // bit 29 - valid only if fpexc[31] is 0 1038 const uint32_t fpexcMask = 0x60000000; 1039 newVal = (newVal & fpexcMask) | 1040 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1041 } 1042 break; 1043 case MISCREG_HCR: 1044 { 1045 if (!haveVirtualization) 1046 return; 1047 } 1048 break; 1049 case MISCREG_IFSR: 1050 { 1051 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1052 const uint32_t ifsrMask = 1053 mask(31, 13) | mask(11, 11) | mask(8, 6); 1054 newVal = newVal & ~ifsrMask; 1055 } 1056 break; 1057 case MISCREG_DFSR: 1058 { 1059 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1060 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1061 newVal = newVal & ~dfsrMask; 1062 } 1063 break; 1064 case MISCREG_AMAIR0: 1065 case MISCREG_AMAIR1: 1066 { 1067 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1068 // Valid only with LPAE 1069 if (!haveLPAE) 1070 return; 1071 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1072 } 1073 break; 1074 case MISCREG_SCR: 1075 tc->getITBPtr()->invalidateMiscReg(); 1076 tc->getDTBPtr()->invalidateMiscReg(); 1077 break; 1078 case MISCREG_SCTLR: 1079 { 1080 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1081 scr = readMiscRegNoEffect(MISCREG_SCR); 1082 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns) 1083 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS; 1084 SCTLR sctlr = miscRegs[sctlr_idx]; 1085 SCTLR new_sctlr = newVal; 1086 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1087 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1088 tc->getITBPtr()->invalidateMiscReg(); 1089 tc->getDTBPtr()->invalidateMiscReg(); 1090 } 1091 case MISCREG_MIDR: 1092 case MISCREG_ID_PFR0: 1093 case MISCREG_ID_PFR1: 1094 case MISCREG_ID_DFR0: 1095 case MISCREG_ID_MMFR0: 1096 case MISCREG_ID_MMFR1: 1097 case MISCREG_ID_MMFR2: 1098 case MISCREG_ID_MMFR3: 1099 case MISCREG_ID_ISAR0: 1100 case MISCREG_ID_ISAR1: 1101 case MISCREG_ID_ISAR2: 1102 case MISCREG_ID_ISAR3: 1103 case MISCREG_ID_ISAR4: 1104 case MISCREG_ID_ISAR5: 1105 1106 case MISCREG_MPIDR: 1107 case MISCREG_FPSID: 1108 case MISCREG_TLBTR: 1109 case MISCREG_MVFR0: 1110 case MISCREG_MVFR1: 1111 1112 case MISCREG_ID_AA64AFR0_EL1: 1113 case MISCREG_ID_AA64AFR1_EL1: 1114 case MISCREG_ID_AA64DFR0_EL1: 1115 case MISCREG_ID_AA64DFR1_EL1: 1116 case MISCREG_ID_AA64ISAR0_EL1: 1117 case MISCREG_ID_AA64ISAR1_EL1: 1118 case MISCREG_ID_AA64MMFR0_EL1: 1119 case MISCREG_ID_AA64MMFR1_EL1: 1120 case MISCREG_ID_AA64PFR0_EL1: 1121 case MISCREG_ID_AA64PFR1_EL1: 1122 // ID registers are constants. 1123 return; 1124 1125 // TLBI all entries, EL0&1 inner sharable (ignored) 1126 case MISCREG_TLBIALLIS: 1127 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1128 assert32(tc); 1129 target_el = 1; // el 0 and 1 are handled together 1130 scr = readMiscReg(MISCREG_SCR, tc); 1131 secure_lookup = haveSecurity && !scr.ns; 1132 sys = tc->getSystemPtr(); 1133 for (x = 0; x < sys->numContexts(); x++) { 1134 oc = sys->getThreadContext(x); 1135 assert(oc->getITBPtr() && oc->getDTBPtr()); 1136 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1137 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1138 1139 // If CheckerCPU is connected, need to notify it of a flush 1140 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1141 if (checker) { 1142 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1143 target_el); 1144 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1145 target_el); 1146 } 1147 } 1148 return; 1149 // TLBI all entries, EL0&1, instruction side 1150 case MISCREG_ITLBIALL: 1151 assert32(tc); 1152 target_el = 1; // el 0 and 1 are handled together 1153 scr = readMiscReg(MISCREG_SCR, tc); 1154 secure_lookup = haveSecurity && !scr.ns; 1155 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1156 return; 1157 // TLBI all entries, EL0&1, data side 1158 case MISCREG_DTLBIALL: 1159 assert32(tc); 1160 target_el = 1; // el 0 and 1 are handled together 1161 scr = readMiscReg(MISCREG_SCR, tc); 1162 secure_lookup = haveSecurity && !scr.ns; 1163 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1164 return; 1165 // TLBI based on VA, EL0&1 inner sharable (ignored) 1166 case MISCREG_TLBIMVAIS: 1167 case MISCREG_TLBIMVA: 1168 assert32(tc); 1169 target_el = 1; // el 0 and 1 are handled together 1170 scr = readMiscReg(MISCREG_SCR, tc); 1171 secure_lookup = haveSecurity && !scr.ns; 1172 sys = tc->getSystemPtr(); 1173 for (x = 0; x < sys->numContexts(); x++) { 1174 oc = sys->getThreadContext(x); 1175 assert(oc->getITBPtr() && oc->getDTBPtr()); 1176 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1177 bits(newVal, 7,0), 1178 secure_lookup, target_el); 1179 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1180 bits(newVal, 7,0), 1181 secure_lookup, target_el); 1182 1183 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1184 if (checker) { 1185 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1186 bits(newVal, 7,0), secure_lookup, target_el); 1187 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1188 bits(newVal, 7,0), secure_lookup, target_el); 1189 } 1190 } 1191 return; 1192 // TLBI by ASID, EL0&1, inner sharable 1193 case MISCREG_TLBIASIDIS: 1194 case MISCREG_TLBIASID: 1195 assert32(tc); 1196 target_el = 1; // el 0 and 1 are handled together 1197 scr = readMiscReg(MISCREG_SCR, tc); 1198 secure_lookup = haveSecurity && !scr.ns; 1199 sys = tc->getSystemPtr(); 1200 for (x = 0; x < sys->numContexts(); x++) { 1201 oc = sys->getThreadContext(x); 1202 assert(oc->getITBPtr() && oc->getDTBPtr()); 1203 oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 1204 secure_lookup, target_el); 1205 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1206 secure_lookup, target_el); 1207 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1208 if (checker) { 1209 checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 1210 secure_lookup, target_el); 1211 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1212 secure_lookup, target_el); 1213 } 1214 } 1215 return; 1216 // TLBI by address, EL0&1, inner sharable (ignored) 1217 case MISCREG_TLBIMVAAIS: 1218 case MISCREG_TLBIMVAA: 1219 assert32(tc); 1220 target_el = 1; // el 0 and 1 are handled together 1221 scr = readMiscReg(MISCREG_SCR, tc); 1222 secure_lookup = haveSecurity && !scr.ns; 1223 hyp = 0; 1224 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1225 return; 1226 // TLBI by address, EL2, hypervisor mode 1227 case MISCREG_TLBIMVAH: 1228 case MISCREG_TLBIMVAHIS: 1229 assert32(tc); 1230 target_el = 1; // aarch32, use hyp bit 1231 scr = readMiscReg(MISCREG_SCR, tc); 1232 secure_lookup = haveSecurity && !scr.ns; 1233 hyp = 1; 1234 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1235 return; 1236 // TLBI by address and asid, EL0&1, instruction side only 1237 case MISCREG_ITLBIMVA: 1238 assert32(tc); 1239 target_el = 1; // el 0 and 1 are handled together 1240 scr = readMiscReg(MISCREG_SCR, tc); 1241 secure_lookup = haveSecurity && !scr.ns; 1242 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1243 bits(newVal, 7,0), secure_lookup, target_el); 1244 return; 1245 // TLBI by address and asid, EL0&1, data side only 1246 case MISCREG_DTLBIMVA: 1247 assert32(tc); 1248 target_el = 1; // el 0 and 1 are handled together 1249 scr = readMiscReg(MISCREG_SCR, tc); 1250 secure_lookup = haveSecurity && !scr.ns; 1251 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1252 bits(newVal, 7,0), secure_lookup, target_el); 1253 return; 1254 // TLBI by ASID, EL0&1, instrution side only 1255 case MISCREG_ITLBIASID: 1256 assert32(tc); 1257 target_el = 1; // el 0 and 1 are handled together 1258 scr = readMiscReg(MISCREG_SCR, tc); 1259 secure_lookup = haveSecurity && !scr.ns; 1260 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1261 target_el); 1262 return; 1263 // TLBI by ASID EL0&1 data size only 1264 case MISCREG_DTLBIASID: 1265 assert32(tc); 1266 target_el = 1; // el 0 and 1 are handled together 1267 scr = readMiscReg(MISCREG_SCR, tc); 1268 secure_lookup = haveSecurity && !scr.ns; 1269 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1270 target_el); 1271 return; 1272 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1273 case MISCREG_TLBIALLNSNH: 1274 case MISCREG_TLBIALLNSNHIS: 1275 assert32(tc); 1276 target_el = 1; // el 0 and 1 are handled together 1277 hyp = 0; 1278 tlbiALLN(tc, hyp, target_el); 1279 return; 1280 // TLBI all entries, EL2, hyp, 1281 case MISCREG_TLBIALLH: 1282 case MISCREG_TLBIALLHIS: 1283 assert32(tc); 1284 target_el = 1; // aarch32, use hyp bit 1285 hyp = 1; 1286 tlbiALLN(tc, hyp, target_el); 1287 return; 1288 // AArch64 TLBI: invalidate all entries EL3 1289 case MISCREG_TLBI_ALLE3IS: 1290 case MISCREG_TLBI_ALLE3: 1291 assert64(tc); 1292 target_el = 3; 1293 secure_lookup = true; 1294 tlbiALL(tc, secure_lookup, target_el); 1295 return; 1296 // @todo: uncomment this to enable Virtualization 1297 // case MISCREG_TLBI_ALLE2IS: 1298 // case MISCREG_TLBI_ALLE2: 1299 // TLBI all entries, EL0&1 1300 case MISCREG_TLBI_ALLE1IS: 1301 case MISCREG_TLBI_ALLE1: 1302 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1303 case MISCREG_TLBI_VMALLE1IS: 1304 case MISCREG_TLBI_VMALLE1: 1305 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1306 case MISCREG_TLBI_VMALLS12E1IS: 1307 case MISCREG_TLBI_VMALLS12E1: 1308 // @todo: handle VMID and stage 2 to enable Virtualization 1309 assert64(tc); 1310 target_el = 1; // el 0 and 1 are handled together 1311 scr = readMiscReg(MISCREG_SCR, tc); 1312 secure_lookup = haveSecurity && !scr.ns; 1313 tlbiALL(tc, secure_lookup, target_el); 1314 return; 1315 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1316 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1317 // from the last level of translation table walks 1318 // @todo: handle VMID to enable Virtualization 1319 // TLBI all entries, EL0&1 1320 case MISCREG_TLBI_VAE3IS_Xt: 1321 case MISCREG_TLBI_VAE3_Xt: 1322 // TLBI by VA, EL3 regime stage 1, last level walk 1323 case MISCREG_TLBI_VALE3IS_Xt: 1324 case MISCREG_TLBI_VALE3_Xt: 1325 assert64(tc); 1326 target_el = 3; 1327 asid = 0xbeef; // does not matter, tlbi is global 1328 secure_lookup = true; 1329 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1330 return; 1331 // TLBI by VA, EL2 1332 case MISCREG_TLBI_VAE2IS_Xt: 1333 case MISCREG_TLBI_VAE2_Xt: 1334 // TLBI by VA, EL2, stage1 last level walk 1335 case MISCREG_TLBI_VALE2IS_Xt: 1336 case MISCREG_TLBI_VALE2_Xt: 1337 assert64(tc); 1338 target_el = 2; 1339 asid = 0xbeef; // does not matter, tlbi is global 1340 scr = readMiscReg(MISCREG_SCR, tc); 1341 secure_lookup = haveSecurity && !scr.ns; 1342 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1343 return; 1344 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1345 case MISCREG_TLBI_VAE1IS_Xt: 1346 case MISCREG_TLBI_VAE1_Xt: 1347 case MISCREG_TLBI_VALE1IS_Xt: 1348 case MISCREG_TLBI_VALE1_Xt: 1349 assert64(tc); 1350 asid = bits(newVal, 63, 48); 1351 target_el = 1; // el 0 and 1 are handled together 1352 scr = readMiscReg(MISCREG_SCR, tc); 1353 secure_lookup = haveSecurity && !scr.ns; 1354 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1355 return; 1356 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1357 // @todo: handle VMID to enable Virtualization 1358 case MISCREG_TLBI_ASIDE1IS_Xt: 1359 case MISCREG_TLBI_ASIDE1_Xt: 1360 assert64(tc); 1361 target_el = 1; // el 0 and 1 are handled together 1362 scr = readMiscReg(MISCREG_SCR, tc); 1363 secure_lookup = haveSecurity && !scr.ns; 1364 sys = tc->getSystemPtr(); 1365 for (x = 0; x < sys->numContexts(); x++) { 1366 oc = sys->getThreadContext(x); 1367 assert(oc->getITBPtr() && oc->getDTBPtr()); 1368 asid = bits(newVal, 63, 48); 1369 if (!haveLargeAsid64) 1370 asid &= mask(8); 1371 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1372 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1373 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1374 if (checker) { 1375 checker->getITBPtr()->flushAsid(asid, 1376 secure_lookup, target_el); 1377 checker->getDTBPtr()->flushAsid(asid, 1378 secure_lookup, target_el); 1379 } 1380 } 1381 return; 1382 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1383 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1384 // entries from the last level of translation table walks 1385 // @todo: handle VMID to enable Virtualization 1386 case MISCREG_TLBI_VAAE1IS_Xt: 1387 case MISCREG_TLBI_VAAE1_Xt: 1388 case MISCREG_TLBI_VAALE1IS_Xt: 1389 case MISCREG_TLBI_VAALE1_Xt: 1390 assert64(tc); 1391 target_el = 1; // el 0 and 1 are handled together 1392 scr = readMiscReg(MISCREG_SCR, tc); 1393 secure_lookup = haveSecurity && !scr.ns; 1394 sys = tc->getSystemPtr(); 1395 for (x = 0; x < sys->numContexts(); x++) { 1396 // @todo: extra controls on TLBI broadcast? 1397 oc = sys->getThreadContext(x); 1398 assert(oc->getITBPtr() && oc->getDTBPtr()); 1399 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1400 oc->getITBPtr()->flushMva(va, 1401 secure_lookup, false, target_el); 1402 oc->getDTBPtr()->flushMva(va, 1403 secure_lookup, false, target_el); 1404 1405 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1406 if (checker) { 1407 checker->getITBPtr()->flushMva(va, 1408 secure_lookup, false, target_el); 1409 checker->getDTBPtr()->flushMva(va, 1410 secure_lookup, false, target_el); 1411 } 1412 } 1413 return; 1414 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1415 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1416 case MISCREG_TLBI_IPAS2LE1_Xt: 1417 case MISCREG_TLBI_IPAS2E1IS_Xt: 1418 case MISCREG_TLBI_IPAS2E1_Xt: 1419 assert64(tc); 1420 target_el = 1; // EL 0 and 1 are handled together 1421 scr = readMiscReg(MISCREG_SCR, tc); 1422 secure_lookup = haveSecurity && !scr.ns; 1423 sys = tc->getSystemPtr(); 1424 for (x = 0; x < sys->numContexts(); x++) { 1425 oc = sys->getThreadContext(x); 1426 assert(oc->getITBPtr() && oc->getDTBPtr()); 1427 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; 1428 oc->getITBPtr()->flushIpaVmid(ipa, 1429 secure_lookup, false, target_el); 1430 oc->getDTBPtr()->flushIpaVmid(ipa, 1431 secure_lookup, false, target_el); 1432 1433 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1434 if (checker) { 1435 checker->getITBPtr()->flushIpaVmid(ipa, 1436 secure_lookup, false, target_el); 1437 checker->getDTBPtr()->flushIpaVmid(ipa, 1438 secure_lookup, false, target_el); 1439 } 1440 } 1441 return; 1442 case MISCREG_ACTLR: 1443 warn("Not doing anything for write of miscreg ACTLR\n"); 1444 break; 1445 1446 case MISCREG_PMXEVTYPER_PMCCFILTR: 1447 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1448 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1449 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1450 pmu->setMiscReg(misc_reg, newVal); 1451 break; 1452 1453 1454 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1455 { 1456 HSTR hstrMask = 0; 1457 hstrMask.tjdbx = 1; 1458 newVal &= ~((uint32_t) hstrMask); 1459 break; 1460 } 1461 case MISCREG_HCPTR: 1462 { 1463 // If a CP bit in NSACR is 0 then the corresponding bit in 1464 // HCPTR is RAO/WI. Same applies to NSASEDIS 1465 secure_lookup = haveSecurity && 1466 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1467 readMiscRegNoEffect(MISCREG_CPSR)); 1468 if (!secure_lookup) { 1469 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1470 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1471 newVal = (newVal & ~mask) | (oldValue & mask); 1472 } 1473 break; 1474 } 1475 case MISCREG_HDFAR: // alias for secure DFAR 1476 misc_reg = MISCREG_DFAR_S; 1477 break; 1478 case MISCREG_HIFAR: // alias for secure IFAR 1479 misc_reg = MISCREG_IFAR_S; 1480 break; 1481 case MISCREG_ATS1CPR: 1482 case MISCREG_ATS1CPW: 1483 case MISCREG_ATS1CUR: 1484 case MISCREG_ATS1CUW: 1485 case MISCREG_ATS12NSOPR: 1486 case MISCREG_ATS12NSOPW: 1487 case MISCREG_ATS12NSOUR: 1488 case MISCREG_ATS12NSOUW: 1489 case MISCREG_ATS1HR: 1490 case MISCREG_ATS1HW: 1491 { 1492 Request::Flags flags = 0; 1493 BaseTLB::Mode mode = BaseTLB::Read; 1494 TLB::ArmTranslationType tranType = TLB::NormalTran; 1495 Fault fault; 1496 switch(misc_reg) { 1497 case MISCREG_ATS1CPR: 1498 flags = TLB::MustBeOne; 1499 tranType = TLB::S1CTran; 1500 mode = BaseTLB::Read; 1501 break; 1502 case MISCREG_ATS1CPW: 1503 flags = TLB::MustBeOne; 1504 tranType = TLB::S1CTran; 1505 mode = BaseTLB::Write; 1506 break; 1507 case MISCREG_ATS1CUR: 1508 flags = TLB::MustBeOne | TLB::UserMode; 1509 tranType = TLB::S1CTran; 1510 mode = BaseTLB::Read; 1511 break; 1512 case MISCREG_ATS1CUW: 1513 flags = TLB::MustBeOne | TLB::UserMode; 1514 tranType = TLB::S1CTran; 1515 mode = BaseTLB::Write; 1516 break; 1517 case MISCREG_ATS12NSOPR: 1518 if (!haveSecurity) 1519 panic("Security Extensions required for ATS12NSOPR"); 1520 flags = TLB::MustBeOne; 1521 tranType = TLB::S1S2NsTran; 1522 mode = BaseTLB::Read; 1523 break; 1524 case MISCREG_ATS12NSOPW: 1525 if (!haveSecurity) 1526 panic("Security Extensions required for ATS12NSOPW"); 1527 flags = TLB::MustBeOne; 1528 tranType = TLB::S1S2NsTran; 1529 mode = BaseTLB::Write; 1530 break; 1531 case MISCREG_ATS12NSOUR: 1532 if (!haveSecurity) 1533 panic("Security Extensions required for ATS12NSOUR"); 1534 flags = TLB::MustBeOne | TLB::UserMode; 1535 tranType = TLB::S1S2NsTran; 1536 mode = BaseTLB::Read; 1537 break; 1538 case MISCREG_ATS12NSOUW: 1539 if (!haveSecurity) 1540 panic("Security Extensions required for ATS12NSOUW"); 1541 flags = TLB::MustBeOne | TLB::UserMode; 1542 tranType = TLB::S1S2NsTran; 1543 mode = BaseTLB::Write; 1544 break; 1545 case MISCREG_ATS1HR: // only really useful from secure mode. 1546 flags = TLB::MustBeOne; 1547 tranType = TLB::HypMode; 1548 mode = BaseTLB::Read; 1549 break; 1550 case MISCREG_ATS1HW: 1551 flags = TLB::MustBeOne; 1552 tranType = TLB::HypMode; 1553 mode = BaseTLB::Write; 1554 break; 1555 } 1556 // If we're in timing mode then doing the translation in 1557 // functional mode then we're slightly distorting performance 1558 // results obtained from simulations. The translation should be 1559 // done in the same mode the core is running in. NOTE: This 1560 // can't be an atomic translation because that causes problems 1561 // with unexpected atomic snoop requests. 1562 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1563 Request req(0, val, 0, flags, Request::funcMasterId, 1564 tc->pcState().pc(), tc->contextId()); 1565 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 1566 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1567 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1568 1569 MiscReg newVal; 1570 if (fault == NoFault) { 1571 Addr paddr = req.getPaddr(); 1572 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1573 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1574 newVal = (paddr & mask(39, 12)) | 1575 (tc->getDTBPtr()->getAttr()); 1576 } else { 1577 newVal = (paddr & 0xfffff000) | 1578 (tc->getDTBPtr()->getAttr()); 1579 } 1580 DPRINTF(MiscRegs, 1581 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1582 val, newVal); 1583 } else { 1584 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1585 // Set fault bit and FSR 1586 FSR fsr = armFault->getFsr(tc); 1587 1588 newVal = ((fsr >> 9) & 1) << 11; 1589 if (newVal) { 1590 // LPAE - rearange fault status 1591 newVal |= ((fsr >> 0) & 0x3f) << 1; 1592 } else { 1593 // VMSA - rearange fault status 1594 newVal |= ((fsr >> 0) & 0xf) << 1; 1595 newVal |= ((fsr >> 10) & 0x1) << 5; 1596 newVal |= ((fsr >> 12) & 0x1) << 6; 1597 } 1598 newVal |= 0x1; // F bit 1599 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1600 newVal |= armFault->isStage2() ? 0x200 : 0; 1601 DPRINTF(MiscRegs, 1602 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1603 val, fsr, newVal); 1604 } 1605 setMiscRegNoEffect(MISCREG_PAR, newVal); 1606 return; 1607 } 1608 case MISCREG_TTBCR: 1609 { 1610 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1611 const uint32_t ones = (uint32_t)(-1); 1612 TTBCR ttbcrMask = 0; 1613 TTBCR ttbcrNew = newVal; 1614 1615 // ARM DDI 0406C.b, ARMv7-32 1616 ttbcrMask.n = ones; // T0SZ 1617 if (haveSecurity) { 1618 ttbcrMask.pd0 = ones; 1619 ttbcrMask.pd1 = ones; 1620 } 1621 ttbcrMask.epd0 = ones; 1622 ttbcrMask.irgn0 = ones; 1623 ttbcrMask.orgn0 = ones; 1624 ttbcrMask.sh0 = ones; 1625 ttbcrMask.ps = ones; // T1SZ 1626 ttbcrMask.a1 = ones; 1627 ttbcrMask.epd1 = ones; 1628 ttbcrMask.irgn1 = ones; 1629 ttbcrMask.orgn1 = ones; 1630 ttbcrMask.sh1 = ones; 1631 if (haveLPAE) 1632 ttbcrMask.eae = ones; 1633 1634 if (haveLPAE && ttbcrNew.eae) { 1635 newVal = newVal & ttbcrMask; 1636 } else { 1637 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1638 } 1639 } 1640 case MISCREG_TTBR0: 1641 case MISCREG_TTBR1: 1642 { 1643 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1644 if (haveLPAE) { 1645 if (ttbcr.eae) { 1646 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1647 // ARMv8 AArch32 bit 63-56 only 1648 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1649 newVal = (newVal & (~ttbrMask)); 1650 } 1651 } 1652 } 1653 case MISCREG_SCTLR_EL1: 1654 { 1655 tc->getITBPtr()->invalidateMiscReg(); 1656 tc->getDTBPtr()->invalidateMiscReg(); 1657 setMiscRegNoEffect(misc_reg, newVal); 1658 } 1659 case MISCREG_CONTEXTIDR: 1660 case MISCREG_PRRR: 1661 case MISCREG_NMRR: 1662 case MISCREG_MAIR0: 1663 case MISCREG_MAIR1: 1664 case MISCREG_DACR: 1665 case MISCREG_VTTBR: 1666 case MISCREG_SCR_EL3: 1667 case MISCREG_HCR_EL2: 1668 case MISCREG_TCR_EL1: 1669 case MISCREG_TCR_EL2: 1670 case MISCREG_TCR_EL3: 1671 case MISCREG_SCTLR_EL2: 1672 case MISCREG_SCTLR_EL3: 1673 case MISCREG_HSCTLR: 1674 case MISCREG_TTBR0_EL1: 1675 case MISCREG_TTBR1_EL1: 1676 case MISCREG_TTBR0_EL2: 1677 case MISCREG_TTBR0_EL3: 1678 tc->getITBPtr()->invalidateMiscReg(); 1679 tc->getDTBPtr()->invalidateMiscReg(); 1680 break; 1681 case MISCREG_NZCV: 1682 { 1683 CPSR cpsr = val; 1684 1685 tc->setCCReg(CCREG_NZ, cpsr.nz); 1686 tc->setCCReg(CCREG_C, cpsr.c); 1687 tc->setCCReg(CCREG_V, cpsr.v); 1688 } 1689 break; 1690 case MISCREG_DAIF: 1691 { 1692 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1693 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1694 newVal = cpsr; 1695 misc_reg = MISCREG_CPSR; 1696 } 1697 break; 1698 case MISCREG_SP_EL0: 1699 tc->setIntReg(INTREG_SP0, newVal); 1700 break; 1701 case MISCREG_SP_EL1: 1702 tc->setIntReg(INTREG_SP1, newVal); 1703 break; 1704 case MISCREG_SP_EL2: 1705 tc->setIntReg(INTREG_SP2, newVal); 1706 break; 1707 case MISCREG_SPSEL: 1708 { 1709 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1710 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1711 newVal = cpsr; 1712 misc_reg = MISCREG_CPSR; 1713 } 1714 break; 1715 case MISCREG_CURRENTEL: 1716 { 1717 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1718 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1719 newVal = cpsr; 1720 misc_reg = MISCREG_CPSR; 1721 } 1722 break; 1723 case MISCREG_AT_S1E1R_Xt: 1724 case MISCREG_AT_S1E1W_Xt: 1725 case MISCREG_AT_S1E0R_Xt: 1726 case MISCREG_AT_S1E0W_Xt: 1727 case MISCREG_AT_S1E2R_Xt: 1728 case MISCREG_AT_S1E2W_Xt: 1729 case MISCREG_AT_S12E1R_Xt: 1730 case MISCREG_AT_S12E1W_Xt: 1731 case MISCREG_AT_S12E0R_Xt: 1732 case MISCREG_AT_S12E0W_Xt: 1733 case MISCREG_AT_S1E3R_Xt: 1734 case MISCREG_AT_S1E3W_Xt: 1735 { 1736 RequestPtr req = new Request; 1737 Request::Flags flags = 0; 1738 BaseTLB::Mode mode = BaseTLB::Read; 1739 TLB::ArmTranslationType tranType = TLB::NormalTran; 1740 Fault fault; 1741 switch(misc_reg) { 1742 case MISCREG_AT_S1E1R_Xt: 1743 flags = TLB::MustBeOne; 1744 tranType = TLB::S1E1Tran; 1745 mode = BaseTLB::Read; 1746 break; 1747 case MISCREG_AT_S1E1W_Xt: 1748 flags = TLB::MustBeOne; 1749 tranType = TLB::S1E1Tran; 1750 mode = BaseTLB::Write; 1751 break; 1752 case MISCREG_AT_S1E0R_Xt: 1753 flags = TLB::MustBeOne | TLB::UserMode; 1754 tranType = TLB::S1E0Tran; 1755 mode = BaseTLB::Read; 1756 break; 1757 case MISCREG_AT_S1E0W_Xt: 1758 flags = TLB::MustBeOne | TLB::UserMode; 1759 tranType = TLB::S1E0Tran; 1760 mode = BaseTLB::Write; 1761 break; 1762 case MISCREG_AT_S1E2R_Xt: 1763 flags = TLB::MustBeOne; 1764 tranType = TLB::S1E2Tran; 1765 mode = BaseTLB::Read; 1766 break; 1767 case MISCREG_AT_S1E2W_Xt: 1768 flags = TLB::MustBeOne; 1769 tranType = TLB::S1E2Tran; 1770 mode = BaseTLB::Write; 1771 break; 1772 case MISCREG_AT_S12E0R_Xt: 1773 flags = TLB::MustBeOne | TLB::UserMode; 1774 tranType = TLB::S12E0Tran; 1775 mode = BaseTLB::Read; 1776 break; 1777 case MISCREG_AT_S12E0W_Xt: 1778 flags = TLB::MustBeOne | TLB::UserMode; 1779 tranType = TLB::S12E0Tran; 1780 mode = BaseTLB::Write; 1781 break; 1782 case MISCREG_AT_S12E1R_Xt: 1783 flags = TLB::MustBeOne; 1784 tranType = TLB::S12E1Tran; 1785 mode = BaseTLB::Read; 1786 break; 1787 case MISCREG_AT_S12E1W_Xt: 1788 flags = TLB::MustBeOne; 1789 tranType = TLB::S12E1Tran; 1790 mode = BaseTLB::Write; 1791 break; 1792 case MISCREG_AT_S1E3R_Xt: 1793 flags = TLB::MustBeOne; 1794 tranType = TLB::S1E3Tran; 1795 mode = BaseTLB::Read; 1796 break; 1797 case MISCREG_AT_S1E3W_Xt: 1798 flags = TLB::MustBeOne; 1799 tranType = TLB::S1E3Tran; 1800 mode = BaseTLB::Write; 1801 break; 1802 } 1803 // If we're in timing mode then doing the translation in 1804 // functional mode then we're slightly distorting performance 1805 // results obtained from simulations. The translation should be 1806 // done in the same mode the core is running in. NOTE: This 1807 // can't be an atomic translation because that causes problems 1808 // with unexpected atomic snoop requests. 1809 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1810 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1811 tc->pcState().pc()); 1812 req->setContext(tc->contextId()); 1813 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1814 tranType); 1815 1816 MiscReg newVal; 1817 if (fault == NoFault) { 1818 Addr paddr = req->getPaddr(); 1819 uint64_t attr = tc->getDTBPtr()->getAttr(); 1820 uint64_t attr1 = attr >> 56; 1821 if (!attr1 || attr1 ==0x44) { 1822 attr |= 0x100; 1823 attr &= ~ uint64_t(0x80); 1824 } 1825 newVal = (paddr & mask(47, 12)) | attr; 1826 DPRINTF(MiscRegs, 1827 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1828 val, newVal); 1829 } else { 1830 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1831 // Set fault bit and FSR 1832 FSR fsr = armFault->getFsr(tc); 1833 1834 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1835 if (cpsr.width) { // AArch32 1836 newVal = ((fsr >> 9) & 1) << 11; 1837 // rearrange fault status 1838 newVal |= ((fsr >> 0) & 0x3f) << 1; 1839 newVal |= 0x1; // F bit 1840 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1841 newVal |= armFault->isStage2() ? 0x200 : 0; 1842 } else { // AArch64 1843 newVal = 1; // F bit 1844 newVal |= fsr << 1; // FST 1845 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1846 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1847 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1848 newVal |= 1 << 11; // RES1 1849 } 1850 DPRINTF(MiscRegs, 1851 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1852 val, fsr, newVal); 1853 } 1854 delete req; 1855 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1856 return; 1857 } 1858 case MISCREG_SPSR_EL3: 1859 case MISCREG_SPSR_EL2: 1860 case MISCREG_SPSR_EL1: 1861 // Force bits 23:21 to 0 1862 newVal = val & ~(0x7 << 21); 1863 break; 1864 case MISCREG_L2CTLR: 1865 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1866 miscRegName[misc_reg], uint32_t(val)); 1867 break; 1868 1869 // Generic Timer registers 1870 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1871 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1872 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1873 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1874 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1875 break; 1876 } 1877 } 1878 setMiscRegNoEffect(misc_reg, newVal); 1879} 1880 1881void 1882ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 1883 bool secure_lookup, uint8_t target_el) 1884{ 1885 if (!haveLargeAsid64) 1886 asid &= mask(8); 1887 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1888 System *sys = tc->getSystemPtr(); 1889 for (int x = 0; x < sys->numContexts(); x++) { 1890 ThreadContext *oc = sys->getThreadContext(x); 1891 assert(oc->getITBPtr() && oc->getDTBPtr()); 1892 oc->getITBPtr()->flushMvaAsid(va, asid, 1893 secure_lookup, target_el); 1894 oc->getDTBPtr()->flushMvaAsid(va, asid, 1895 secure_lookup, target_el); 1896 1897 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1898 if (checker) { 1899 checker->getITBPtr()->flushMvaAsid( 1900 va, asid, secure_lookup, target_el); 1901 checker->getDTBPtr()->flushMvaAsid( 1902 va, asid, secure_lookup, target_el); 1903 } 1904 } 1905} 1906 1907void 1908ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1909{ 1910 System *sys = tc->getSystemPtr(); 1911 for (int x = 0; x < sys->numContexts(); x++) { 1912 ThreadContext *oc = sys->getThreadContext(x); 1913 assert(oc->getITBPtr() && oc->getDTBPtr()); 1914 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1915 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1916 1917 // If CheckerCPU is connected, need to notify it of a flush 1918 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1919 if (checker) { 1920 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1921 target_el); 1922 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1923 target_el); 1924 } 1925 } 1926} 1927 1928void 1929ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1930{ 1931 System *sys = tc->getSystemPtr(); 1932 for (int x = 0; x < sys->numContexts(); x++) { 1933 ThreadContext *oc = sys->getThreadContext(x); 1934 assert(oc->getITBPtr() && oc->getDTBPtr()); 1935 oc->getITBPtr()->flushAllNs(hyp, target_el); 1936 oc->getDTBPtr()->flushAllNs(hyp, target_el); 1937 1938 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1939 if (checker) { 1940 checker->getITBPtr()->flushAllNs(hyp, target_el); 1941 checker->getDTBPtr()->flushAllNs(hyp, target_el); 1942 } 1943 } 1944} 1945 1946void 1947ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 1948 uint8_t target_el) 1949{ 1950 System *sys = tc->getSystemPtr(); 1951 for (int x = 0; x < sys->numContexts(); x++) { 1952 ThreadContext *oc = sys->getThreadContext(x); 1953 assert(oc->getITBPtr() && oc->getDTBPtr()); 1954 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 1955 secure_lookup, hyp, target_el); 1956 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1957 secure_lookup, hyp, target_el); 1958 1959 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1960 if (checker) { 1961 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 1962 secure_lookup, hyp, target_el); 1963 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1964 secure_lookup, hyp, target_el); 1965 } 1966 } 1967} 1968 1969BaseISADevice & 1970ISA::getGenericTimer(ThreadContext *tc) 1971{ 1972 // We only need to create an ISA interface the first time we try 1973 // to access the timer. 1974 if (timer) 1975 return *timer.get(); 1976 1977 assert(system); 1978 GenericTimer *generic_timer(system->getGenericTimer()); 1979 if (!generic_timer) { 1980 panic("Trying to get a generic timer from a system that hasn't " 1981 "been configured to use a generic timer.\n"); 1982 } 1983 1984 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1985 return *timer.get(); 1986} 1987 1988} 1989 1990ArmISA::ISA * 1991ArmISAParams::create() 1992{ 1993 return new ArmISA::ISA(this); 1994} 1995