isa.cc revision 10709
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "cpu/checker/cpu.hh"
45#include "cpu/base.hh"
46#include "debug/Arm.hh"
47#include "debug/MiscRegs.hh"
48#include "params/ArmISA.hh"
49#include "sim/faults.hh"
50#include "sim/stat_control.hh"
51#include "sim/system.hh"
52
53namespace ArmISA
54{
55
56
57/**
58 * Some registers aliase with others, and therefore need to be translated.
59 * For each entry:
60 * The first value is the misc register that is to be looked up
61 * the second value is the lower part of the translation
62 * the third the upper part
63 */
64const struct ISA::MiscRegInitializerEntry
65    ISA::MiscRegSwitch[miscRegTranslateMax] = {
66    {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}},
67    {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}},
68    {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}},
69    {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}},
70    {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}},
71    {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}},
72    {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}},
73    {MISCREG_HCR_EL2, {MISCREG_HCR, 0}},
74    {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}},
75    {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}},
76    {MISCREG_HACR_EL2, {MISCREG_HACR, 0}},
77    {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}},
78    {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}},
79    {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}},
80    {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}},
81    {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}},
82    {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}},
83    {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}},
84    {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}},
85    {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}},
86    {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}},
87    {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}},
88    {MISCREG_ESR_EL2, {MISCREG_HSR, 0}},
89    {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}},
90    {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}},
91    {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}},
92    {MISCREG_PAR_EL1, {MISCREG_PAR, 0}},
93    {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}},
94    {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}},
95    {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}},
96    {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}},
97    {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}},
98    {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}},
99    {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}},
100    {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}},
101    {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}},
102    {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}},
103    {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}},
104    {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}},
105    {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}},
106    {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}},
107    {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}},
108    {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}},
109    {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}},
110    {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}},
111    {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}},
112    {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}},
113    {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}},
114    {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}},
115    {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}},
116    {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}},
117    {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}},
118    {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}},
119    {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}},
120    {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}},
121    {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}},
122    {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}
123};
124
125
126ISA::ISA(Params *p)
127    : SimObject(p),
128      system(NULL),
129      pmu(p->pmu),
130      lookUpMiscReg(NUM_MISCREGS, {0,0})
131{
132    SCTLR sctlr;
133    sctlr = 0;
134    miscRegs[MISCREG_SCTLR_RST] = sctlr;
135
136    // Hook up a dummy device if we haven't been configured with a
137    // real PMU. By using a dummy device, we don't need to check that
138    // the PMU exist every time we try to access a PMU register.
139    if (!pmu)
140        pmu = &dummyDevice;
141
142    // Give all ISA devices a pointer to this ISA
143    pmu->setISA(this);
144
145    system = dynamic_cast<ArmSystem *>(p->system);
146    DPRINTFN("ISA system set to: %p %p\n", system, p->system);
147
148    // Cache system-level properties
149    if (FullSystem && system) {
150        haveSecurity = system->haveSecurity();
151        haveLPAE = system->haveLPAE();
152        haveVirtualization = system->haveVirtualization();
153        haveLargeAsid64 = system->haveLargeAsid64();
154        physAddrRange64 = system->physAddrRange64();
155    } else {
156        haveSecurity = haveLPAE = haveVirtualization = false;
157        haveLargeAsid64 = false;
158        physAddrRange64 = 32;  // dummy value
159    }
160
161    /** Fill in the miscReg translation table */
162    for (uint32_t i = 0; i < miscRegTranslateMax; i++) {
163        struct MiscRegLUTEntry new_entry;
164
165        uint32_t select = MiscRegSwitch[i].index;
166        new_entry = MiscRegSwitch[i].entry;
167
168        lookUpMiscReg[select] = new_entry;
169    }
170
171    preUnflattenMiscReg();
172
173    clear();
174}
175
176const ArmISAParams *
177ISA::params() const
178{
179    return dynamic_cast<const Params *>(_params);
180}
181
182void
183ISA::clear()
184{
185    const Params *p(params());
186
187    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
188    memset(miscRegs, 0, sizeof(miscRegs));
189
190    // Initialize configurable default values
191    miscRegs[MISCREG_MIDR] = p->midr;
192    miscRegs[MISCREG_MIDR_EL1] = p->midr;
193    miscRegs[MISCREG_VPIDR] = p->midr;
194
195    if (FullSystem && system->highestELIs64()) {
196        // Initialize AArch64 state
197        clear64(p);
198        return;
199    }
200
201    // Initialize AArch32 state...
202
203    CPSR cpsr = 0;
204    cpsr.mode = MODE_USER;
205    miscRegs[MISCREG_CPSR] = cpsr;
206    updateRegMap(cpsr);
207
208    SCTLR sctlr = 0;
209    sctlr.te = (bool) sctlr_rst.te;
210    sctlr.nmfi = (bool) sctlr_rst.nmfi;
211    sctlr.v = (bool) sctlr_rst.v;
212    sctlr.u = 1;
213    sctlr.xp = 1;
214    sctlr.rao2 = 1;
215    sctlr.rao3 = 1;
216    sctlr.rao4 = 0xf;  // SCTLR[6:3]
217    sctlr.uci = 1;
218    sctlr.dze = 1;
219    miscRegs[MISCREG_SCTLR_NS] = sctlr;
220    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
221    miscRegs[MISCREG_HCPTR] = 0;
222
223    // Start with an event in the mailbox
224    miscRegs[MISCREG_SEV_MAILBOX] = 1;
225
226    // Separate Instruction and Data TLBs
227    miscRegs[MISCREG_TLBTR] = 1;
228
229    MVFR0 mvfr0 = 0;
230    mvfr0.advSimdRegisters = 2;
231    mvfr0.singlePrecision = 2;
232    mvfr0.doublePrecision = 2;
233    mvfr0.vfpExceptionTrapping = 0;
234    mvfr0.divide = 1;
235    mvfr0.squareRoot = 1;
236    mvfr0.shortVectors = 1;
237    mvfr0.roundingModes = 1;
238    miscRegs[MISCREG_MVFR0] = mvfr0;
239
240    MVFR1 mvfr1 = 0;
241    mvfr1.flushToZero = 1;
242    mvfr1.defaultNaN = 1;
243    mvfr1.advSimdLoadStore = 1;
244    mvfr1.advSimdInteger = 1;
245    mvfr1.advSimdSinglePrecision = 1;
246    mvfr1.advSimdHalfPrecision = 1;
247    mvfr1.vfpHalfPrecision = 1;
248    miscRegs[MISCREG_MVFR1] = mvfr1;
249
250    // Reset values of PRRR and NMRR are implementation dependent
251
252    // @todo: PRRR and NMRR in secure state?
253    miscRegs[MISCREG_PRRR_NS] =
254        (1 << 19) | // 19
255        (0 << 18) | // 18
256        (0 << 17) | // 17
257        (1 << 16) | // 16
258        (2 << 14) | // 15:14
259        (0 << 12) | // 13:12
260        (2 << 10) | // 11:10
261        (2 << 8)  | // 9:8
262        (2 << 6)  | // 7:6
263        (2 << 4)  | // 5:4
264        (1 << 2)  | // 3:2
265        0;          // 1:0
266    miscRegs[MISCREG_NMRR_NS] =
267        (1 << 30) | // 31:30
268        (0 << 26) | // 27:26
269        (0 << 24) | // 25:24
270        (3 << 22) | // 23:22
271        (2 << 20) | // 21:20
272        (0 << 18) | // 19:18
273        (0 << 16) | // 17:16
274        (1 << 14) | // 15:14
275        (0 << 12) | // 13:12
276        (2 << 10) | // 11:10
277        (0 << 8)  | // 9:8
278        (3 << 6)  | // 7:6
279        (2 << 4)  | // 5:4
280        (0 << 2)  | // 3:2
281        0;          // 1:0
282
283    miscRegs[MISCREG_CPACR] = 0;
284
285
286    miscRegs[MISCREG_ID_PFR0] = p->id_pfr0;
287    miscRegs[MISCREG_ID_PFR1] = p->id_pfr1;
288
289    miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
290    miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
291    miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
292    miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
293
294    miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
295    miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
296    miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
297    miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
298    miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
299    miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
300
301    miscRegs[MISCREG_FPSID] = p->fpsid;
302
303    if (haveLPAE) {
304        TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
305        ttbcr.eae = 0;
306        miscRegs[MISCREG_TTBCR_NS] = ttbcr;
307        // Enforce consistency with system-level settings
308        miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
309    }
310
311    if (haveSecurity) {
312        miscRegs[MISCREG_SCTLR_S] = sctlr;
313        miscRegs[MISCREG_SCR] = 0;
314        miscRegs[MISCREG_VBAR_S] = 0;
315    } else {
316        // we're always non-secure
317        miscRegs[MISCREG_SCR] = 1;
318    }
319
320    //XXX We need to initialize the rest of the state.
321}
322
323void
324ISA::clear64(const ArmISAParams *p)
325{
326    CPSR cpsr = 0;
327    Addr rvbar = system->resetAddr64();
328    switch (system->highestEL()) {
329        // Set initial EL to highest implemented EL using associated stack
330        // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
331        // value
332      case EL3:
333        cpsr.mode = MODE_EL3H;
334        miscRegs[MISCREG_RVBAR_EL3] = rvbar;
335        break;
336      case EL2:
337        cpsr.mode = MODE_EL2H;
338        miscRegs[MISCREG_RVBAR_EL2] = rvbar;
339        break;
340      case EL1:
341        cpsr.mode = MODE_EL1H;
342        miscRegs[MISCREG_RVBAR_EL1] = rvbar;
343        break;
344      default:
345        panic("Invalid highest implemented exception level");
346        break;
347    }
348
349    // Initialize rest of CPSR
350    cpsr.daif = 0xf;  // Mask all interrupts
351    cpsr.ss = 0;
352    cpsr.il = 0;
353    miscRegs[MISCREG_CPSR] = cpsr;
354    updateRegMap(cpsr);
355
356    // Initialize other control registers
357    miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
358    if (haveSecurity) {
359        miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870;
360        miscRegs[MISCREG_SCR_EL3]   = 0x00000030;  // RES1 fields
361    // @todo: uncomment this to enable Virtualization
362    // } else if (haveVirtualization) {
363    //     miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
364    } else {
365        miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870;
366        // Always non-secure
367        miscRegs[MISCREG_SCR_EL3] = 1;
368    }
369
370    // Initialize configurable id registers
371    miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
372    miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
373    miscRegs[MISCREG_ID_AA64DFR0_EL1] =
374        (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
375        (p->pmu ?             0x0000000000000100ULL : 0); // Enable PMUv3
376
377    miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
378    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
379    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
380    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
381    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
382    miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1;
383    miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1;
384
385    miscRegs[MISCREG_ID_DFR0_EL1] =
386        (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
387
388    miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
389
390    // Enforce consistency with system-level settings...
391
392    // EL3
393    // (no AArch32/64 interprocessing support for now)
394    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
395        miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
396        haveSecurity ? 0x1 : 0x0);
397    // EL2
398    // (no AArch32/64 interprocessing support for now)
399    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
400        miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
401        haveVirtualization ? 0x1 : 0x0);
402    // Large ASID support
403    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
404        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
405        haveLargeAsid64 ? 0x2 : 0x0);
406    // Physical address size
407    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
408        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
409        encodePhysAddrRange64(physAddrRange64));
410}
411
412MiscReg
413ISA::readMiscRegNoEffect(int misc_reg) const
414{
415    assert(misc_reg < NumMiscRegs);
416
417    int flat_idx = flattenMiscIndex(misc_reg);  // Note: indexes of AArch64
418                                                // registers are left unchanged
419    MiscReg val;
420
421    if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR
422            || flat_idx == MISCREG_SCTLR_EL1) {
423        if (flat_idx == MISCREG_SPSR)
424            flat_idx = flattenMiscIndex(MISCREG_SPSR);
425        if (flat_idx == MISCREG_SCTLR_EL1)
426            flat_idx = flattenMiscIndex(MISCREG_SCTLR);
427        val = miscRegs[flat_idx];
428    } else
429        if (lookUpMiscReg[flat_idx].upper > 0)
430            val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32))
431                    | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32));
432        else
433            val = miscRegs[lookUpMiscReg[flat_idx].lower];
434
435    return val;
436}
437
438
439MiscReg
440ISA::readMiscReg(int misc_reg, ThreadContext *tc)
441{
442    CPSR cpsr = 0;
443    PCState pc = 0;
444    SCR scr = 0;
445
446    if (misc_reg == MISCREG_CPSR) {
447        cpsr = miscRegs[misc_reg];
448        pc = tc->pcState();
449        cpsr.j = pc.jazelle() ? 1 : 0;
450        cpsr.t = pc.thumb() ? 1 : 0;
451        return cpsr;
452    }
453
454#ifndef NDEBUG
455    if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
456        if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
457            warn("Unimplemented system register %s read.\n",
458                 miscRegName[misc_reg]);
459        else
460            panic("Unimplemented system register %s read.\n",
461                  miscRegName[misc_reg]);
462    }
463#endif
464
465    switch (unflattenMiscReg(misc_reg)) {
466      case MISCREG_HCR:
467        {
468            if (!haveVirtualization)
469                return 0;
470            else
471                return readMiscRegNoEffect(MISCREG_HCR);
472        }
473      case MISCREG_CPACR:
474        {
475            const uint32_t ones = (uint32_t)(-1);
476            CPACR cpacrMask = 0;
477            // Only cp10, cp11, and ase are implemented, nothing else should
478            // be readable? (straight copy from the write code)
479            cpacrMask.cp10 = ones;
480            cpacrMask.cp11 = ones;
481            cpacrMask.asedis = ones;
482
483            // Security Extensions may limit the readability of CPACR
484            if (haveSecurity) {
485                scr = readMiscRegNoEffect(MISCREG_SCR);
486                cpsr = readMiscRegNoEffect(MISCREG_CPSR);
487                if (scr.ns && (cpsr.mode != MODE_MON)) {
488                    NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
489                    // NB: Skipping the full loop, here
490                    if (!nsacr.cp10) cpacrMask.cp10 = 0;
491                    if (!nsacr.cp11) cpacrMask.cp11 = 0;
492                }
493            }
494            MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
495            val &= cpacrMask;
496            DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
497                    miscRegName[misc_reg], val);
498            return val;
499        }
500      case MISCREG_MPIDR:
501        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
502        scr  = readMiscRegNoEffect(MISCREG_SCR);
503        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
504            return getMPIDR(system, tc);
505        } else {
506            return readMiscReg(MISCREG_VMPIDR, tc);
507        }
508            break;
509      case MISCREG_MPIDR_EL1:
510        // @todo in the absence of v8 virtualization support just return MPIDR_EL1
511        return getMPIDR(system, tc) & 0xffffffff;
512      case MISCREG_VMPIDR:
513        // top bit defined as RES1
514        return readMiscRegNoEffect(misc_reg) | 0x80000000;
515      case MISCREG_ID_AFR0: // not implemented, so alias MIDR
516      case MISCREG_REVIDR:  // not implemented, so alias MIDR
517      case MISCREG_MIDR:
518        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
519        scr  = readMiscRegNoEffect(MISCREG_SCR);
520        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
521            return readMiscRegNoEffect(misc_reg);
522        } else {
523            return readMiscRegNoEffect(MISCREG_VPIDR);
524        }
525        break;
526      case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
527      case MISCREG_JMCR:  // Jazelle trivial implementation, RAZ/WI
528      case MISCREG_JIDR:  // Jazelle trivial implementation, RAZ/WI
529      case MISCREG_AIDR:  // AUX ID set to 0
530      case MISCREG_TCMTR: // No TCM's
531        return 0;
532
533      case MISCREG_CLIDR:
534        warn_once("The clidr register always reports 0 caches.\n");
535        warn_once("clidr LoUIS field of 0b001 to match current "
536                  "ARM implementations.\n");
537        return 0x00200000;
538      case MISCREG_CCSIDR:
539        warn_once("The ccsidr register isn't implemented and "
540                "always reads as 0.\n");
541        break;
542      case MISCREG_CTR:
543        {
544            //all caches have the same line size in gem5
545            //4 byte words in ARM
546            unsigned lineSizeWords =
547                tc->getSystemPtr()->cacheLineSize() / 4;
548            unsigned log2LineSizeWords = 0;
549
550            while (lineSizeWords >>= 1) {
551                ++log2LineSizeWords;
552            }
553
554            CTR ctr = 0;
555            //log2 of minimun i-cache line size (words)
556            ctr.iCacheLineSize = log2LineSizeWords;
557            //b11 - gem5 uses pipt
558            ctr.l1IndexPolicy = 0x3;
559            //log2 of minimum d-cache line size (words)
560            ctr.dCacheLineSize = log2LineSizeWords;
561            //log2 of max reservation size (words)
562            ctr.erg = log2LineSizeWords;
563            //log2 of max writeback size (words)
564            ctr.cwg = log2LineSizeWords;
565            //b100 - gem5 format is ARMv7
566            ctr.format = 0x4;
567
568            return ctr;
569        }
570      case MISCREG_ACTLR:
571        warn("Not doing anything for miscreg ACTLR\n");
572        break;
573
574      case MISCREG_PMXEVTYPER_PMCCFILTR:
575      case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
576      case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
577      case MISCREG_PMCR ... MISCREG_PMOVSSET:
578        return pmu->readMiscReg(misc_reg);
579
580      case MISCREG_CPSR_Q:
581        panic("shouldn't be reading this register seperately\n");
582      case MISCREG_FPSCR_QC:
583        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
584      case MISCREG_FPSCR_EXC:
585        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
586      case MISCREG_FPSR:
587        {
588            const uint32_t ones = (uint32_t)(-1);
589            FPSCR fpscrMask = 0;
590            fpscrMask.ioc = ones;
591            fpscrMask.dzc = ones;
592            fpscrMask.ofc = ones;
593            fpscrMask.ufc = ones;
594            fpscrMask.ixc = ones;
595            fpscrMask.idc = ones;
596            fpscrMask.qc = ones;
597            fpscrMask.v = ones;
598            fpscrMask.c = ones;
599            fpscrMask.z = ones;
600            fpscrMask.n = ones;
601            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
602        }
603      case MISCREG_FPCR:
604        {
605            const uint32_t ones = (uint32_t)(-1);
606            FPSCR fpscrMask  = 0;
607            fpscrMask.ioe = ones;
608            fpscrMask.dze = ones;
609            fpscrMask.ofe = ones;
610            fpscrMask.ufe = ones;
611            fpscrMask.ixe = ones;
612            fpscrMask.ide = ones;
613            fpscrMask.len    = ones;
614            fpscrMask.stride = ones;
615            fpscrMask.rMode  = ones;
616            fpscrMask.fz     = ones;
617            fpscrMask.dn     = ones;
618            fpscrMask.ahp    = ones;
619            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
620        }
621      case MISCREG_NZCV:
622        {
623            CPSR cpsr = 0;
624            cpsr.nz   = tc->readCCReg(CCREG_NZ);
625            cpsr.c    = tc->readCCReg(CCREG_C);
626            cpsr.v    = tc->readCCReg(CCREG_V);
627            return cpsr;
628        }
629      case MISCREG_DAIF:
630        {
631            CPSR cpsr = 0;
632            cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
633            return cpsr;
634        }
635      case MISCREG_SP_EL0:
636        {
637            return tc->readIntReg(INTREG_SP0);
638        }
639      case MISCREG_SP_EL1:
640        {
641            return tc->readIntReg(INTREG_SP1);
642        }
643      case MISCREG_SP_EL2:
644        {
645            return tc->readIntReg(INTREG_SP2);
646        }
647      case MISCREG_SPSEL:
648        {
649            return miscRegs[MISCREG_CPSR] & 0x1;
650        }
651      case MISCREG_CURRENTEL:
652        {
653            return miscRegs[MISCREG_CPSR] & 0xc;
654        }
655      case MISCREG_L2CTLR:
656        {
657            // mostly unimplemented, just set NumCPUs field from sim and return
658            L2CTLR l2ctlr = 0;
659            // b00:1CPU to b11:4CPUs
660            l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
661            return l2ctlr;
662        }
663      case MISCREG_DBGDIDR:
664        /* For now just implement the version number.
665         * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
666         */
667        return 0x5 << 16;
668      case MISCREG_DBGDSCRint:
669        return 0;
670      case MISCREG_ISR:
671        return tc->getCpuPtr()->getInterruptController()->getISR(
672            readMiscRegNoEffect(MISCREG_HCR),
673            readMiscRegNoEffect(MISCREG_CPSR),
674            readMiscRegNoEffect(MISCREG_SCR));
675      case MISCREG_ISR_EL1:
676        return tc->getCpuPtr()->getInterruptController()->getISR(
677            readMiscRegNoEffect(MISCREG_HCR_EL2),
678            readMiscRegNoEffect(MISCREG_CPSR),
679            readMiscRegNoEffect(MISCREG_SCR_EL3));
680      case MISCREG_DCZID_EL0:
681        return 0x04;  // DC ZVA clear 64-byte chunks
682      case MISCREG_HCPTR:
683        {
684            MiscReg val = readMiscRegNoEffect(misc_reg);
685            // The trap bit associated with CP14 is defined as RAZ
686            val &= ~(1 << 14);
687            // If a CP bit in NSACR is 0 then the corresponding bit in
688            // HCPTR is RAO/WI
689            bool secure_lookup = haveSecurity &&
690                inSecureState(readMiscRegNoEffect(MISCREG_SCR),
691                              readMiscRegNoEffect(MISCREG_CPSR));
692            if (!secure_lookup) {
693                MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
694                val |= (mask ^ 0x7FFF) & 0xBFFF;
695            }
696            // Set the bits for unimplemented coprocessors to RAO/WI
697            val |= 0x33FF;
698            return (val);
699        }
700      case MISCREG_HDFAR: // alias for secure DFAR
701        return readMiscRegNoEffect(MISCREG_DFAR_S);
702      case MISCREG_HIFAR: // alias for secure IFAR
703        return readMiscRegNoEffect(MISCREG_IFAR_S);
704      case MISCREG_HVBAR: // bottom bits reserved
705        return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
706      case MISCREG_SCTLR: // Some bits hardwired
707        // The FI field (bit 21) is common between S/NS versions of the register
708        return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21))  |
709               (readMiscRegNoEffect(misc_reg)        & 0x72DD39FF) | 0x00C00818; // V8 SCTLR
710      case MISCREG_SCTLR_EL1:
711        // The FI field (bit 21) is common between S/NS versions of the register
712        return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21))  |
713               (readMiscRegNoEffect(misc_reg)        & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1
714      case MISCREG_SCTLR_EL3:
715        // The FI field (bit 21) is common between S/NS versions of the register
716        return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21))  |
717               (readMiscRegNoEffect(misc_reg)        & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3
718      case MISCREG_HSCTLR: // FI comes from SCTLR
719        {
720            uint32_t mask = 1 << 27;
721            return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) |
722                (readMiscRegNoEffect(MISCREG_SCTLR)  &  mask);
723        }
724      case MISCREG_SCR:
725        {
726            CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
727            if (cpsr.width) {
728                return readMiscRegNoEffect(MISCREG_SCR);
729            } else {
730                return readMiscRegNoEffect(MISCREG_SCR_EL3);
731            }
732        }
733      // Generic Timer registers
734      case MISCREG_CNTFRQ:
735      case MISCREG_CNTFRQ_EL0:
736        inform_once("Read CNTFREQ_EL0 frequency\n");
737        return getSystemCounter(tc)->freq();
738      case MISCREG_CNTPCT:
739      case MISCREG_CNTPCT_EL0:
740        return getSystemCounter(tc)->value();
741      case MISCREG_CNTVCT:
742        return getSystemCounter(tc)->value();
743      case MISCREG_CNTVCT_EL0:
744        return getSystemCounter(tc)->value();
745      case MISCREG_CNTP_CVAL:
746      case MISCREG_CNTP_CVAL_EL0:
747        return getArchTimer(tc, tc->cpuId())->compareValue();
748      case MISCREG_CNTP_TVAL:
749      case MISCREG_CNTP_TVAL_EL0:
750        return getArchTimer(tc, tc->cpuId())->timerValue();
751      case MISCREG_CNTP_CTL:
752      case MISCREG_CNTP_CTL_EL0:
753        return getArchTimer(tc, tc->cpuId())->control();
754      // PL1 phys. timer, secure
755      //   AArch64
756      // case MISCREG_CNTPS_CVAL_EL1:
757      // case MISCREG_CNTPS_TVAL_EL1:
758      // case MISCREG_CNTPS_CTL_EL1:
759      // PL2 phys. timer, non-secure
760      //   AArch32
761      // case MISCREG_CNTHCTL:
762      // case MISCREG_CNTHP_CVAL:
763      // case MISCREG_CNTHP_TVAL:
764      // case MISCREG_CNTHP_CTL:
765      //   AArch64
766      // case MISCREG_CNTHCTL_EL2:
767      // case MISCREG_CNTHP_CVAL_EL2:
768      // case MISCREG_CNTHP_TVAL_EL2:
769      // case MISCREG_CNTHP_CTL_EL2:
770      // Virtual timer
771      //   AArch32
772      // case MISCREG_CNTV_CVAL:
773      // case MISCREG_CNTV_TVAL:
774      // case MISCREG_CNTV_CTL:
775      //   AArch64
776      // case MISCREG_CNTV_CVAL_EL2:
777      // case MISCREG_CNTV_TVAL_EL2:
778      // case MISCREG_CNTV_CTL_EL2:
779      default:
780        break;
781
782    }
783    return readMiscRegNoEffect(misc_reg);
784}
785
786void
787ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
788{
789    assert(misc_reg < NumMiscRegs);
790
791    int flat_idx = flattenMiscIndex(misc_reg);  // Note: indexes of AArch64
792                                                // registers are left unchanged
793
794    int flat_idx2 = lookUpMiscReg[flat_idx].upper;
795
796    if (flat_idx2 > 0) {
797        miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0);
798        miscRegs[flat_idx2] = bits(val, 63, 32);
799        DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
800                misc_reg, flat_idx, flat_idx2, val);
801    } else {
802        if (flat_idx == MISCREG_SPSR)
803            flat_idx = flattenMiscIndex(MISCREG_SPSR);
804        else if (flat_idx == MISCREG_SCTLR_EL1)
805            flat_idx = flattenMiscIndex(MISCREG_SCTLR);
806        else
807            flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ?
808                       lookUpMiscReg[flat_idx].lower : flat_idx;
809        miscRegs[flat_idx] = val;
810        DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
811                misc_reg, flat_idx, val);
812    }
813}
814
815void
816ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
817{
818
819    MiscReg newVal = val;
820    int x;
821    bool secure_lookup;
822    bool hyp;
823    System *sys;
824    ThreadContext *oc;
825    uint8_t target_el;
826    uint16_t asid;
827    SCR scr;
828
829    if (misc_reg == MISCREG_CPSR) {
830        updateRegMap(val);
831
832
833        CPSR old_cpsr = miscRegs[MISCREG_CPSR];
834        int old_mode = old_cpsr.mode;
835        CPSR cpsr = val;
836        if (old_mode != cpsr.mode) {
837            tc->getITBPtr()->invalidateMiscReg();
838            tc->getDTBPtr()->invalidateMiscReg();
839        }
840
841        DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
842                miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
843        PCState pc = tc->pcState();
844        pc.nextThumb(cpsr.t);
845        pc.nextJazelle(cpsr.j);
846
847        // Follow slightly different semantics if a CheckerCPU object
848        // is connected
849        CheckerCPU *checker = tc->getCheckerCpuPtr();
850        if (checker) {
851            tc->pcStateNoRecord(pc);
852        } else {
853            tc->pcState(pc);
854        }
855    } else {
856#ifndef NDEBUG
857        if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
858            if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
859                warn("Unimplemented system register %s write with %#x.\n",
860                    miscRegName[misc_reg], val);
861            else
862                panic("Unimplemented system register %s write with %#x.\n",
863                    miscRegName[misc_reg], val);
864        }
865#endif
866        switch (unflattenMiscReg(misc_reg)) {
867          case MISCREG_CPACR:
868            {
869
870                const uint32_t ones = (uint32_t)(-1);
871                CPACR cpacrMask = 0;
872                // Only cp10, cp11, and ase are implemented, nothing else should
873                // be writable
874                cpacrMask.cp10 = ones;
875                cpacrMask.cp11 = ones;
876                cpacrMask.asedis = ones;
877
878                // Security Extensions may limit the writability of CPACR
879                if (haveSecurity) {
880                    scr = readMiscRegNoEffect(MISCREG_SCR);
881                    CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
882                    if (scr.ns && (cpsr.mode != MODE_MON)) {
883                        NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
884                        // NB: Skipping the full loop, here
885                        if (!nsacr.cp10) cpacrMask.cp10 = 0;
886                        if (!nsacr.cp11) cpacrMask.cp11 = 0;
887                    }
888                }
889
890                MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
891                newVal &= cpacrMask;
892                newVal |= old_val & ~cpacrMask;
893                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
894                        miscRegName[misc_reg], newVal);
895            }
896            break;
897          case MISCREG_CPACR_EL1:
898            {
899                const uint32_t ones = (uint32_t)(-1);
900                CPACR cpacrMask = 0;
901                cpacrMask.tta = ones;
902                cpacrMask.fpen = ones;
903                newVal &= cpacrMask;
904                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
905                        miscRegName[misc_reg], newVal);
906            }
907            break;
908          case MISCREG_CPTR_EL2:
909            {
910                const uint32_t ones = (uint32_t)(-1);
911                CPTR cptrMask = 0;
912                cptrMask.tcpac = ones;
913                cptrMask.tta = ones;
914                cptrMask.tfp = ones;
915                newVal &= cptrMask;
916                cptrMask = 0;
917                cptrMask.res1_13_12_el2 = ones;
918                cptrMask.res1_9_0_el2 = ones;
919                newVal |= cptrMask;
920                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
921                        miscRegName[misc_reg], newVal);
922            }
923            break;
924          case MISCREG_CPTR_EL3:
925            {
926                const uint32_t ones = (uint32_t)(-1);
927                CPTR cptrMask = 0;
928                cptrMask.tcpac = ones;
929                cptrMask.tta = ones;
930                cptrMask.tfp = ones;
931                newVal &= cptrMask;
932                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
933                        miscRegName[misc_reg], newVal);
934            }
935            break;
936          case MISCREG_CSSELR:
937            warn_once("The csselr register isn't implemented.\n");
938            return;
939
940          case MISCREG_DC_ZVA_Xt:
941            warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
942            return;
943
944          case MISCREG_FPSCR:
945            {
946                const uint32_t ones = (uint32_t)(-1);
947                FPSCR fpscrMask = 0;
948                fpscrMask.ioc = ones;
949                fpscrMask.dzc = ones;
950                fpscrMask.ofc = ones;
951                fpscrMask.ufc = ones;
952                fpscrMask.ixc = ones;
953                fpscrMask.idc = ones;
954                fpscrMask.ioe = ones;
955                fpscrMask.dze = ones;
956                fpscrMask.ofe = ones;
957                fpscrMask.ufe = ones;
958                fpscrMask.ixe = ones;
959                fpscrMask.ide = ones;
960                fpscrMask.len = ones;
961                fpscrMask.stride = ones;
962                fpscrMask.rMode = ones;
963                fpscrMask.fz = ones;
964                fpscrMask.dn = ones;
965                fpscrMask.ahp = ones;
966                fpscrMask.qc = ones;
967                fpscrMask.v = ones;
968                fpscrMask.c = ones;
969                fpscrMask.z = ones;
970                fpscrMask.n = ones;
971                newVal = (newVal & (uint32_t)fpscrMask) |
972                         (readMiscRegNoEffect(MISCREG_FPSCR) &
973                          ~(uint32_t)fpscrMask);
974                tc->getDecoderPtr()->setContext(newVal);
975            }
976            break;
977          case MISCREG_FPSR:
978            {
979                const uint32_t ones = (uint32_t)(-1);
980                FPSCR fpscrMask = 0;
981                fpscrMask.ioc = ones;
982                fpscrMask.dzc = ones;
983                fpscrMask.ofc = ones;
984                fpscrMask.ufc = ones;
985                fpscrMask.ixc = ones;
986                fpscrMask.idc = ones;
987                fpscrMask.qc = ones;
988                fpscrMask.v = ones;
989                fpscrMask.c = ones;
990                fpscrMask.z = ones;
991                fpscrMask.n = ones;
992                newVal = (newVal & (uint32_t)fpscrMask) |
993                         (readMiscRegNoEffect(MISCREG_FPSCR) &
994                          ~(uint32_t)fpscrMask);
995                misc_reg = MISCREG_FPSCR;
996            }
997            break;
998          case MISCREG_FPCR:
999            {
1000                const uint32_t ones = (uint32_t)(-1);
1001                FPSCR fpscrMask  = 0;
1002                fpscrMask.ioe = ones;
1003                fpscrMask.dze = ones;
1004                fpscrMask.ofe = ones;
1005                fpscrMask.ufe = ones;
1006                fpscrMask.ixe = ones;
1007                fpscrMask.ide = ones;
1008                fpscrMask.len    = ones;
1009                fpscrMask.stride = ones;
1010                fpscrMask.rMode  = ones;
1011                fpscrMask.fz     = ones;
1012                fpscrMask.dn     = ones;
1013                fpscrMask.ahp    = ones;
1014                newVal = (newVal & (uint32_t)fpscrMask) |
1015                         (readMiscRegNoEffect(MISCREG_FPSCR) &
1016                          ~(uint32_t)fpscrMask);
1017                misc_reg = MISCREG_FPSCR;
1018            }
1019            break;
1020          case MISCREG_CPSR_Q:
1021            {
1022                assert(!(newVal & ~CpsrMaskQ));
1023                newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1024                misc_reg = MISCREG_CPSR;
1025            }
1026            break;
1027          case MISCREG_FPSCR_QC:
1028            {
1029                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1030                         (newVal & FpscrQcMask);
1031                misc_reg = MISCREG_FPSCR;
1032            }
1033            break;
1034          case MISCREG_FPSCR_EXC:
1035            {
1036                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1037                         (newVal & FpscrExcMask);
1038                misc_reg = MISCREG_FPSCR;
1039            }
1040            break;
1041          case MISCREG_FPEXC:
1042            {
1043                // vfpv3 architecture, section B.6.1 of DDI04068
1044                // bit 29 - valid only if fpexc[31] is 0
1045                const uint32_t fpexcMask = 0x60000000;
1046                newVal = (newVal & fpexcMask) |
1047                         (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1048            }
1049            break;
1050          case MISCREG_HCR:
1051            {
1052                if (!haveVirtualization)
1053                    return;
1054            }
1055            break;
1056          case MISCREG_IFSR:
1057            {
1058                // ARM ARM (ARM DDI 0406C.b) B4.1.96
1059                const uint32_t ifsrMask =
1060                    mask(31, 13) | mask(11, 11) | mask(8, 6);
1061                newVal = newVal & ~ifsrMask;
1062            }
1063            break;
1064          case MISCREG_DFSR:
1065            {
1066                // ARM ARM (ARM DDI 0406C.b) B4.1.52
1067                const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1068                newVal = newVal & ~dfsrMask;
1069            }
1070            break;
1071          case MISCREG_AMAIR0:
1072          case MISCREG_AMAIR1:
1073            {
1074                // ARM ARM (ARM DDI 0406C.b) B4.1.5
1075                // Valid only with LPAE
1076                if (!haveLPAE)
1077                    return;
1078                DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1079            }
1080            break;
1081          case MISCREG_SCR:
1082            tc->getITBPtr()->invalidateMiscReg();
1083            tc->getDTBPtr()->invalidateMiscReg();
1084            break;
1085          case MISCREG_SCTLR:
1086            {
1087                DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1088                MiscRegIndex sctlr_idx;
1089                scr = readMiscRegNoEffect(MISCREG_SCR);
1090                if (haveSecurity && !scr.ns) {
1091                    sctlr_idx = MISCREG_SCTLR_S;
1092                } else {
1093                    sctlr_idx = MISCREG_SCTLR_NS;
1094                    // The FI field (bit 21) is common between S/NS versions
1095                    // of the register, we store this in the secure copy of
1096                    // the reg
1097                    miscRegs[MISCREG_SCTLR_S] &=         ~(1 << 21);
1098                    miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21);
1099                }
1100                SCTLR sctlr = miscRegs[sctlr_idx];
1101                SCTLR new_sctlr = newVal;
1102                new_sctlr.nmfi =  ((bool)sctlr.nmfi) && !haveVirtualization;
1103                miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1104                tc->getITBPtr()->invalidateMiscReg();
1105                tc->getDTBPtr()->invalidateMiscReg();
1106
1107                if (new_sctlr.c)
1108                    updateBootUncacheable(sctlr_idx, tc);
1109                return;
1110            }
1111          case MISCREG_MIDR:
1112          case MISCREG_ID_PFR0:
1113          case MISCREG_ID_PFR1:
1114          case MISCREG_ID_DFR0:
1115          case MISCREG_ID_MMFR0:
1116          case MISCREG_ID_MMFR1:
1117          case MISCREG_ID_MMFR2:
1118          case MISCREG_ID_MMFR3:
1119          case MISCREG_ID_ISAR0:
1120          case MISCREG_ID_ISAR1:
1121          case MISCREG_ID_ISAR2:
1122          case MISCREG_ID_ISAR3:
1123          case MISCREG_ID_ISAR4:
1124          case MISCREG_ID_ISAR5:
1125
1126          case MISCREG_MPIDR:
1127          case MISCREG_FPSID:
1128          case MISCREG_TLBTR:
1129          case MISCREG_MVFR0:
1130          case MISCREG_MVFR1:
1131
1132          case MISCREG_ID_AA64AFR0_EL1:
1133          case MISCREG_ID_AA64AFR1_EL1:
1134          case MISCREG_ID_AA64DFR0_EL1:
1135          case MISCREG_ID_AA64DFR1_EL1:
1136          case MISCREG_ID_AA64ISAR0_EL1:
1137          case MISCREG_ID_AA64ISAR1_EL1:
1138          case MISCREG_ID_AA64MMFR0_EL1:
1139          case MISCREG_ID_AA64MMFR1_EL1:
1140          case MISCREG_ID_AA64PFR0_EL1:
1141          case MISCREG_ID_AA64PFR1_EL1:
1142            // ID registers are constants.
1143            return;
1144
1145          // TLBI all entries, EL0&1 inner sharable (ignored)
1146          case MISCREG_TLBIALLIS:
1147          case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1148            assert32(tc);
1149            target_el = 1; // el 0 and 1 are handled together
1150            scr = readMiscReg(MISCREG_SCR, tc);
1151            secure_lookup = haveSecurity && !scr.ns;
1152            sys = tc->getSystemPtr();
1153            for (x = 0; x < sys->numContexts(); x++) {
1154                oc = sys->getThreadContext(x);
1155                assert(oc->getITBPtr() && oc->getDTBPtr());
1156                oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1157                oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1158
1159                // If CheckerCPU is connected, need to notify it of a flush
1160                CheckerCPU *checker = oc->getCheckerCpuPtr();
1161                if (checker) {
1162                    checker->getITBPtr()->flushAllSecurity(secure_lookup,
1163                                                           target_el);
1164                    checker->getDTBPtr()->flushAllSecurity(secure_lookup,
1165                                                           target_el);
1166                }
1167            }
1168            return;
1169          // TLBI all entries, EL0&1, instruction side
1170          case MISCREG_ITLBIALL:
1171            assert32(tc);
1172            target_el = 1; // el 0 and 1 are handled together
1173            scr = readMiscReg(MISCREG_SCR, tc);
1174            secure_lookup = haveSecurity && !scr.ns;
1175            tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1176            return;
1177          // TLBI all entries, EL0&1, data side
1178          case MISCREG_DTLBIALL:
1179            assert32(tc);
1180            target_el = 1; // el 0 and 1 are handled together
1181            scr = readMiscReg(MISCREG_SCR, tc);
1182            secure_lookup = haveSecurity && !scr.ns;
1183            tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1184            return;
1185          // TLBI based on VA, EL0&1 inner sharable (ignored)
1186          case MISCREG_TLBIMVAIS:
1187          case MISCREG_TLBIMVA:
1188            assert32(tc);
1189            target_el = 1; // el 0 and 1 are handled together
1190            scr = readMiscReg(MISCREG_SCR, tc);
1191            secure_lookup = haveSecurity && !scr.ns;
1192            sys = tc->getSystemPtr();
1193            for (x = 0; x < sys->numContexts(); x++) {
1194                oc = sys->getThreadContext(x);
1195                assert(oc->getITBPtr() && oc->getDTBPtr());
1196                oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1197                                              bits(newVal, 7,0),
1198                                              secure_lookup, target_el);
1199                oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1200                                              bits(newVal, 7,0),
1201                                              secure_lookup, target_el);
1202
1203                CheckerCPU *checker = oc->getCheckerCpuPtr();
1204                if (checker) {
1205                    checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1206                        bits(newVal, 7,0), secure_lookup, target_el);
1207                    checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1208                        bits(newVal, 7,0), secure_lookup, target_el);
1209                }
1210            }
1211            return;
1212          // TLBI by ASID, EL0&1, inner sharable
1213          case MISCREG_TLBIASIDIS:
1214          case MISCREG_TLBIASID:
1215            assert32(tc);
1216            target_el = 1; // el 0 and 1 are handled together
1217            scr = readMiscReg(MISCREG_SCR, tc);
1218            secure_lookup = haveSecurity && !scr.ns;
1219            sys = tc->getSystemPtr();
1220            for (x = 0; x < sys->numContexts(); x++) {
1221                oc = sys->getThreadContext(x);
1222                assert(oc->getITBPtr() && oc->getDTBPtr());
1223                oc->getITBPtr()->flushAsid(bits(newVal, 7,0),
1224                    secure_lookup, target_el);
1225                oc->getDTBPtr()->flushAsid(bits(newVal, 7,0),
1226                    secure_lookup, target_el);
1227                CheckerCPU *checker = oc->getCheckerCpuPtr();
1228                if (checker) {
1229                    checker->getITBPtr()->flushAsid(bits(newVal, 7,0),
1230                        secure_lookup, target_el);
1231                    checker->getDTBPtr()->flushAsid(bits(newVal, 7,0),
1232                        secure_lookup, target_el);
1233                }
1234            }
1235            return;
1236          // TLBI by address, EL0&1, inner sharable (ignored)
1237          case MISCREG_TLBIMVAAIS:
1238          case MISCREG_TLBIMVAA:
1239            assert32(tc);
1240            target_el = 1; // el 0 and 1 are handled together
1241            scr = readMiscReg(MISCREG_SCR, tc);
1242            secure_lookup = haveSecurity && !scr.ns;
1243            hyp = 0;
1244            tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1245            return;
1246          // TLBI by address, EL2, hypervisor mode
1247          case MISCREG_TLBIMVAH:
1248          case MISCREG_TLBIMVAHIS:
1249            assert32(tc);
1250            target_el = 1; // aarch32, use hyp bit
1251            scr = readMiscReg(MISCREG_SCR, tc);
1252            secure_lookup = haveSecurity && !scr.ns;
1253            hyp = 1;
1254            tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1255            return;
1256          // TLBI by address and asid, EL0&1, instruction side only
1257          case MISCREG_ITLBIMVA:
1258            assert32(tc);
1259            target_el = 1; // el 0 and 1 are handled together
1260            scr = readMiscReg(MISCREG_SCR, tc);
1261            secure_lookup = haveSecurity && !scr.ns;
1262            tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1263                bits(newVal, 7,0), secure_lookup, target_el);
1264            return;
1265          // TLBI by address and asid, EL0&1, data side only
1266          case MISCREG_DTLBIMVA:
1267            assert32(tc);
1268            target_el = 1; // el 0 and 1 are handled together
1269            scr = readMiscReg(MISCREG_SCR, tc);
1270            secure_lookup = haveSecurity && !scr.ns;
1271            tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1272                bits(newVal, 7,0), secure_lookup, target_el);
1273            return;
1274          // TLBI by ASID, EL0&1, instrution side only
1275          case MISCREG_ITLBIASID:
1276            assert32(tc);
1277            target_el = 1; // el 0 and 1 are handled together
1278            scr = readMiscReg(MISCREG_SCR, tc);
1279            secure_lookup = haveSecurity && !scr.ns;
1280            tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
1281                                       target_el);
1282            return;
1283          // TLBI by ASID EL0&1 data size only
1284          case MISCREG_DTLBIASID:
1285            assert32(tc);
1286            target_el = 1; // el 0 and 1 are handled together
1287            scr = readMiscReg(MISCREG_SCR, tc);
1288            secure_lookup = haveSecurity && !scr.ns;
1289            tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
1290                                       target_el);
1291            return;
1292          // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1293          case MISCREG_TLBIALLNSNH:
1294          case MISCREG_TLBIALLNSNHIS:
1295            assert32(tc);
1296            target_el = 1; // el 0 and 1 are handled together
1297            hyp = 0;
1298            tlbiALLN(tc, hyp, target_el);
1299            return;
1300          // TLBI all entries, EL2, hyp,
1301          case MISCREG_TLBIALLH:
1302          case MISCREG_TLBIALLHIS:
1303            assert32(tc);
1304            target_el = 1; // aarch32, use hyp bit
1305            hyp = 1;
1306            tlbiALLN(tc, hyp, target_el);
1307            return;
1308          // AArch64 TLBI: invalidate all entries EL3
1309          case MISCREG_TLBI_ALLE3IS:
1310          case MISCREG_TLBI_ALLE3:
1311            assert64(tc);
1312            target_el = 3;
1313            secure_lookup = true;
1314            tlbiALL(tc, secure_lookup, target_el);
1315            return;
1316          // @todo: uncomment this to enable Virtualization
1317          // case MISCREG_TLBI_ALLE2IS:
1318          // case MISCREG_TLBI_ALLE2:
1319          // TLBI all entries, EL0&1
1320          case MISCREG_TLBI_ALLE1IS:
1321          case MISCREG_TLBI_ALLE1:
1322          // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1323          case MISCREG_TLBI_VMALLE1IS:
1324          case MISCREG_TLBI_VMALLE1:
1325          // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1326          case MISCREG_TLBI_VMALLS12E1IS:
1327          case MISCREG_TLBI_VMALLS12E1:
1328            // @todo: handle VMID and stage 2 to enable Virtualization
1329            assert64(tc);
1330            target_el = 1; // el 0 and 1 are handled together
1331            scr = readMiscReg(MISCREG_SCR, tc);
1332            secure_lookup = haveSecurity && !scr.ns;
1333            tlbiALL(tc, secure_lookup, target_el);
1334            return;
1335          // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1336          // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1337          // from the last level of translation table walks
1338          // @todo: handle VMID to enable Virtualization
1339          // TLBI all entries, EL0&1
1340          case MISCREG_TLBI_VAE3IS_Xt:
1341          case MISCREG_TLBI_VAE3_Xt:
1342          // TLBI by VA, EL3  regime stage 1, last level walk
1343          case MISCREG_TLBI_VALE3IS_Xt:
1344          case MISCREG_TLBI_VALE3_Xt:
1345            assert64(tc);
1346            target_el = 3;
1347            asid = 0xbeef; // does not matter, tlbi is global
1348            secure_lookup = true;
1349            tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1350            return;
1351          // TLBI by VA, EL2
1352          case MISCREG_TLBI_VAE2IS_Xt:
1353          case MISCREG_TLBI_VAE2_Xt:
1354          // TLBI by VA, EL2, stage1 last level walk
1355          case MISCREG_TLBI_VALE2IS_Xt:
1356          case MISCREG_TLBI_VALE2_Xt:
1357            assert64(tc);
1358            target_el = 2;
1359            asid = 0xbeef; // does not matter, tlbi is global
1360            scr = readMiscReg(MISCREG_SCR, tc);
1361            secure_lookup = haveSecurity && !scr.ns;
1362            tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1363            return;
1364          // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1365          case MISCREG_TLBI_VAE1IS_Xt:
1366          case MISCREG_TLBI_VAE1_Xt:
1367          case MISCREG_TLBI_VALE1IS_Xt:
1368          case MISCREG_TLBI_VALE1_Xt:
1369            assert64(tc);
1370            asid = bits(newVal, 63, 48);
1371            target_el = 1; // el 0 and 1 are handled together
1372            scr = readMiscReg(MISCREG_SCR, tc);
1373            secure_lookup = haveSecurity && !scr.ns;
1374            tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1375            return;
1376          // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1377          // @todo: handle VMID to enable Virtualization
1378          case MISCREG_TLBI_ASIDE1IS_Xt:
1379          case MISCREG_TLBI_ASIDE1_Xt:
1380            assert64(tc);
1381            target_el = 1; // el 0 and 1 are handled together
1382            scr = readMiscReg(MISCREG_SCR, tc);
1383            secure_lookup = haveSecurity && !scr.ns;
1384            sys = tc->getSystemPtr();
1385            for (x = 0; x < sys->numContexts(); x++) {
1386                oc = sys->getThreadContext(x);
1387                assert(oc->getITBPtr() && oc->getDTBPtr());
1388                asid = bits(newVal, 63, 48);
1389                if (!haveLargeAsid64)
1390                    asid &= mask(8);
1391                oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el);
1392                oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el);
1393                CheckerCPU *checker = oc->getCheckerCpuPtr();
1394                if (checker) {
1395                    checker->getITBPtr()->flushAsid(asid,
1396                        secure_lookup, target_el);
1397                    checker->getDTBPtr()->flushAsid(asid,
1398                        secure_lookup, target_el);
1399                }
1400            }
1401            return;
1402          // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1403          // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1404          // entries from the last level of translation table walks
1405          // @todo: handle VMID to enable Virtualization
1406          case MISCREG_TLBI_VAAE1IS_Xt:
1407          case MISCREG_TLBI_VAAE1_Xt:
1408          case MISCREG_TLBI_VAALE1IS_Xt:
1409          case MISCREG_TLBI_VAALE1_Xt:
1410            assert64(tc);
1411            target_el = 1; // el 0 and 1 are handled together
1412            scr = readMiscReg(MISCREG_SCR, tc);
1413            secure_lookup = haveSecurity && !scr.ns;
1414            sys = tc->getSystemPtr();
1415            for (x = 0; x < sys->numContexts(); x++) {
1416                // @todo: extra controls on TLBI broadcast?
1417                oc = sys->getThreadContext(x);
1418                assert(oc->getITBPtr() && oc->getDTBPtr());
1419                Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1420                oc->getITBPtr()->flushMva(va,
1421                    secure_lookup, false, target_el);
1422                oc->getDTBPtr()->flushMva(va,
1423                    secure_lookup, false, target_el);
1424
1425                CheckerCPU *checker = oc->getCheckerCpuPtr();
1426                if (checker) {
1427                    checker->getITBPtr()->flushMva(va,
1428                        secure_lookup, false, target_el);
1429                    checker->getDTBPtr()->flushMva(va,
1430                        secure_lookup, false, target_el);
1431                }
1432            }
1433            return;
1434          // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1435          case MISCREG_TLBI_IPAS2LE1IS_Xt:
1436          case MISCREG_TLBI_IPAS2LE1_Xt:
1437          case MISCREG_TLBI_IPAS2E1IS_Xt:
1438          case MISCREG_TLBI_IPAS2E1_Xt:
1439            assert64(tc);
1440            // @todo: implement these as part of Virtualization
1441            warn("Not doing anything for write of miscreg ITLB_IPAS2\n");
1442            return;
1443          case MISCREG_ACTLR:
1444            warn("Not doing anything for write of miscreg ACTLR\n");
1445            break;
1446
1447          case MISCREG_PMXEVTYPER_PMCCFILTR:
1448          case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1449          case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1450          case MISCREG_PMCR ... MISCREG_PMOVSSET:
1451            pmu->setMiscReg(misc_reg, newVal);
1452            break;
1453
1454
1455          case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1456            {
1457                HSTR hstrMask = 0;
1458                hstrMask.tjdbx = 1;
1459                newVal &= ~((uint32_t) hstrMask);
1460                break;
1461            }
1462          case MISCREG_HCPTR:
1463            {
1464                // If a CP bit in NSACR is 0 then the corresponding bit in
1465                // HCPTR is RAO/WI. Same applies to NSASEDIS
1466                secure_lookup = haveSecurity &&
1467                    inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1468                                  readMiscRegNoEffect(MISCREG_CPSR));
1469                if (!secure_lookup) {
1470                    MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1471                    MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1472                    newVal = (newVal & ~mask) | (oldValue & mask);
1473                }
1474                break;
1475            }
1476          case MISCREG_HDFAR: // alias for secure DFAR
1477            misc_reg = MISCREG_DFAR_S;
1478            break;
1479          case MISCREG_HIFAR: // alias for secure IFAR
1480            misc_reg = MISCREG_IFAR_S;
1481            break;
1482          case MISCREG_ATS1CPR:
1483          case MISCREG_ATS1CPW:
1484          case MISCREG_ATS1CUR:
1485          case MISCREG_ATS1CUW:
1486          case MISCREG_ATS12NSOPR:
1487          case MISCREG_ATS12NSOPW:
1488          case MISCREG_ATS12NSOUR:
1489          case MISCREG_ATS12NSOUW:
1490          case MISCREG_ATS1HR:
1491          case MISCREG_ATS1HW:
1492            {
1493              unsigned flags = 0;
1494              BaseTLB::Mode mode = BaseTLB::Read;
1495              TLB::ArmTranslationType tranType = TLB::NormalTran;
1496              Fault fault;
1497              switch(misc_reg) {
1498                case MISCREG_ATS1CPR:
1499                  flags    = TLB::MustBeOne;
1500                  tranType = TLB::S1CTran;
1501                  mode     = BaseTLB::Read;
1502                  break;
1503                case MISCREG_ATS1CPW:
1504                  flags    = TLB::MustBeOne;
1505                  tranType = TLB::S1CTran;
1506                  mode     = BaseTLB::Write;
1507                  break;
1508                case MISCREG_ATS1CUR:
1509                  flags    = TLB::MustBeOne | TLB::UserMode;
1510                  tranType = TLB::S1CTran;
1511                  mode     = BaseTLB::Read;
1512                  break;
1513                case MISCREG_ATS1CUW:
1514                  flags    = TLB::MustBeOne | TLB::UserMode;
1515                  tranType = TLB::S1CTran;
1516                  mode     = BaseTLB::Write;
1517                  break;
1518                case MISCREG_ATS12NSOPR:
1519                  if (!haveSecurity)
1520                      panic("Security Extensions required for ATS12NSOPR");
1521                  flags    = TLB::MustBeOne;
1522                  tranType = TLB::S1S2NsTran;
1523                  mode     = BaseTLB::Read;
1524                  break;
1525                case MISCREG_ATS12NSOPW:
1526                  if (!haveSecurity)
1527                      panic("Security Extensions required for ATS12NSOPW");
1528                  flags    = TLB::MustBeOne;
1529                  tranType = TLB::S1S2NsTran;
1530                  mode     = BaseTLB::Write;
1531                  break;
1532                case MISCREG_ATS12NSOUR:
1533                  if (!haveSecurity)
1534                      panic("Security Extensions required for ATS12NSOUR");
1535                  flags    = TLB::MustBeOne | TLB::UserMode;
1536                  tranType = TLB::S1S2NsTran;
1537                  mode     = BaseTLB::Read;
1538                  break;
1539                case MISCREG_ATS12NSOUW:
1540                  if (!haveSecurity)
1541                      panic("Security Extensions required for ATS12NSOUW");
1542                  flags    = TLB::MustBeOne | TLB::UserMode;
1543                  tranType = TLB::S1S2NsTran;
1544                  mode     = BaseTLB::Write;
1545                  break;
1546                case MISCREG_ATS1HR: // only really useful from secure mode.
1547                  flags    = TLB::MustBeOne;
1548                  tranType = TLB::HypMode;
1549                  mode     = BaseTLB::Read;
1550                  break;
1551                case MISCREG_ATS1HW:
1552                  flags    = TLB::MustBeOne;
1553                  tranType = TLB::HypMode;
1554                  mode     = BaseTLB::Write;
1555                  break;
1556              }
1557              // If we're in timing mode then doing the translation in
1558              // functional mode then we're slightly distorting performance
1559              // results obtained from simulations. The translation should be
1560              // done in the same mode the core is running in. NOTE: This
1561              // can't be an atomic translation because that causes problems
1562              // with unexpected atomic snoop requests.
1563              warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1564              Request req(0, val, 1, flags,  Request::funcMasterId,
1565                          tc->pcState().pc(), tc->contextId(),
1566                          tc->threadId());
1567              fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType);
1568              TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1569              HCR   hcr   = readMiscRegNoEffect(MISCREG_HCR);
1570
1571              MiscReg newVal;
1572              if (fault == NoFault) {
1573                  Addr paddr = req.getPaddr();
1574                  if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1575                     ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1576                      newVal = (paddr & mask(39, 12)) |
1577                               (tc->getDTBPtr()->getAttr());
1578                  } else {
1579                      newVal = (paddr & 0xfffff000) |
1580                               (tc->getDTBPtr()->getAttr());
1581                  }
1582                  DPRINTF(MiscRegs,
1583                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1584                          val, newVal);
1585              } else {
1586                  ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1587                  // Set fault bit and FSR
1588                  FSR fsr = armFault->getFsr(tc);
1589
1590                  newVal = ((fsr >> 9) & 1) << 11;
1591                  if (newVal) {
1592                    // LPAE - rearange fault status
1593                    newVal |= ((fsr >>  0) & 0x3f) << 1;
1594                  } else {
1595                    // VMSA - rearange fault status
1596                    newVal |= ((fsr >>  0) & 0xf) << 1;
1597                    newVal |= ((fsr >> 10) & 0x1) << 5;
1598                    newVal |= ((fsr >> 12) & 0x1) << 6;
1599                  }
1600                  newVal |= 0x1; // F bit
1601                  newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1602                  newVal |= armFault->isStage2() ? 0x200 : 0;
1603                  DPRINTF(MiscRegs,
1604                          "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1605                          val, fsr, newVal);
1606              }
1607              setMiscRegNoEffect(MISCREG_PAR, newVal);
1608              return;
1609            }
1610          case MISCREG_TTBCR:
1611            {
1612                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1613                const uint32_t ones = (uint32_t)(-1);
1614                TTBCR ttbcrMask = 0;
1615                TTBCR ttbcrNew = newVal;
1616
1617                // ARM DDI 0406C.b, ARMv7-32
1618                ttbcrMask.n = ones; // T0SZ
1619                if (haveSecurity) {
1620                    ttbcrMask.pd0 = ones;
1621                    ttbcrMask.pd1 = ones;
1622                }
1623                ttbcrMask.epd0 = ones;
1624                ttbcrMask.irgn0 = ones;
1625                ttbcrMask.orgn0 = ones;
1626                ttbcrMask.sh0 = ones;
1627                ttbcrMask.ps = ones; // T1SZ
1628                ttbcrMask.a1 = ones;
1629                ttbcrMask.epd1 = ones;
1630                ttbcrMask.irgn1 = ones;
1631                ttbcrMask.orgn1 = ones;
1632                ttbcrMask.sh1 = ones;
1633                if (haveLPAE)
1634                    ttbcrMask.eae = ones;
1635
1636                if (haveLPAE && ttbcrNew.eae) {
1637                    newVal = newVal & ttbcrMask;
1638                } else {
1639                    newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1640                }
1641            }
1642          case MISCREG_TTBR0:
1643          case MISCREG_TTBR1:
1644            {
1645                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1646                if (haveLPAE) {
1647                    if (ttbcr.eae) {
1648                        // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1649                        // ARMv8 AArch32 bit 63-56 only
1650                        uint64_t ttbrMask = mask(63,56) | mask(47,40);
1651                        newVal = (newVal & (~ttbrMask));
1652                    }
1653                }
1654            }
1655          case MISCREG_SCTLR_EL1:
1656            {
1657                tc->getITBPtr()->invalidateMiscReg();
1658                tc->getDTBPtr()->invalidateMiscReg();
1659                SCTLR new_sctlr = newVal;
1660                setMiscRegNoEffect(misc_reg, newVal);
1661                if (new_sctlr.c)
1662                    updateBootUncacheable(misc_reg, tc);
1663                return;
1664            }
1665          case MISCREG_CONTEXTIDR:
1666          case MISCREG_PRRR:
1667          case MISCREG_NMRR:
1668          case MISCREG_MAIR0:
1669          case MISCREG_MAIR1:
1670          case MISCREG_DACR:
1671          case MISCREG_VTTBR:
1672          case MISCREG_SCR_EL3:
1673          case MISCREG_TCR_EL1:
1674          case MISCREG_TCR_EL2:
1675          case MISCREG_TCR_EL3:
1676          case MISCREG_SCTLR_EL2:
1677          case MISCREG_SCTLR_EL3:
1678          case MISCREG_TTBR0_EL1:
1679          case MISCREG_TTBR1_EL1:
1680          case MISCREG_TTBR0_EL2:
1681          case MISCREG_TTBR0_EL3:
1682            tc->getITBPtr()->invalidateMiscReg();
1683            tc->getDTBPtr()->invalidateMiscReg();
1684            break;
1685          case MISCREG_NZCV:
1686            {
1687                CPSR cpsr = val;
1688
1689                tc->setCCReg(CCREG_NZ, cpsr.nz);
1690                tc->setCCReg(CCREG_C,  cpsr.c);
1691                tc->setCCReg(CCREG_V,  cpsr.v);
1692            }
1693            break;
1694          case MISCREG_DAIF:
1695            {
1696                CPSR cpsr = miscRegs[MISCREG_CPSR];
1697                cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1698                newVal = cpsr;
1699                misc_reg = MISCREG_CPSR;
1700            }
1701            break;
1702          case MISCREG_SP_EL0:
1703            tc->setIntReg(INTREG_SP0, newVal);
1704            break;
1705          case MISCREG_SP_EL1:
1706            tc->setIntReg(INTREG_SP1, newVal);
1707            break;
1708          case MISCREG_SP_EL2:
1709            tc->setIntReg(INTREG_SP2, newVal);
1710            break;
1711          case MISCREG_SPSEL:
1712            {
1713                CPSR cpsr = miscRegs[MISCREG_CPSR];
1714                cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1715                newVal = cpsr;
1716                misc_reg = MISCREG_CPSR;
1717            }
1718            break;
1719          case MISCREG_CURRENTEL:
1720            {
1721                CPSR cpsr = miscRegs[MISCREG_CPSR];
1722                cpsr.el = (uint8_t) ((CPSR) newVal).el;
1723                newVal = cpsr;
1724                misc_reg = MISCREG_CPSR;
1725            }
1726            break;
1727          case MISCREG_AT_S1E1R_Xt:
1728          case MISCREG_AT_S1E1W_Xt:
1729          case MISCREG_AT_S1E0R_Xt:
1730          case MISCREG_AT_S1E0W_Xt:
1731          case MISCREG_AT_S1E2R_Xt:
1732          case MISCREG_AT_S1E2W_Xt:
1733          case MISCREG_AT_S12E1R_Xt:
1734          case MISCREG_AT_S12E1W_Xt:
1735          case MISCREG_AT_S12E0R_Xt:
1736          case MISCREG_AT_S12E0W_Xt:
1737          case MISCREG_AT_S1E3R_Xt:
1738          case MISCREG_AT_S1E3W_Xt:
1739            {
1740                RequestPtr req = new Request;
1741                unsigned flags = 0;
1742                BaseTLB::Mode mode = BaseTLB::Read;
1743                TLB::ArmTranslationType tranType = TLB::NormalTran;
1744                Fault fault;
1745                switch(misc_reg) {
1746                  case MISCREG_AT_S1E1R_Xt:
1747                    flags    = TLB::MustBeOne;
1748                    tranType = TLB::S1CTran;
1749                    mode     = BaseTLB::Read;
1750                    break;
1751                  case MISCREG_AT_S1E1W_Xt:
1752                    flags    = TLB::MustBeOne;
1753                    tranType = TLB::S1CTran;
1754                    mode     = BaseTLB::Write;
1755                    break;
1756                  case MISCREG_AT_S1E0R_Xt:
1757                    flags    = TLB::MustBeOne | TLB::UserMode;
1758                    tranType = TLB::S1CTran;
1759                    mode     = BaseTLB::Read;
1760                    break;
1761                  case MISCREG_AT_S1E0W_Xt:
1762                    flags    = TLB::MustBeOne | TLB::UserMode;
1763                    tranType = TLB::S1CTran;
1764                    mode     = BaseTLB::Write;
1765                    break;
1766                  case MISCREG_AT_S1E2R_Xt:
1767                    flags    = TLB::MustBeOne;
1768                    tranType = TLB::HypMode;
1769                    mode     = BaseTLB::Read;
1770                    break;
1771                  case MISCREG_AT_S1E2W_Xt:
1772                    flags    = TLB::MustBeOne;
1773                    tranType = TLB::HypMode;
1774                    mode     = BaseTLB::Write;
1775                    break;
1776                  case MISCREG_AT_S12E0R_Xt:
1777                    flags    = TLB::MustBeOne | TLB::UserMode;
1778                    tranType = TLB::S1S2NsTran;
1779                    mode     = BaseTLB::Read;
1780                    break;
1781                  case MISCREG_AT_S12E0W_Xt:
1782                    flags    = TLB::MustBeOne | TLB::UserMode;
1783                    tranType = TLB::S1S2NsTran;
1784                    mode     = BaseTLB::Write;
1785                    break;
1786                  case MISCREG_AT_S12E1R_Xt:
1787                    flags    = TLB::MustBeOne;
1788                    tranType = TLB::S1S2NsTran;
1789                    mode     = BaseTLB::Read;
1790                    break;
1791                  case MISCREG_AT_S12E1W_Xt:
1792                    flags    = TLB::MustBeOne;
1793                    tranType = TLB::S1S2NsTran;
1794                    mode     = BaseTLB::Write;
1795                    break;
1796                  case MISCREG_AT_S1E3R_Xt:
1797                    flags    = TLB::MustBeOne;
1798                    tranType = TLB::HypMode; // There is no TZ mode defined.
1799                    mode     = BaseTLB::Read;
1800                    break;
1801                  case MISCREG_AT_S1E3W_Xt:
1802                    flags    = TLB::MustBeOne;
1803                    tranType = TLB::HypMode; // There is no TZ mode defined.
1804                    mode     = BaseTLB::Write;
1805                    break;
1806                }
1807                // If we're in timing mode then doing the translation in
1808                // functional mode then we're slightly distorting performance
1809                // results obtained from simulations. The translation should be
1810                // done in the same mode the core is running in. NOTE: This
1811                // can't be an atomic translation because that causes problems
1812                // with unexpected atomic snoop requests.
1813                warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1814                req->setVirt(0, val, 1, flags,  Request::funcMasterId,
1815                               tc->pcState().pc());
1816                req->setThreadContext(tc->contextId(), tc->threadId());
1817                fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
1818                                                             tranType);
1819
1820                MiscReg newVal;
1821                if (fault == NoFault) {
1822                    Addr paddr = req->getPaddr();
1823                    uint64_t attr = tc->getDTBPtr()->getAttr();
1824                    uint64_t attr1 = attr >> 56;
1825                    if (!attr1 || attr1 ==0x44) {
1826                        attr |= 0x100;
1827                        attr &= ~ uint64_t(0x80);
1828                    }
1829                    newVal = (paddr & mask(47, 12)) | attr;
1830                    DPRINTF(MiscRegs,
1831                          "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1832                          val, newVal);
1833                } else {
1834                    ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1835                    // Set fault bit and FSR
1836                    FSR fsr = armFault->getFsr(tc);
1837
1838                    newVal = ((fsr >> 9) & 1) << 11;
1839                    // rearange fault status
1840                    newVal |= ((fsr >>  0) & 0x3f) << 1;
1841                    newVal |= 0x1; // F bit
1842                    newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1843                    newVal |= armFault->isStage2() ? 0x200 : 0;
1844                    DPRINTF(MiscRegs,
1845                            "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1846                            val, fsr, newVal);
1847                }
1848                delete req;
1849                setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1850                return;
1851            }
1852          case MISCREG_SPSR_EL3:
1853          case MISCREG_SPSR_EL2:
1854          case MISCREG_SPSR_EL1:
1855            // Force bits 23:21 to 0
1856            newVal = val & ~(0x7 << 21);
1857            break;
1858          case MISCREG_L2CTLR:
1859            warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1860                 miscRegName[misc_reg], uint32_t(val));
1861            break;
1862
1863          // Generic Timer registers
1864          case MISCREG_CNTFRQ:
1865          case MISCREG_CNTFRQ_EL0:
1866            getSystemCounter(tc)->setFreq(val);
1867            break;
1868          case MISCREG_CNTP_CVAL:
1869          case MISCREG_CNTP_CVAL_EL0:
1870            getArchTimer(tc, tc->cpuId())->setCompareValue(val);
1871            break;
1872          case MISCREG_CNTP_TVAL:
1873          case MISCREG_CNTP_TVAL_EL0:
1874            getArchTimer(tc, tc->cpuId())->setTimerValue(val);
1875            break;
1876          case MISCREG_CNTP_CTL:
1877          case MISCREG_CNTP_CTL_EL0:
1878            getArchTimer(tc, tc->cpuId())->setControl(val);
1879            break;
1880          // PL1 phys. timer, secure
1881          //   AArch64
1882          case MISCREG_CNTPS_CVAL_EL1:
1883          case MISCREG_CNTPS_TVAL_EL1:
1884          case MISCREG_CNTPS_CTL_EL1:
1885          // PL2 phys. timer, non-secure
1886          //   AArch32
1887          case MISCREG_CNTHCTL:
1888          case MISCREG_CNTHP_CVAL:
1889          case MISCREG_CNTHP_TVAL:
1890          case MISCREG_CNTHP_CTL:
1891          //   AArch64
1892          case MISCREG_CNTHCTL_EL2:
1893          case MISCREG_CNTHP_CVAL_EL2:
1894          case MISCREG_CNTHP_TVAL_EL2:
1895          case MISCREG_CNTHP_CTL_EL2:
1896          // Virtual timer
1897          //   AArch32
1898          case MISCREG_CNTV_CVAL:
1899          case MISCREG_CNTV_TVAL:
1900          case MISCREG_CNTV_CTL:
1901          //   AArch64
1902          // case MISCREG_CNTV_CVAL_EL2:
1903          // case MISCREG_CNTV_TVAL_EL2:
1904          // case MISCREG_CNTV_CTL_EL2:
1905            break;
1906        }
1907    }
1908    setMiscRegNoEffect(misc_reg, newVal);
1909}
1910
1911void
1912ISA::updateBootUncacheable(int sctlr_idx, ThreadContext *tc)
1913{
1914    System *sys;
1915    ThreadContext *oc;
1916
1917    // Check if all CPUs are booted with caches enabled
1918    // so we can stop enforcing coherency of some kernel
1919    // structures manually.
1920    sys = tc->getSystemPtr();
1921    for (int x = 0; x < sys->numContexts(); x++) {
1922        oc = sys->getThreadContext(x);
1923        // @todo: double check this for security
1924        SCTLR other_sctlr = oc->readMiscRegNoEffect(sctlr_idx);
1925        if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
1926            return;
1927    }
1928
1929    for (int x = 0; x < sys->numContexts(); x++) {
1930        oc = sys->getThreadContext(x);
1931        oc->getDTBPtr()->allCpusCaching();
1932        oc->getITBPtr()->allCpusCaching();
1933
1934       // If CheckerCPU is connected, need to notify it.
1935        CheckerCPU *checker = oc->getCheckerCpuPtr();
1936        if (checker) {
1937            checker->getDTBPtr()->allCpusCaching();
1938            checker->getITBPtr()->allCpusCaching();
1939        }
1940    }
1941}
1942
1943void
1944ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
1945            bool secure_lookup, uint8_t target_el)
1946{
1947    if (!haveLargeAsid64)
1948        asid &= mask(8);
1949    Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1950    System *sys = tc->getSystemPtr();
1951    for (int x = 0; x < sys->numContexts(); x++) {
1952        ThreadContext *oc = sys->getThreadContext(x);
1953        assert(oc->getITBPtr() && oc->getDTBPtr());
1954        oc->getITBPtr()->flushMvaAsid(va, asid,
1955                                      secure_lookup, target_el);
1956        oc->getDTBPtr()->flushMvaAsid(va, asid,
1957                                      secure_lookup, target_el);
1958
1959        CheckerCPU *checker = oc->getCheckerCpuPtr();
1960        if (checker) {
1961            checker->getITBPtr()->flushMvaAsid(
1962                va, asid, secure_lookup, target_el);
1963            checker->getDTBPtr()->flushMvaAsid(
1964                va, asid, secure_lookup, target_el);
1965        }
1966    }
1967}
1968
1969void
1970ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el)
1971{
1972    System *sys = tc->getSystemPtr();
1973    for (int x = 0; x < sys->numContexts(); x++) {
1974        ThreadContext *oc = sys->getThreadContext(x);
1975        assert(oc->getITBPtr() && oc->getDTBPtr());
1976        oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1977        oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1978
1979        // If CheckerCPU is connected, need to notify it of a flush
1980        CheckerCPU *checker = oc->getCheckerCpuPtr();
1981        if (checker) {
1982            checker->getITBPtr()->flushAllSecurity(secure_lookup,
1983                                                   target_el);
1984            checker->getDTBPtr()->flushAllSecurity(secure_lookup,
1985                                                   target_el);
1986        }
1987    }
1988}
1989
1990void
1991ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el)
1992{
1993    System *sys = tc->getSystemPtr();
1994    for (int x = 0; x < sys->numContexts(); x++) {
1995      ThreadContext *oc = sys->getThreadContext(x);
1996      assert(oc->getITBPtr() && oc->getDTBPtr());
1997      oc->getITBPtr()->flushAllNs(hyp, target_el);
1998      oc->getDTBPtr()->flushAllNs(hyp, target_el);
1999
2000      CheckerCPU *checker = oc->getCheckerCpuPtr();
2001      if (checker) {
2002          checker->getITBPtr()->flushAllNs(hyp, target_el);
2003          checker->getDTBPtr()->flushAllNs(hyp, target_el);
2004      }
2005    }
2006}
2007
2008void
2009ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
2010             uint8_t target_el)
2011{
2012    System *sys = tc->getSystemPtr();
2013    for (int x = 0; x < sys->numContexts(); x++) {
2014        ThreadContext *oc = sys->getThreadContext(x);
2015        assert(oc->getITBPtr() && oc->getDTBPtr());
2016        oc->getITBPtr()->flushMva(mbits(newVal, 31,12),
2017            secure_lookup, hyp, target_el);
2018        oc->getDTBPtr()->flushMva(mbits(newVal, 31,12),
2019            secure_lookup, hyp, target_el);
2020
2021        CheckerCPU *checker = oc->getCheckerCpuPtr();
2022        if (checker) {
2023            checker->getITBPtr()->flushMva(mbits(newVal, 31,12),
2024                secure_lookup, hyp, target_el);
2025            checker->getDTBPtr()->flushMva(mbits(newVal, 31,12),
2026                secure_lookup, hyp, target_el);
2027        }
2028    }
2029}
2030
2031::GenericTimer::SystemCounter *
2032ISA::getSystemCounter(ThreadContext *tc)
2033{
2034    ::GenericTimer::SystemCounter *cnt = ((ArmSystem *) tc->getSystemPtr())->
2035        getSystemCounter();
2036    if (cnt == NULL) {
2037        panic("System counter not available\n");
2038    }
2039    return cnt;
2040}
2041
2042::GenericTimer::ArchTimer *
2043ISA::getArchTimer(ThreadContext *tc, int cpu_id)
2044{
2045    ::GenericTimer::ArchTimer *timer = ((ArmSystem *) tc->getSystemPtr())->
2046        getArchTimer(cpu_id);
2047    if (timer == NULL) {
2048        panic("Architected timer not available\n");
2049    }
2050    return timer;
2051}
2052
2053}
2054
2055ArmISA::ISA *
2056ArmISAParams::create()
2057{
2058    return new ArmISA::ISA(this);
2059}
2060