isa.cc revision 10653
17405SAli.Saidi@ARM.com/* 211573SDylan.Johnson@ARM.com * Copyright (c) 2010-2014 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 439050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 448887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 4510461SAndreas.Sandberg@ARM.com#include "cpu/base.hh" 468232Snate@binkert.org#include "debug/Arm.hh" 478232Snate@binkert.org#include "debug/MiscRegs.hh" 4810844Sandreas.sandberg@arm.com#include "params/ArmISA.hh" 499384SAndreas.Sandberg@arm.com#include "sim/faults.hh" 507678Sgblack@eecs.umich.edu#include "sim/stat_control.hh" 518059SAli.Saidi@ARM.com#include "sim/system.hh" 528284SAli.Saidi@ARM.com 537405SAli.Saidi@ARM.comnamespace ArmISA 547405SAli.Saidi@ARM.com{ 557405SAli.Saidi@ARM.com 567405SAli.Saidi@ARM.com 5710037SARM gem5 Developers/** 5810037SARM gem5 Developers * Some registers aliase with others, and therefore need to be translated. 5911768SCurtis.Dunham@arm.com * For each entry: 6010037SARM gem5 Developers * The first value is the misc register that is to be looked up 6110037SARM gem5 Developers * the second value is the lower part of the translation 6210037SARM gem5 Developers * the third the upper part 6310037SARM gem5 Developers */ 6411768SCurtis.Dunham@arm.comconst struct ISA::MiscRegInitializerEntry 6510037SARM gem5 Developers ISA::MiscRegSwitch[miscRegTranslateMax] = { 6610037SARM gem5 Developers {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}}, 6711768SCurtis.Dunham@arm.com {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}}, 6811768SCurtis.Dunham@arm.com {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 6911768SCurtis.Dunham@arm.com {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}}, 7011768SCurtis.Dunham@arm.com {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 7111768SCurtis.Dunham@arm.com {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 7211768SCurtis.Dunham@arm.com {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 7311768SCurtis.Dunham@arm.com {MISCREG_HCR_EL2, {MISCREG_HCR, 0}}, 7411768SCurtis.Dunham@arm.com {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 7511768SCurtis.Dunham@arm.com {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 7611768SCurtis.Dunham@arm.com {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 7711768SCurtis.Dunham@arm.com {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}}, 7811768SCurtis.Dunham@arm.com {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}}, 7910037SARM gem5 Developers {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 8010037SARM gem5 Developers {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 8110037SARM gem5 Developers {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}}, 8211768SCurtis.Dunham@arm.com {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 8311768SCurtis.Dunham@arm.com {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 8411768SCurtis.Dunham@arm.com {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}}, 8511768SCurtis.Dunham@arm.com {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}}, 8611768SCurtis.Dunham@arm.com {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 8711768SCurtis.Dunham@arm.com {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 8811768SCurtis.Dunham@arm.com {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 8911768SCurtis.Dunham@arm.com {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}}, 9010037SARM gem5 Developers {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 9111768SCurtis.Dunham@arm.com {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 9211768SCurtis.Dunham@arm.com {MISCREG_PAR_EL1, {MISCREG_PAR, 0}}, 9311768SCurtis.Dunham@arm.com {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}}, 9411768SCurtis.Dunham@arm.com {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 9510037SARM gem5 Developers {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}}, 9611768SCurtis.Dunham@arm.com {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}}, 9711768SCurtis.Dunham@arm.com {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 9811768SCurtis.Dunham@arm.com {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}}, 9911768SCurtis.Dunham@arm.com {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}}, 10011768SCurtis.Dunham@arm.com {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}}, 10111768SCurtis.Dunham@arm.com {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}}, 10211768SCurtis.Dunham@arm.com {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 10311768SCurtis.Dunham@arm.com {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}}, 10411768SCurtis.Dunham@arm.com {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 10511768SCurtis.Dunham@arm.com {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, 10611768SCurtis.Dunham@arm.com {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, 10711768SCurtis.Dunham@arm.com {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, 10811768SCurtis.Dunham@arm.com {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 10911768SCurtis.Dunham@arm.com {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 11011768SCurtis.Dunham@arm.com {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}}, 11111768SCurtis.Dunham@arm.com {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}}, 11211768SCurtis.Dunham@arm.com {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}}, 11311768SCurtis.Dunham@arm.com {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 11410037SARM gem5 Developers {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 11511768SCurtis.Dunham@arm.com {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, 11611768SCurtis.Dunham@arm.com {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 11711768SCurtis.Dunham@arm.com {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 11811768SCurtis.Dunham@arm.com {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, 11910037SARM gem5 Developers {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}}, 12011768SCurtis.Dunham@arm.com {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}}, 12111768SCurtis.Dunham@arm.com {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}}, 12211768SCurtis.Dunham@arm.com {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}} 12311768SCurtis.Dunham@arm.com}; 12411768SCurtis.Dunham@arm.com 12511768SCurtis.Dunham@arm.com 12610037SARM gem5 DevelopersISA::ISA(Params *p) 12711768SCurtis.Dunham@arm.com : SimObject(p), 12811768SCurtis.Dunham@arm.com system(NULL), 12911768SCurtis.Dunham@arm.com pmu(p->pmu), 13011768SCurtis.Dunham@arm.com lookUpMiscReg(NUM_MISCREGS, {0,0}) 13111768SCurtis.Dunham@arm.com{ 13211768SCurtis.Dunham@arm.com SCTLR sctlr; 13311768SCurtis.Dunham@arm.com sctlr = 0; 13411768SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_RST] = sctlr; 13511768SCurtis.Dunham@arm.com 13611768SCurtis.Dunham@arm.com // Hook up a dummy device if we haven't been configured with a 13711768SCurtis.Dunham@arm.com // real PMU. By using a dummy device, we don't need to check that 13811768SCurtis.Dunham@arm.com // the PMU exist every time we try to access a PMU register. 13911768SCurtis.Dunham@arm.com if (!pmu) 14011768SCurtis.Dunham@arm.com pmu = &dummyDevice; 14111768SCurtis.Dunham@arm.com 14211768SCurtis.Dunham@arm.com // Give all ISA devices a pointer to this ISA 14311768SCurtis.Dunham@arm.com pmu->setISA(this); 14411768SCurtis.Dunham@arm.com 14511768SCurtis.Dunham@arm.com system = dynamic_cast<ArmSystem *>(p->system); 14611768SCurtis.Dunham@arm.com DPRINTFN("ISA system set to: %p %p\n", system, p->system); 14711768SCurtis.Dunham@arm.com 14811768SCurtis.Dunham@arm.com // Cache system-level properties 14911768SCurtis.Dunham@arm.com if (FullSystem && system) { 15011768SCurtis.Dunham@arm.com haveSecurity = system->haveSecurity(); 15111768SCurtis.Dunham@arm.com haveLPAE = system->haveLPAE(); 15211768SCurtis.Dunham@arm.com haveVirtualization = system->haveVirtualization(); 15311768SCurtis.Dunham@arm.com haveLargeAsid64 = system->haveLargeAsid64(); 15411768SCurtis.Dunham@arm.com physAddrRange64 = system->physAddrRange64(); 15511768SCurtis.Dunham@arm.com } else { 15611768SCurtis.Dunham@arm.com haveSecurity = haveLPAE = haveVirtualization = false; 15711768SCurtis.Dunham@arm.com haveLargeAsid64 = false; 15811768SCurtis.Dunham@arm.com physAddrRange64 = 32; // dummy value 15911768SCurtis.Dunham@arm.com } 16011768SCurtis.Dunham@arm.com 16111768SCurtis.Dunham@arm.com /** Fill in the miscReg translation table */ 16211768SCurtis.Dunham@arm.com for (uint32_t i = 0; i < miscRegTranslateMax; i++) { 16311768SCurtis.Dunham@arm.com struct MiscRegLUTEntry new_entry; 16411768SCurtis.Dunham@arm.com 16511768SCurtis.Dunham@arm.com uint32_t select = MiscRegSwitch[i].index; 16611768SCurtis.Dunham@arm.com new_entry = MiscRegSwitch[i].entry; 16711768SCurtis.Dunham@arm.com 16811768SCurtis.Dunham@arm.com lookUpMiscReg[select] = new_entry; 16911768SCurtis.Dunham@arm.com } 17011768SCurtis.Dunham@arm.com 17111768SCurtis.Dunham@arm.com preUnflattenMiscReg(); 17211768SCurtis.Dunham@arm.com 17311768SCurtis.Dunham@arm.com clear(); 17411768SCurtis.Dunham@arm.com} 17511768SCurtis.Dunham@arm.com 17611768SCurtis.Dunham@arm.comconst ArmISAParams * 17711768SCurtis.Dunham@arm.comISA::params() const 17811768SCurtis.Dunham@arm.com{ 17911768SCurtis.Dunham@arm.com return dynamic_cast<const Params *>(_params); 18011768SCurtis.Dunham@arm.com} 18111768SCurtis.Dunham@arm.com 18211768SCurtis.Dunham@arm.comvoid 18311768SCurtis.Dunham@arm.comISA::clear() 18411768SCurtis.Dunham@arm.com{ 18511768SCurtis.Dunham@arm.com const Params *p(params()); 18611768SCurtis.Dunham@arm.com 18711768SCurtis.Dunham@arm.com SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 18811768SCurtis.Dunham@arm.com memset(miscRegs, 0, sizeof(miscRegs)); 18911768SCurtis.Dunham@arm.com 19011768SCurtis.Dunham@arm.com // Initialize configurable default values 19111768SCurtis.Dunham@arm.com miscRegs[MISCREG_MIDR] = p->midr; 19211768SCurtis.Dunham@arm.com miscRegs[MISCREG_MIDR_EL1] = p->midr; 19311768SCurtis.Dunham@arm.com miscRegs[MISCREG_VPIDR] = p->midr; 19411768SCurtis.Dunham@arm.com 19511768SCurtis.Dunham@arm.com if (FullSystem && system->highestELIs64()) { 19611768SCurtis.Dunham@arm.com // Initialize AArch64 state 19711768SCurtis.Dunham@arm.com clear64(p); 19811768SCurtis.Dunham@arm.com return; 19911768SCurtis.Dunham@arm.com } 20011768SCurtis.Dunham@arm.com 20111768SCurtis.Dunham@arm.com // Initialize AArch32 state... 20211768SCurtis.Dunham@arm.com 20311768SCurtis.Dunham@arm.com CPSR cpsr = 0; 20410037SARM gem5 Developers cpsr.mode = MODE_USER; 20510037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 20610037SARM gem5 Developers updateRegMap(cpsr); 2079384SAndreas.Sandberg@arm.com 20810461SAndreas.Sandberg@ARM.com SCTLR sctlr = 0; 20910461SAndreas.Sandberg@ARM.com sctlr.te = (bool) sctlr_rst.te; 21011165SRekai.GonzalezAlberquilla@arm.com sctlr.nmfi = (bool) sctlr_rst.nmfi; 21110461SAndreas.Sandberg@ARM.com sctlr.v = (bool) sctlr_rst.v; 21210461SAndreas.Sandberg@ARM.com sctlr.u = 1; 2139384SAndreas.Sandberg@arm.com sctlr.xp = 1; 2149384SAndreas.Sandberg@arm.com sctlr.rao2 = 1; 2159384SAndreas.Sandberg@arm.com sctlr.rao3 = 1; 2169384SAndreas.Sandberg@arm.com sctlr.rao4 = 0xf; // SCTLR[6:3] 21710037SARM gem5 Developers sctlr.uci = 1; 21810461SAndreas.Sandberg@ARM.com sctlr.dze = 1; 21910461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_SCTLR_NS] = sctlr; 22010461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 22110461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_HCPTR] = 0; 22210461SAndreas.Sandberg@ARM.com 22310461SAndreas.Sandberg@ARM.com // Start with an event in the mailbox 22410609Sandreas.sandberg@arm.com miscRegs[MISCREG_SEV_MAILBOX] = 1; 22510609Sandreas.sandberg@arm.com 22610609Sandreas.sandberg@arm.com // Separate Instruction and Data TLBs 22710037SARM gem5 Developers miscRegs[MISCREG_TLBTR] = 1; 22810037SARM gem5 Developers 22910037SARM gem5 Developers MVFR0 mvfr0 = 0; 23010037SARM gem5 Developers mvfr0.advSimdRegisters = 2; 23110037SARM gem5 Developers mvfr0.singlePrecision = 2; 23210037SARM gem5 Developers mvfr0.doublePrecision = 2; 23310037SARM gem5 Developers mvfr0.vfpExceptionTrapping = 0; 23410037SARM gem5 Developers mvfr0.divide = 1; 23510037SARM gem5 Developers mvfr0.squareRoot = 1; 23610037SARM gem5 Developers mvfr0.shortVectors = 1; 23710037SARM gem5 Developers mvfr0.roundingModes = 1; 23810037SARM gem5 Developers miscRegs[MISCREG_MVFR0] = mvfr0; 23910037SARM gem5 Developers 24010037SARM gem5 Developers MVFR1 mvfr1 = 0; 24110037SARM gem5 Developers mvfr1.flushToZero = 1; 24210037SARM gem5 Developers mvfr1.defaultNaN = 1; 24311768SCurtis.Dunham@arm.com mvfr1.advSimdLoadStore = 1; 24411768SCurtis.Dunham@arm.com mvfr1.advSimdInteger = 1; 24510037SARM gem5 Developers mvfr1.advSimdSinglePrecision = 1; 24610037SARM gem5 Developers mvfr1.advSimdHalfPrecision = 1; 24710037SARM gem5 Developers mvfr1.vfpHalfPrecision = 1; 24810037SARM gem5 Developers miscRegs[MISCREG_MVFR1] = mvfr1; 2499384SAndreas.Sandberg@arm.com 2509384SAndreas.Sandberg@arm.com // Reset values of PRRR and NMRR are implementation dependent 2519384SAndreas.Sandberg@arm.com 2529384SAndreas.Sandberg@arm.com // @todo: PRRR and NMRR in secure state? 2539384SAndreas.Sandberg@arm.com miscRegs[MISCREG_PRRR_NS] = 2549384SAndreas.Sandberg@arm.com (1 << 19) | // 19 2559384SAndreas.Sandberg@arm.com (0 << 18) | // 18 2569384SAndreas.Sandberg@arm.com (0 << 17) | // 17 2579384SAndreas.Sandberg@arm.com (1 << 16) | // 16 2587427Sgblack@eecs.umich.edu (2 << 14) | // 15:14 2597427Sgblack@eecs.umich.edu (0 << 12) | // 13:12 2607427Sgblack@eecs.umich.edu (2 << 10) | // 11:10 2619385SAndreas.Sandberg@arm.com (2 << 8) | // 9:8 2629385SAndreas.Sandberg@arm.com (2 << 6) | // 7:6 2637427Sgblack@eecs.umich.edu (2 << 4) | // 5:4 2647427Sgblack@eecs.umich.edu (1 << 2) | // 3:2 26510037SARM gem5 Developers 0; // 1:0 26610037SARM gem5 Developers miscRegs[MISCREG_NMRR_NS] = 26710037SARM gem5 Developers (1 << 30) | // 31:30 26810037SARM gem5 Developers (0 << 26) | // 27:26 26910037SARM gem5 Developers (0 << 24) | // 25:24 27010037SARM gem5 Developers (3 << 22) | // 23:22 27110037SARM gem5 Developers (2 << 20) | // 21:20 27210037SARM gem5 Developers (0 << 18) | // 19:18 27310037SARM gem5 Developers (0 << 16) | // 17:16 27410037SARM gem5 Developers (1 << 14) | // 15:14 27510037SARM gem5 Developers (0 << 12) | // 13:12 27610037SARM gem5 Developers (2 << 10) | // 11:10 27710037SARM gem5 Developers (0 << 8) | // 9:8 27810037SARM gem5 Developers (3 << 6) | // 7:6 2797427Sgblack@eecs.umich.edu (2 << 4) | // 5:4 2807427Sgblack@eecs.umich.edu (0 << 2) | // 3:2 2817427Sgblack@eecs.umich.edu 0; // 1:0 2827427Sgblack@eecs.umich.edu 2837427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPACR] = 0; 2847427Sgblack@eecs.umich.edu 28510037SARM gem5 Developers 28610037SARM gem5 Developers miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 28710037SARM gem5 Developers miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 28810037SARM gem5 Developers 2897427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 2907427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 2917427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 29210037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 29310204SAli.Saidi@ARM.com 29410204SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 29510037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 2967427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 29710037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 2987427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 29910037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 3007427Sgblack@eecs.umich.edu 3017427Sgblack@eecs.umich.edu miscRegs[MISCREG_FPSID] = p->fpsid; 30210037SARM gem5 Developers 3037427Sgblack@eecs.umich.edu if (haveLPAE) { 3047427Sgblack@eecs.umich.edu TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 3057427Sgblack@eecs.umich.edu ttbcr.eae = 0; 3067427Sgblack@eecs.umich.edu miscRegs[MISCREG_TTBCR_NS] = ttbcr; 3077427Sgblack@eecs.umich.edu // Enforce consistency with system-level settings 3087427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 3097427Sgblack@eecs.umich.edu } 3107427Sgblack@eecs.umich.edu 3117427Sgblack@eecs.umich.edu if (haveSecurity) { 3127427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_S] = sctlr; 3137427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR] = 0; 3147427Sgblack@eecs.umich.edu miscRegs[MISCREG_VBAR_S] = 0; 3157427Sgblack@eecs.umich.edu } else { 3167427Sgblack@eecs.umich.edu // we're always non-secure 3177427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR] = 1; 3187427Sgblack@eecs.umich.edu } 3197427Sgblack@eecs.umich.edu 3207427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 3217427Sgblack@eecs.umich.edu} 3227427Sgblack@eecs.umich.edu 3237427Sgblack@eecs.umich.eduvoid 3247427Sgblack@eecs.umich.eduISA::clear64(const ArmISAParams *p) 3257427Sgblack@eecs.umich.edu{ 3267436Sdam.sunwoo@arm.com CPSR cpsr = 0; 3277436Sdam.sunwoo@arm.com Addr rvbar = system->resetAddr64(); 32810037SARM gem5 Developers switch (system->highestEL()) { 32910037SARM gem5 Developers // Set initial EL to highest implemented EL using associated stack 3307436Sdam.sunwoo@arm.com // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 3317436Sdam.sunwoo@arm.com // value 3327436Sdam.sunwoo@arm.com case EL3: 3337436Sdam.sunwoo@arm.com cpsr.mode = MODE_EL3H; 3347436Sdam.sunwoo@arm.com miscRegs[MISCREG_RVBAR_EL3] = rvbar; 3357436Sdam.sunwoo@arm.com break; 3367436Sdam.sunwoo@arm.com case EL2: 3377436Sdam.sunwoo@arm.com cpsr.mode = MODE_EL2H; 3387436Sdam.sunwoo@arm.com miscRegs[MISCREG_RVBAR_EL2] = rvbar; 3397436Sdam.sunwoo@arm.com break; 3407436Sdam.sunwoo@arm.com case EL1: 3417436Sdam.sunwoo@arm.com cpsr.mode = MODE_EL1H; 34210037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL1] = rvbar; 3437436Sdam.sunwoo@arm.com break; 3447436Sdam.sunwoo@arm.com default: 3457436Sdam.sunwoo@arm.com panic("Invalid highest implemented exception level"); 3467436Sdam.sunwoo@arm.com break; 3477436Sdam.sunwoo@arm.com } 3487436Sdam.sunwoo@arm.com 3497436Sdam.sunwoo@arm.com // Initialize rest of CPSR 3507436Sdam.sunwoo@arm.com cpsr.daif = 0xf; // Mask all interrupts 3517436Sdam.sunwoo@arm.com cpsr.ss = 0; 3527436Sdam.sunwoo@arm.com cpsr.il = 0; 3537436Sdam.sunwoo@arm.com miscRegs[MISCREG_CPSR] = cpsr; 3547436Sdam.sunwoo@arm.com updateRegMap(cpsr); 3557436Sdam.sunwoo@arm.com 3567436Sdam.sunwoo@arm.com // Initialize other control registers 3577436Sdam.sunwoo@arm.com miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 3587436Sdam.sunwoo@arm.com if (haveSecurity) { 3597644Sali.saidi@arm.com miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870; 3608147SAli.Saidi@ARM.com miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 3619385SAndreas.Sandberg@arm.com // @todo: uncomment this to enable Virtualization 3629385SAndreas.Sandberg@arm.com // } else if (haveVirtualization) { 3639385SAndreas.Sandberg@arm.com // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870; 3649385SAndreas.Sandberg@arm.com } else { 3659385SAndreas.Sandberg@arm.com miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870; 3669385SAndreas.Sandberg@arm.com // Always non-secure 3679385SAndreas.Sandberg@arm.com miscRegs[MISCREG_SCR_EL3] = 1; 3689385SAndreas.Sandberg@arm.com } 3699385SAndreas.Sandberg@arm.com 3709385SAndreas.Sandberg@arm.com // Initialize configurable id registers 3719385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 3729385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 3739385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 3749385SAndreas.Sandberg@arm.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 3759385SAndreas.Sandberg@arm.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 3769385SAndreas.Sandberg@arm.com 3779385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 3789385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 37910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 38010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 38110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 38210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 38310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; 38410037SARM gem5 Developers 38510037SARM gem5 Developers miscRegs[MISCREG_ID_DFR0_EL1] = 38610037SARM gem5 Developers (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 38710037SARM gem5 Developers 38810037SARM gem5 Developers miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 38910037SARM gem5 Developers 39010037SARM gem5 Developers // Enforce consistency with system-level settings... 39110037SARM gem5 Developers 39210037SARM gem5 Developers // EL3 39310037SARM gem5 Developers // (no AArch32/64 interprocessing support for now) 39410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 3958147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 3967427Sgblack@eecs.umich.edu haveSecurity ? 0x1 : 0x0); 3977427Sgblack@eecs.umich.edu // EL2 3987427Sgblack@eecs.umich.edu // (no AArch32/64 interprocessing support for now) 39910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 40010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 40110037SARM gem5 Developers haveVirtualization ? 0x1 : 0x0); 40210037SARM gem5 Developers // Large ASID support 40310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 40410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 40510037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 40610037SARM gem5 Developers // Physical address size 40710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 40810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 40910037SARM gem5 Developers encodePhysAddrRange64(physAddrRange64)); 41010037SARM gem5 Developers} 41110037SARM gem5 Developers 41210037SARM gem5 DevelopersMiscReg 41310037SARM gem5 DevelopersISA::readMiscRegNoEffect(int misc_reg) const 41410037SARM gem5 Developers{ 41510037SARM gem5 Developers assert(misc_reg < NumMiscRegs); 41610037SARM gem5 Developers 41710037SARM gem5 Developers int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 41810037SARM gem5 Developers // registers are left unchanged 41910037SARM gem5 Developers MiscReg val; 42010037SARM gem5 Developers 42110037SARM gem5 Developers if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR 42210037SARM gem5 Developers || flat_idx == MISCREG_SCTLR_EL1) { 42310037SARM gem5 Developers if (flat_idx == MISCREG_SPSR) 42410037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_SPSR); 42510037SARM gem5 Developers if (flat_idx == MISCREG_SCTLR_EL1) 42610037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_SCTLR); 42710037SARM gem5 Developers val = miscRegs[flat_idx]; 42810037SARM gem5 Developers } else 42910037SARM gem5 Developers if (lookUpMiscReg[flat_idx].upper > 0) 43010037SARM gem5 Developers val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32)) 43110037SARM gem5 Developers | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32)); 43210037SARM gem5 Developers else 43310037SARM gem5 Developers val = miscRegs[lookUpMiscReg[flat_idx].lower]; 43410037SARM gem5 Developers 43510037SARM gem5 Developers return val; 43610037SARM gem5 Developers} 43711574SCurtis.Dunham@arm.com 43811574SCurtis.Dunham@arm.com 43910037SARM gem5 DevelopersMiscReg 44010037SARM gem5 DevelopersISA::readMiscReg(int misc_reg, ThreadContext *tc) 44110037SARM gem5 Developers{ 44210037SARM gem5 Developers CPSR cpsr = 0; 44310037SARM gem5 Developers PCState pc = 0; 44410037SARM gem5 Developers SCR scr = 0; 44510037SARM gem5 Developers 44610037SARM gem5 Developers if (misc_reg == MISCREG_CPSR) { 44710037SARM gem5 Developers cpsr = miscRegs[misc_reg]; 44810461SAndreas.Sandberg@ARM.com pc = tc->pcState(); 44910461SAndreas.Sandberg@ARM.com cpsr.j = pc.jazelle() ? 1 : 0; 45010461SAndreas.Sandberg@ARM.com cpsr.t = pc.thumb() ? 1 : 0; 45110461SAndreas.Sandberg@ARM.com return cpsr; 45210037SARM gem5 Developers } 45310037SARM gem5 Developers 45410037SARM gem5 Developers#ifndef NDEBUG 45510037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 45610037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 45710037SARM gem5 Developers warn("Unimplemented system register %s read.\n", 45810037SARM gem5 Developers miscRegName[misc_reg]); 45910037SARM gem5 Developers else 46010461SAndreas.Sandberg@ARM.com panic("Unimplemented system register %s read.\n", 46110461SAndreas.Sandberg@ARM.com miscRegName[misc_reg]); 46210461SAndreas.Sandberg@ARM.com } 46310461SAndreas.Sandberg@ARM.com#endif 46410461SAndreas.Sandberg@ARM.com 46510037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 46610037SARM gem5 Developers case MISCREG_HCR: 46710037SARM gem5 Developers { 46810037SARM gem5 Developers if (!haveVirtualization) 46910037SARM gem5 Developers return 0; 47011574SCurtis.Dunham@arm.com else 47110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HCR); 47210037SARM gem5 Developers } 47310037SARM gem5 Developers case MISCREG_CPACR: 47411574SCurtis.Dunham@arm.com { 47510037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 47610037SARM gem5 Developers CPACR cpacrMask = 0; 47710037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 47810037SARM gem5 Developers // be readable? (straight copy from the write code) 47910037SARM gem5 Developers cpacrMask.cp10 = ones; 48010037SARM gem5 Developers cpacrMask.cp11 = ones; 48110037SARM gem5 Developers cpacrMask.asedis = ones; 48210037SARM gem5 Developers 48310037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 48410037SARM gem5 Developers if (haveSecurity) { 4857405SAli.Saidi@ARM.com scr = readMiscRegNoEffect(MISCREG_SCR); 48610035Sandreas.hansson@arm.com cpsr = readMiscRegNoEffect(MISCREG_CPSR); 4877405SAli.Saidi@ARM.com if (scr.ns && (cpsr.mode != MODE_MON)) { 4887405SAli.Saidi@ARM.com NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 4897614Sminkyu.jeong@arm.com // NB: Skipping the full loop, here 49010037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 49110037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 49210037SARM gem5 Developers } 4937614Sminkyu.jeong@arm.com } 49410037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 49510037SARM gem5 Developers val &= cpacrMask; 49610037SARM gem5 Developers DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 49710037SARM gem5 Developers miscRegName[misc_reg], val); 49810037SARM gem5 Developers return val; 49910037SARM gem5 Developers } 50010037SARM gem5 Developers case MISCREG_MPIDR: 50110037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 50210037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 50310037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 50410037SARM gem5 Developers return getMPIDR(system, tc); 50510037SARM gem5 Developers } else { 50610037SARM gem5 Developers return readMiscReg(MISCREG_VMPIDR, tc); 50710037SARM gem5 Developers } 5087614Sminkyu.jeong@arm.com break; 5097405SAli.Saidi@ARM.com case MISCREG_MPIDR_EL1: 5107405SAli.Saidi@ARM.com // @todo in the absence of v8 virtualization support just return MPIDR_EL1 5117405SAli.Saidi@ARM.com return getMPIDR(system, tc) & 0xffffffff; 5127405SAli.Saidi@ARM.com case MISCREG_VMPIDR: 5137405SAli.Saidi@ARM.com // top bit defined as RES1 5147405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg) | 0x80000000; 51510037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 51610037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 51710037SARM gem5 Developers case MISCREG_MIDR: 5189050Schander.sudanthi@arm.com cpsr = readMiscRegNoEffect(MISCREG_CPSR); 5197405SAli.Saidi@ARM.com scr = readMiscRegNoEffect(MISCREG_SCR); 52010037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 52110037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 5227720Sgblack@eecs.umich.edu } else { 5237720Sgblack@eecs.umich.edu return readMiscRegNoEffect(MISCREG_VPIDR); 5247405SAli.Saidi@ARM.com } 5257405SAli.Saidi@ARM.com break; 5267757SAli.Saidi@ARM.com case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 52710037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 52810037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 52910037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 53010037SARM gem5 Developers case MISCREG_TCMTR: // No TCM's 53110037SARM gem5 Developers return 0; 53210037SARM gem5 Developers 53310037SARM gem5 Developers case MISCREG_CLIDR: 53410037SARM gem5 Developers warn_once("The clidr register always reports 0 caches.\n"); 53510037SARM gem5 Developers warn_once("clidr LoUIS field of 0b001 to match current " 53610037SARM gem5 Developers "ARM implementations.\n"); 53710037SARM gem5 Developers return 0x00200000; 53810037SARM gem5 Developers case MISCREG_CCSIDR: 53910037SARM gem5 Developers warn_once("The ccsidr register isn't implemented and " 54010037SARM gem5 Developers "always reads as 0.\n"); 54110037SARM gem5 Developers break; 54210037SARM gem5 Developers case MISCREG_CTR: 54310037SARM gem5 Developers { 54410037SARM gem5 Developers //all caches have the same line size in gem5 54510037SARM gem5 Developers //4 byte words in ARM 54610037SARM gem5 Developers unsigned lineSizeWords = 54710037SARM gem5 Developers tc->getSystemPtr()->cacheLineSize() / 4; 54810037SARM gem5 Developers unsigned log2LineSizeWords = 0; 54910037SARM gem5 Developers 55010037SARM gem5 Developers while (lineSizeWords >>= 1) { 55110037SARM gem5 Developers ++log2LineSizeWords; 55210037SARM gem5 Developers } 55310037SARM gem5 Developers 55410037SARM gem5 Developers CTR ctr = 0; 55510037SARM gem5 Developers //log2 of minimun i-cache line size (words) 55610037SARM gem5 Developers ctr.iCacheLineSize = log2LineSizeWords; 55710037SARM gem5 Developers //b11 - gem5 uses pipt 55810037SARM gem5 Developers ctr.l1IndexPolicy = 0x3; 55910037SARM gem5 Developers //log2 of minimum d-cache line size (words) 56010037SARM gem5 Developers ctr.dCacheLineSize = log2LineSizeWords; 56110037SARM gem5 Developers //log2 of max reservation size (words) 56210037SARM gem5 Developers ctr.erg = log2LineSizeWords; 56310037SARM gem5 Developers //log2 of max writeback size (words) 56410037SARM gem5 Developers ctr.cwg = log2LineSizeWords; 56510037SARM gem5 Developers //b100 - gem5 format is ARMv7 56610037SARM gem5 Developers ctr.format = 0x4; 56710037SARM gem5 Developers 56810037SARM gem5 Developers return ctr; 56910037SARM gem5 Developers } 57010037SARM gem5 Developers case MISCREG_ACTLR: 57110037SARM gem5 Developers warn("Not doing anything for miscreg ACTLR\n"); 57210037SARM gem5 Developers break; 5738284SAli.Saidi@ARM.com 57410037SARM gem5 Developers case MISCREG_PMXEVTYPER_PMCCFILTR: 57510037SARM gem5 Developers case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 57610037SARM gem5 Developers case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 57710037SARM gem5 Developers case MISCREG_PMCR ... MISCREG_PMOVSSET: 5789050Schander.sudanthi@arm.com return pmu->readMiscReg(misc_reg); 57910037SARM gem5 Developers 58010037SARM gem5 Developers case MISCREG_CPSR_Q: 58110037SARM gem5 Developers panic("shouldn't be reading this register seperately\n"); 58210037SARM gem5 Developers case MISCREG_FPSCR_QC: 58310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 58410037SARM gem5 Developers case MISCREG_FPSCR_EXC: 58510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 58610037SARM gem5 Developers case MISCREG_FPSR: 58710037SARM gem5 Developers { 58810037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 58910037SARM gem5 Developers FPSCR fpscrMask = 0; 59010037SARM gem5 Developers fpscrMask.ioc = ones; 59110037SARM gem5 Developers fpscrMask.dzc = ones; 59210037SARM gem5 Developers fpscrMask.ofc = ones; 59310037SARM gem5 Developers fpscrMask.ufc = ones; 59410037SARM gem5 Developers fpscrMask.ixc = ones; 59510037SARM gem5 Developers fpscrMask.idc = ones; 59610037SARM gem5 Developers fpscrMask.qc = ones; 5979050Schander.sudanthi@arm.com fpscrMask.v = ones; 5988284SAli.Saidi@ARM.com fpscrMask.c = ones; 59910037SARM gem5 Developers fpscrMask.z = ones; 60010037SARM gem5 Developers fpscrMask.n = ones; 60110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 60210037SARM gem5 Developers } 60310037SARM gem5 Developers case MISCREG_FPCR: 60410037SARM gem5 Developers { 60510037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 6067405SAli.Saidi@ARM.com FPSCR fpscrMask = 0; 6077731SAli.Saidi@ARM.com fpscrMask.ioe = ones; 6088468Swade.walker@arm.com fpscrMask.dze = ones; 6098468Swade.walker@arm.com fpscrMask.ofe = ones; 6108468Swade.walker@arm.com fpscrMask.ufe = ones; 6117405SAli.Saidi@ARM.com fpscrMask.ixe = ones; 6127731SAli.Saidi@ARM.com fpscrMask.ide = ones; 6137405SAli.Saidi@ARM.com fpscrMask.len = ones; 6147405SAli.Saidi@ARM.com fpscrMask.stride = ones; 6157583SAli.Saidi@arm.com fpscrMask.rMode = ones; 6169130Satgutier@umich.edu fpscrMask.fz = ones; 6179130Satgutier@umich.edu fpscrMask.dn = ones; 6189130Satgutier@umich.edu fpscrMask.ahp = ones; 6199130Satgutier@umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 6209814Sandreas.hansson@arm.com } 6219130Satgutier@umich.edu case MISCREG_NZCV: 6229130Satgutier@umich.edu { 6239130Satgutier@umich.edu CPSR cpsr = 0; 6249130Satgutier@umich.edu cpsr.nz = tc->readCCReg(CCREG_NZ); 6259130Satgutier@umich.edu cpsr.c = tc->readCCReg(CCREG_C); 6269130Satgutier@umich.edu cpsr.v = tc->readCCReg(CCREG_V); 6279130Satgutier@umich.edu return cpsr; 6289130Satgutier@umich.edu } 6299130Satgutier@umich.edu case MISCREG_DAIF: 6309130Satgutier@umich.edu { 6319130Satgutier@umich.edu CPSR cpsr = 0; 6329130Satgutier@umich.edu cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 6339130Satgutier@umich.edu return cpsr; 6349130Satgutier@umich.edu } 6359130Satgutier@umich.edu case MISCREG_SP_EL0: 6369130Satgutier@umich.edu { 6379130Satgutier@umich.edu return tc->readIntReg(INTREG_SP0); 6389130Satgutier@umich.edu } 6399130Satgutier@umich.edu case MISCREG_SP_EL1: 6409130Satgutier@umich.edu { 6419130Satgutier@umich.edu return tc->readIntReg(INTREG_SP1); 6429130Satgutier@umich.edu } 6437583SAli.Saidi@arm.com case MISCREG_SP_EL2: 6447583SAli.Saidi@arm.com { 6457583SAli.Saidi@arm.com return tc->readIntReg(INTREG_SP2); 64610461SAndreas.Sandberg@ARM.com } 64710461SAndreas.Sandberg@ARM.com case MISCREG_SPSEL: 64810461SAndreas.Sandberg@ARM.com { 64910461SAndreas.Sandberg@ARM.com return miscRegs[MISCREG_CPSR] & 0x1; 65010461SAndreas.Sandberg@ARM.com } 65110461SAndreas.Sandberg@ARM.com case MISCREG_CURRENTEL: 65210461SAndreas.Sandberg@ARM.com { 6538302SAli.Saidi@ARM.com return miscRegs[MISCREG_CPSR] & 0xc; 6548302SAli.Saidi@ARM.com } 6557783SGiacomo.Gabrielli@arm.com case MISCREG_L2CTLR: 6567783SGiacomo.Gabrielli@arm.com { 6577783SGiacomo.Gabrielli@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 6587783SGiacomo.Gabrielli@arm.com L2CTLR l2ctlr = 0; 65910037SARM gem5 Developers // b00:1CPU to b11:4CPUs 66010037SARM gem5 Developers l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 66110037SARM gem5 Developers return l2ctlr; 66210037SARM gem5 Developers } 66310037SARM gem5 Developers case MISCREG_DBGDIDR: 66410037SARM gem5 Developers /* For now just implement the version number. 66510037SARM gem5 Developers * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 66610037SARM gem5 Developers */ 66710037SARM gem5 Developers return 0x5 << 16; 66810037SARM gem5 Developers case MISCREG_DBGDSCRint: 66910037SARM gem5 Developers return 0; 67010037SARM gem5 Developers case MISCREG_ISR: 67110037SARM gem5 Developers return tc->getCpuPtr()->getInterruptController()->getISR( 67210037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR), 67310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 67410037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR)); 67510037SARM gem5 Developers case MISCREG_ISR_EL1: 67610037SARM gem5 Developers return tc->getCpuPtr()->getInterruptController()->getISR( 67710037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR_EL2), 67810037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 67910037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR_EL3)); 68010037SARM gem5 Developers case MISCREG_DCZID_EL0: 68110037SARM gem5 Developers return 0x04; // DC ZVA clear 64-byte chunks 68210037SARM gem5 Developers case MISCREG_HCPTR: 68310037SARM gem5 Developers { 68410037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(misc_reg); 68510037SARM gem5 Developers // The trap bit associated with CP14 is defined as RAZ 68610037SARM gem5 Developers val &= ~(1 << 14); 68710037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 68810037SARM gem5 Developers // HCPTR is RAO/WI 68910037SARM gem5 Developers bool secure_lookup = haveSecurity && 69010037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 69110037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 69210037SARM gem5 Developers if (!secure_lookup) { 69310037SARM gem5 Developers MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 69410037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 69510037SARM gem5 Developers } 69610037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 69710338SCurtis.Dunham@arm.com val |= 0x33FF; 69810338SCurtis.Dunham@arm.com return (val); 69910338SCurtis.Dunham@arm.com } 70010037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 70110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 70210037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 70310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 70410037SARM gem5 Developers case MISCREG_HVBAR: // bottom bits reserved 70510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 70610037SARM gem5 Developers case MISCREG_SCTLR: // Some bits hardwired 70710037SARM gem5 Developers // The FI field (bit 21) is common between S/NS versions of the register 70810037SARM gem5 Developers return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 70910037SARM gem5 Developers (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR 71010037SARM gem5 Developers case MISCREG_SCTLR_EL1: 71110037SARM gem5 Developers // The FI field (bit 21) is common between S/NS versions of the register 71210037SARM gem5 Developers return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 71310037SARM gem5 Developers (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1 71410037SARM gem5 Developers case MISCREG_SCTLR_EL3: 71510037SARM gem5 Developers // The FI field (bit 21) is common between S/NS versions of the register 71610037SARM gem5 Developers return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 71710037SARM gem5 Developers (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3 71810037SARM gem5 Developers case MISCREG_HSCTLR: // FI comes from SCTLR 71910037SARM gem5 Developers { 72010037SARM gem5 Developers uint32_t mask = 1 << 27; 72110037SARM gem5 Developers return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) | 72210037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_SCTLR) & mask); 72310037SARM gem5 Developers } 72410037SARM gem5 Developers case MISCREG_SCR: 72510037SARM gem5 Developers { 72610037SARM gem5 Developers CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 72710037SARM gem5 Developers if (cpsr.width) { 7288549Sdaniel.johnson@arm.com return readMiscRegNoEffect(MISCREG_SCR); 7298868SMatt.Horsnell@arm.com } else { 7308868SMatt.Horsnell@arm.com return readMiscRegNoEffect(MISCREG_SCR_EL3); 7318868SMatt.Horsnell@arm.com } 7328868SMatt.Horsnell@arm.com } 7338868SMatt.Horsnell@arm.com // Generic Timer registers 7348868SMatt.Horsnell@arm.com case MISCREG_CNTFRQ: 7358868SMatt.Horsnell@arm.com case MISCREG_CNTFRQ_EL0: 7368868SMatt.Horsnell@arm.com inform_once("Read CNTFREQ_EL0 frequency\n"); 7378868SMatt.Horsnell@arm.com return getSystemCounter(tc)->freq(); 73810461SAndreas.Sandberg@ARM.com case MISCREG_CNTPCT: 7398868SMatt.Horsnell@arm.com case MISCREG_CNTPCT_EL0: 74010461SAndreas.Sandberg@ARM.com return getSystemCounter(tc)->value(); 74110037SARM gem5 Developers case MISCREG_CNTVCT: 7428868SMatt.Horsnell@arm.com return getSystemCounter(tc)->value(); 74310037SARM gem5 Developers case MISCREG_CNTVCT_EL0: 74411150Smitch.hayenga@arm.com return getSystemCounter(tc)->value(); 74510037SARM gem5 Developers case MISCREG_CNTP_CVAL: 74610037SARM gem5 Developers case MISCREG_CNTP_CVAL_EL0: 74710037SARM gem5 Developers return getArchTimer(tc, tc->cpuId())->compareValue(); 74810037SARM gem5 Developers case MISCREG_CNTP_TVAL: 74911150Smitch.hayenga@arm.com case MISCREG_CNTP_TVAL_EL0: 75010037SARM gem5 Developers return getArchTimer(tc, tc->cpuId())->timerValue(); 75110037SARM gem5 Developers case MISCREG_CNTP_CTL: 75210037SARM gem5 Developers case MISCREG_CNTP_CTL_EL0: 75310037SARM gem5 Developers return getArchTimer(tc, tc->cpuId())->control(); 75410037SARM gem5 Developers // PL1 phys. timer, secure 75510037SARM gem5 Developers // AArch64 75610037SARM gem5 Developers // case MISCREG_CNTPS_CVAL_EL1: 75710037SARM gem5 Developers // case MISCREG_CNTPS_TVAL_EL1: 75810037SARM gem5 Developers // case MISCREG_CNTPS_CTL_EL1: 75910037SARM gem5 Developers // PL2 phys. timer, non-secure 76010037SARM gem5 Developers // AArch32 76110037SARM gem5 Developers // case MISCREG_CNTHCTL: 76210037SARM gem5 Developers // case MISCREG_CNTHP_CVAL: 76310037SARM gem5 Developers // case MISCREG_CNTHP_TVAL: 76410037SARM gem5 Developers // case MISCREG_CNTHP_CTL: 76510037SARM gem5 Developers // AArch64 76610037SARM gem5 Developers // case MISCREG_CNTHCTL_EL2: 76710037SARM gem5 Developers // case MISCREG_CNTHP_CVAL_EL2: 76810037SARM gem5 Developers // case MISCREG_CNTHP_TVAL_EL2: 76910037SARM gem5 Developers // case MISCREG_CNTHP_CTL_EL2: 77010037SARM gem5 Developers // Virtual timer 77110037SARM gem5 Developers // AArch32 77210037SARM gem5 Developers // case MISCREG_CNTV_CVAL: 77310037SARM gem5 Developers // case MISCREG_CNTV_TVAL: 77410037SARM gem5 Developers // case MISCREG_CNTV_CTL: 77510037SARM gem5 Developers // AArch64 77610037SARM gem5 Developers // case MISCREG_CNTV_CVAL_EL2: 77710037SARM gem5 Developers // case MISCREG_CNTV_TVAL_EL2: 77810037SARM gem5 Developers // case MISCREG_CNTV_CTL_EL2: 77911769SCurtis.Dunham@arm.com default: 78011769SCurtis.Dunham@arm.com break; 78110037SARM gem5 Developers 78211769SCurtis.Dunham@arm.com } 78310037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 78411769SCurtis.Dunham@arm.com} 78511769SCurtis.Dunham@arm.com 78611769SCurtis.Dunham@arm.comvoid 78710844Sandreas.sandberg@arm.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 78810037SARM gem5 Developers{ 78910844Sandreas.sandberg@arm.com assert(misc_reg < NumMiscRegs); 79010844Sandreas.sandberg@arm.com 79110844Sandreas.sandberg@arm.com int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 79210844Sandreas.sandberg@arm.com // registers are left unchanged 79310844Sandreas.sandberg@arm.com 79410844Sandreas.sandberg@arm.com int flat_idx2 = lookUpMiscReg[flat_idx].upper; 79510188Sgeoffrey.blake@arm.com 79610037SARM gem5 Developers if (flat_idx2 > 0) { 79710037SARM gem5 Developers miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0); 7987405SAli.Saidi@ARM.com miscRegs[flat_idx2] = bits(val, 63, 32); 7997405SAli.Saidi@ARM.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 8007405SAli.Saidi@ARM.com misc_reg, flat_idx, flat_idx2, val); 8017405SAli.Saidi@ARM.com } else { 8027405SAli.Saidi@ARM.com if (flat_idx == MISCREG_SPSR) 8037405SAli.Saidi@ARM.com flat_idx = flattenMiscIndex(MISCREG_SPSR); 8047405SAli.Saidi@ARM.com else if (flat_idx == MISCREG_SCTLR_EL1) 8057405SAli.Saidi@ARM.com flat_idx = flattenMiscIndex(MISCREG_SCTLR); 8067614Sminkyu.jeong@arm.com else 80710037SARM gem5 Developers flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ? 80810037SARM gem5 Developers lookUpMiscReg[flat_idx].lower : flat_idx; 8097614Sminkyu.jeong@arm.com miscRegs[flat_idx] = val; 81010037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 81110037SARM gem5 Developers misc_reg, flat_idx, val); 81210037SARM gem5 Developers } 81310037SARM gem5 Developers} 81410037SARM gem5 Developers 81510037SARM gem5 Developersvoid 81610037SARM gem5 DevelopersISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 81710037SARM gem5 Developers{ 81810037SARM gem5 Developers 81910037SARM gem5 Developers MiscReg newVal = val; 82010037SARM gem5 Developers int x; 82110037SARM gem5 Developers bool secure_lookup; 82210037SARM gem5 Developers bool hyp; 82310037SARM gem5 Developers System *sys; 82410037SARM gem5 Developers ThreadContext *oc; 82510037SARM gem5 Developers uint8_t target_el; 82610037SARM gem5 Developers uint16_t asid; 82710037SARM gem5 Developers SCR scr; 82810037SARM gem5 Developers 8297405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 8307405SAli.Saidi@ARM.com updateRegMap(val); 8317405SAli.Saidi@ARM.com 8327405SAli.Saidi@ARM.com 8337405SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 8347749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 8357405SAli.Saidi@ARM.com CPSR cpsr = val; 8368284SAli.Saidi@ARM.com if (old_mode != cpsr.mode) { 83710037SARM gem5 Developers tc->getITBPtr()->invalidateMiscReg(); 83810037SARM gem5 Developers tc->getDTBPtr()->invalidateMiscReg(); 8398284SAli.Saidi@ARM.com } 8408284SAli.Saidi@ARM.com 84110037SARM gem5 Developers DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 84210037SARM gem5 Developers miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 84310037SARM gem5 Developers PCState pc = tc->pcState(); 8448284SAli.Saidi@ARM.com pc.nextThumb(cpsr.t); 8457405SAli.Saidi@ARM.com pc.nextJazelle(cpsr.j); 8467405SAli.Saidi@ARM.com 8477749SAli.Saidi@ARM.com // Follow slightly different semantics if a CheckerCPU object 8487749SAli.Saidi@ARM.com // is connected 8497749SAli.Saidi@ARM.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 8507749SAli.Saidi@ARM.com if (checker) { 8517405SAli.Saidi@ARM.com tc->pcStateNoRecord(pc); 8527749SAli.Saidi@ARM.com } else { 8537749SAli.Saidi@ARM.com tc->pcState(pc); 8547749SAli.Saidi@ARM.com } 8557749SAli.Saidi@ARM.com } else { 8567749SAli.Saidi@ARM.com#ifndef NDEBUG 8577614Sminkyu.jeong@arm.com if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 8587614Sminkyu.jeong@arm.com if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 8597720Sgblack@eecs.umich.edu warn("Unimplemented system register %s write with %#x.\n", 8607720Sgblack@eecs.umich.edu miscRegName[misc_reg], val); 8617720Sgblack@eecs.umich.edu else 8628887Sgeoffrey.blake@arm.com panic("Unimplemented system register %s write with %#x.\n", 8638887Sgeoffrey.blake@arm.com miscRegName[misc_reg], val); 8648887Sgeoffrey.blake@arm.com } 8658887Sgeoffrey.blake@arm.com#endif 8668887Sgeoffrey.blake@arm.com switch (unflattenMiscReg(misc_reg)) { 8678887Sgeoffrey.blake@arm.com case MISCREG_CPACR: 8688887Sgeoffrey.blake@arm.com { 8698887Sgeoffrey.blake@arm.com 8708887Sgeoffrey.blake@arm.com const uint32_t ones = (uint32_t)(-1); 8717408Sgblack@eecs.umich.edu CPACR cpacrMask = 0; 87210037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 87310037SARM gem5 Developers // be writable 87410037SARM gem5 Developers cpacrMask.cp10 = ones; 87510037SARM gem5 Developers cpacrMask.cp11 = ones; 87610037SARM gem5 Developers cpacrMask.asedis = ones; 87710037SARM gem5 Developers 87810037SARM gem5 Developers // Security Extensions may limit the writability of CPACR 87910037SARM gem5 Developers if (haveSecurity) { 88010037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 88110037SARM gem5 Developers CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 88210037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON)) { 8837408Sgblack@eecs.umich.edu NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 8847408Sgblack@eecs.umich.edu // NB: Skipping the full loop, here 8858206SWilliam.Wang@arm.com if (!nsacr.cp10) cpacrMask.cp10 = 0; 8868206SWilliam.Wang@arm.com if (!nsacr.cp11) cpacrMask.cp11 = 0; 8878206SWilliam.Wang@arm.com } 8888206SWilliam.Wang@arm.com } 8898206SWilliam.Wang@arm.com 8908206SWilliam.Wang@arm.com MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 8918206SWilliam.Wang@arm.com newVal &= cpacrMask; 8928206SWilliam.Wang@arm.com newVal |= old_val & ~cpacrMask; 89310037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 89410037SARM gem5 Developers miscRegName[misc_reg], newVal); 89510037SARM gem5 Developers } 89610037SARM gem5 Developers break; 89710037SARM gem5 Developers case MISCREG_CPACR_EL1: 89810037SARM gem5 Developers { 89910037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 90010037SARM gem5 Developers CPACR cpacrMask = 0; 90110037SARM gem5 Developers cpacrMask.tta = ones; 90210037SARM gem5 Developers cpacrMask.fpen = ones; 90310037SARM gem5 Developers newVal &= cpacrMask; 90410037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 90510037SARM gem5 Developers miscRegName[misc_reg], newVal); 90610037SARM gem5 Developers } 9078206SWilliam.Wang@arm.com break; 90810037SARM gem5 Developers case MISCREG_CPTR_EL2: 90910037SARM gem5 Developers { 91010037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 91110037SARM gem5 Developers CPTR cptrMask = 0; 91210037SARM gem5 Developers cptrMask.tcpac = ones; 91310037SARM gem5 Developers cptrMask.tta = ones; 91410037SARM gem5 Developers cptrMask.tfp = ones; 91510037SARM gem5 Developers newVal &= cptrMask; 91610037SARM gem5 Developers cptrMask = 0; 91710037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 91810037SARM gem5 Developers cptrMask.res1_9_0_el2 = ones; 91910037SARM gem5 Developers newVal |= cptrMask; 92010037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 92110037SARM gem5 Developers miscRegName[misc_reg], newVal); 92210037SARM gem5 Developers } 92310037SARM gem5 Developers break; 92410037SARM gem5 Developers case MISCREG_CPTR_EL3: 92510037SARM gem5 Developers { 92610037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 92710037SARM gem5 Developers CPTR cptrMask = 0; 92810037SARM gem5 Developers cptrMask.tcpac = ones; 92910037SARM gem5 Developers cptrMask.tta = ones; 93010037SARM gem5 Developers cptrMask.tfp = ones; 93110037SARM gem5 Developers newVal &= cptrMask; 93210037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 93310037SARM gem5 Developers miscRegName[misc_reg], newVal); 93410037SARM gem5 Developers } 93510037SARM gem5 Developers break; 93610037SARM gem5 Developers case MISCREG_CSSELR: 93710037SARM gem5 Developers warn_once("The csselr register isn't implemented.\n"); 93810037SARM gem5 Developers return; 93910037SARM gem5 Developers 94010037SARM gem5 Developers case MISCREG_DC_ZVA_Xt: 94110037SARM gem5 Developers warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 94210037SARM gem5 Developers return; 94310037SARM gem5 Developers 94410037SARM gem5 Developers case MISCREG_FPSCR: 94510037SARM gem5 Developers { 94610037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 94710037SARM gem5 Developers FPSCR fpscrMask = 0; 9488206SWilliam.Wang@arm.com fpscrMask.ioc = ones; 9498206SWilliam.Wang@arm.com fpscrMask.dzc = ones; 9507408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 9517408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 9527408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 9537731SAli.Saidi@ARM.com fpscrMask.idc = ones; 9548206SWilliam.Wang@arm.com fpscrMask.ioe = ones; 95510037SARM gem5 Developers fpscrMask.dze = ones; 95610037SARM gem5 Developers fpscrMask.ofe = ones; 95710037SARM gem5 Developers fpscrMask.ufe = ones; 95810037SARM gem5 Developers fpscrMask.ixe = ones; 95910037SARM gem5 Developers fpscrMask.ide = ones; 9607408Sgblack@eecs.umich.edu fpscrMask.len = ones; 9617408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 9627408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 9637408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 9647408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 9657408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 9667408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 9677408Sgblack@eecs.umich.edu fpscrMask.v = ones; 9687408Sgblack@eecs.umich.edu fpscrMask.c = ones; 9697408Sgblack@eecs.umich.edu fpscrMask.z = ones; 97010037SARM gem5 Developers fpscrMask.n = ones; 97110037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 97210037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 97310037SARM gem5 Developers ~(uint32_t)fpscrMask); 97410037SARM gem5 Developers tc->getDecoderPtr()->setContext(newVal); 97510037SARM gem5 Developers } 9767408Sgblack@eecs.umich.edu break; 9777408Sgblack@eecs.umich.edu case MISCREG_FPSR: 9787408Sgblack@eecs.umich.edu { 9797408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 9807408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 9817408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 9827408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 9837408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 9847408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 9857408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 9867408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 9877408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 98810037SARM gem5 Developers fpscrMask.v = ones; 98910037SARM gem5 Developers fpscrMask.c = ones; 9909377Sgblack@eecs.umich.edu fpscrMask.z = ones; 9917408Sgblack@eecs.umich.edu fpscrMask.n = ones; 9927408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 99310037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 99410037SARM gem5 Developers ~(uint32_t)fpscrMask); 99510037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 99610037SARM gem5 Developers } 99710037SARM gem5 Developers break; 99810037SARM gem5 Developers case MISCREG_FPCR: 99910037SARM gem5 Developers { 100010037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 100110037SARM gem5 Developers FPSCR fpscrMask = 0; 100210037SARM gem5 Developers fpscrMask.ioe = ones; 100310037SARM gem5 Developers fpscrMask.dze = ones; 100410037SARM gem5 Developers fpscrMask.ofe = ones; 100510037SARM gem5 Developers fpscrMask.ufe = ones; 100610037SARM gem5 Developers fpscrMask.ixe = ones; 100710037SARM gem5 Developers fpscrMask.ide = ones; 100810037SARM gem5 Developers fpscrMask.len = ones; 100910037SARM gem5 Developers fpscrMask.stride = ones; 101010037SARM gem5 Developers fpscrMask.rMode = ones; 101110037SARM gem5 Developers fpscrMask.fz = ones; 101210037SARM gem5 Developers fpscrMask.dn = ones; 101310037SARM gem5 Developers fpscrMask.ahp = ones; 101410037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 101510037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 101610037SARM gem5 Developers ~(uint32_t)fpscrMask); 101710037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 101810037SARM gem5 Developers } 101910037SARM gem5 Developers break; 102010037SARM gem5 Developers case MISCREG_CPSR_Q: 102110037SARM gem5 Developers { 102210037SARM gem5 Developers assert(!(newVal & ~CpsrMaskQ)); 102310037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 102410037SARM gem5 Developers misc_reg = MISCREG_CPSR; 102510037SARM gem5 Developers } 102610037SARM gem5 Developers break; 102710037SARM gem5 Developers case MISCREG_FPSCR_QC: 102810037SARM gem5 Developers { 102910037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 103010037SARM gem5 Developers (newVal & FpscrQcMask); 103110037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 103210037SARM gem5 Developers } 103310037SARM gem5 Developers break; 103410037SARM gem5 Developers case MISCREG_FPSCR_EXC: 103510037SARM gem5 Developers { 10368302SAli.Saidi@ARM.com newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 10378302SAli.Saidi@ARM.com (newVal & FpscrExcMask); 10388302SAli.Saidi@ARM.com misc_reg = MISCREG_FPSCR; 103910037SARM gem5 Developers } 10408302SAli.Saidi@ARM.com break; 10418302SAli.Saidi@ARM.com case MISCREG_FPEXC: 10428302SAli.Saidi@ARM.com { 10437783SGiacomo.Gabrielli@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 10447783SGiacomo.Gabrielli@arm.com // bit 29 - valid only if fpexc[31] is 0 104510037SARM gem5 Developers const uint32_t fpexcMask = 0x60000000; 104610037SARM gem5 Developers newVal = (newVal & fpexcMask) | 10477783SGiacomo.Gabrielli@arm.com (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 10487783SGiacomo.Gabrielli@arm.com } 10497783SGiacomo.Gabrielli@arm.com break; 10507783SGiacomo.Gabrielli@arm.com case MISCREG_HCR: 10517783SGiacomo.Gabrielli@arm.com { 105210037SARM gem5 Developers if (!haveVirtualization) 105310037SARM gem5 Developers return; 10547783SGiacomo.Gabrielli@arm.com } 10557783SGiacomo.Gabrielli@arm.com break; 10567783SGiacomo.Gabrielli@arm.com case MISCREG_IFSR: 10577408Sgblack@eecs.umich.edu { 10587408Sgblack@eecs.umich.edu // ARM ARM (ARM DDI 0406C.b) B4.1.96 10598206SWilliam.Wang@arm.com const uint32_t ifsrMask = 10608206SWilliam.Wang@arm.com mask(31, 13) | mask(11, 11) | mask(8, 6); 10617408Sgblack@eecs.umich.edu newVal = newVal & ~ifsrMask; 10627408Sgblack@eecs.umich.edu } 106310037SARM gem5 Developers break; 10647408Sgblack@eecs.umich.edu case MISCREG_DFSR: 10657408Sgblack@eecs.umich.edu { 106610037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.52 106710037SARM gem5 Developers const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 106810037SARM gem5 Developers newVal = newVal & ~dfsrMask; 106910037SARM gem5 Developers } 107010037SARM gem5 Developers break; 107110037SARM gem5 Developers case MISCREG_AMAIR0: 107210037SARM gem5 Developers case MISCREG_AMAIR1: 107310037SARM gem5 Developers { 107410037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 107510037SARM gem5 Developers // Valid only with LPAE 107610037SARM gem5 Developers if (!haveLPAE) 107710037SARM gem5 Developers return; 107810037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 107910037SARM gem5 Developers } 108010037SARM gem5 Developers break; 108110037SARM gem5 Developers case MISCREG_SCR: 108210037SARM gem5 Developers tc->getITBPtr()->invalidateMiscReg(); 108310037SARM gem5 Developers tc->getDTBPtr()->invalidateMiscReg(); 108410037SARM gem5 Developers break; 108510037SARM gem5 Developers case MISCREG_SCTLR: 108610037SARM gem5 Developers { 108710037SARM gem5 Developers DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 108810037SARM gem5 Developers MiscRegIndex sctlr_idx; 108910037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 109010037SARM gem5 Developers if (haveSecurity && !scr.ns) { 109110037SARM gem5 Developers sctlr_idx = MISCREG_SCTLR_S; 109210037SARM gem5 Developers } else { 109310037SARM gem5 Developers sctlr_idx = MISCREG_SCTLR_NS; 109410037SARM gem5 Developers // The FI field (bit 21) is common between S/NS versions 109510037SARM gem5 Developers // of the register, we store this in the secure copy of 109610037SARM gem5 Developers // the reg 109710037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21); 109810037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21); 109910037SARM gem5 Developers } 110010037SARM gem5 Developers SCTLR sctlr = miscRegs[sctlr_idx]; 11017408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 11027408Sgblack@eecs.umich.edu new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 11037408Sgblack@eecs.umich.edu miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 110410037SARM gem5 Developers tc->getITBPtr()->invalidateMiscReg(); 110511769SCurtis.Dunham@arm.com tc->getDTBPtr()->invalidateMiscReg(); 110611769SCurtis.Dunham@arm.com 110710037SARM gem5 Developers if (new_sctlr.c) 11087408Sgblack@eecs.umich.edu updateBootUncacheable(sctlr_idx, tc); 110910037SARM gem5 Developers return; 111010037SARM gem5 Developers } 11117749SAli.Saidi@ARM.com case MISCREG_MIDR: 11127749SAli.Saidi@ARM.com case MISCREG_ID_PFR0: 11137408Sgblack@eecs.umich.edu case MISCREG_ID_PFR1: 11149385SAndreas.Sandberg@arm.com case MISCREG_ID_DFR0: 11159385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR0: 11169385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR1: 111710461SAndreas.Sandberg@ARM.com case MISCREG_ID_MMFR2: 11189385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR3: 11199385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR0: 11209385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR1: 11219385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR2: 11229385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR3: 11239385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR4: 11249385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR5: 11259385SAndreas.Sandberg@arm.com 11269385SAndreas.Sandberg@arm.com case MISCREG_MPIDR: 11279385SAndreas.Sandberg@arm.com case MISCREG_FPSID: 11289385SAndreas.Sandberg@arm.com case MISCREG_TLBTR: 11299385SAndreas.Sandberg@arm.com case MISCREG_MVFR0: 11309385SAndreas.Sandberg@arm.com case MISCREG_MVFR1: 11317408Sgblack@eecs.umich.edu 11327408Sgblack@eecs.umich.edu case MISCREG_ID_AA64AFR0_EL1: 11337408Sgblack@eecs.umich.edu case MISCREG_ID_AA64AFR1_EL1: 113410037SARM gem5 Developers case MISCREG_ID_AA64DFR0_EL1: 113510037SARM gem5 Developers case MISCREG_ID_AA64DFR1_EL1: 113610037SARM gem5 Developers case MISCREG_ID_AA64ISAR0_EL1: 113710037SARM gem5 Developers case MISCREG_ID_AA64ISAR1_EL1: 113810037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 113910037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 114010037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 114110037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 114210037SARM gem5 Developers // ID registers are constants. 114310037SARM gem5 Developers return; 114410037SARM gem5 Developers 11459385SAndreas.Sandberg@arm.com // TLBI all entries, EL0&1 inner sharable (ignored) 11467408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 11479385SAndreas.Sandberg@arm.com case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 114810037SARM gem5 Developers assert32(tc); 11497408Sgblack@eecs.umich.edu target_el = 1; // el 0 and 1 are handled together 115010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 115110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 115210037SARM gem5 Developers sys = tc->getSystemPtr(); 115310037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 115410037SARM gem5 Developers oc = sys->getThreadContext(x); 11558284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 11568284SAli.Saidi@ARM.com oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 11578284SAli.Saidi@ARM.com oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 11588284SAli.Saidi@ARM.com 115910037SARM gem5 Developers // If CheckerCPU is connected, need to notify it of a flush 116010037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 11618887Sgeoffrey.blake@arm.com if (checker) { 11628887Sgeoffrey.blake@arm.com checker->getITBPtr()->flushAllSecurity(secure_lookup, 11638887Sgeoffrey.blake@arm.com target_el); 11648733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushAllSecurity(secure_lookup, 116510037SARM gem5 Developers target_el); 116610037SARM gem5 Developers } 116710037SARM gem5 Developers } 116810037SARM gem5 Developers return; 11698733Sgeoffrey.blake@arm.com // TLBI all entries, EL0&1, instruction side 11708284SAli.Saidi@ARM.com case MISCREG_ITLBIALL: 11717408Sgblack@eecs.umich.edu assert32(tc); 117210037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 11737408Sgblack@eecs.umich.edu scr = readMiscReg(MISCREG_SCR, tc); 117410037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 117510037SARM gem5 Developers tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 117610037SARM gem5 Developers return; 117710037SARM gem5 Developers // TLBI all entries, EL0&1, data side 117810037SARM gem5 Developers case MISCREG_DTLBIALL: 11797408Sgblack@eecs.umich.edu assert32(tc); 118010037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 11817408Sgblack@eecs.umich.edu scr = readMiscReg(MISCREG_SCR, tc); 118210037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 118310037SARM gem5 Developers tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 118410037SARM gem5 Developers return; 118510037SARM gem5 Developers // TLBI based on VA, EL0&1 inner sharable (ignored) 118610037SARM gem5 Developers case MISCREG_TLBIMVAIS: 11877408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 118810037SARM gem5 Developers assert32(tc); 11897408Sgblack@eecs.umich.edu target_el = 1; // el 0 and 1 are handled together 11907408Sgblack@eecs.umich.edu scr = readMiscReg(MISCREG_SCR, tc); 119110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 119210037SARM gem5 Developers sys = tc->getSystemPtr(); 119310037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 119410037SARM gem5 Developers oc = sys->getThreadContext(x); 11958284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 11968284SAli.Saidi@ARM.com oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 11978284SAli.Saidi@ARM.com bits(newVal, 7,0), 11988284SAli.Saidi@ARM.com secure_lookup, target_el); 11998284SAli.Saidi@ARM.com oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 120010037SARM gem5 Developers bits(newVal, 7,0), 120110037SARM gem5 Developers secure_lookup, target_el); 12028284SAli.Saidi@ARM.com 120310037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 120410037SARM gem5 Developers if (checker) { 12058887Sgeoffrey.blake@arm.com checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 12068887Sgeoffrey.blake@arm.com bits(newVal, 7,0), secure_lookup, target_el); 12078733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 12088733Sgeoffrey.blake@arm.com bits(newVal, 7,0), secure_lookup, target_el); 120910037SARM gem5 Developers } 12108733Sgeoffrey.blake@arm.com } 121110037SARM gem5 Developers return; 12128733Sgeoffrey.blake@arm.com // TLBI by ASID, EL0&1, inner sharable 12138284SAli.Saidi@ARM.com case MISCREG_TLBIASIDIS: 12147408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 121510037SARM gem5 Developers assert32(tc); 12167408Sgblack@eecs.umich.edu target_el = 1; // el 0 and 1 are handled together 12177408Sgblack@eecs.umich.edu scr = readMiscReg(MISCREG_SCR, tc); 121810037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 121910037SARM gem5 Developers sys = tc->getSystemPtr(); 122010037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 122110037SARM gem5 Developers oc = sys->getThreadContext(x); 12228284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 12238284SAli.Saidi@ARM.com oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 12248284SAli.Saidi@ARM.com secure_lookup, target_el); 12258284SAli.Saidi@ARM.com oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 122610037SARM gem5 Developers secure_lookup, target_el); 122710037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 122810037SARM gem5 Developers if (checker) { 122910037SARM gem5 Developers checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 12308887Sgeoffrey.blake@arm.com secure_lookup, target_el); 12318733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 123210037SARM gem5 Developers secure_lookup, target_el); 123310037SARM gem5 Developers } 123410037SARM gem5 Developers } 123510037SARM gem5 Developers return; 12368733Sgeoffrey.blake@arm.com // TLBI by address, EL0&1, inner sharable (ignored) 12378284SAli.Saidi@ARM.com case MISCREG_TLBIMVAAIS: 12387408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 123910037SARM gem5 Developers assert32(tc); 12407408Sgblack@eecs.umich.edu target_el = 1; // el 0 and 1 are handled together 12417408Sgblack@eecs.umich.edu scr = readMiscReg(MISCREG_SCR, tc); 124210037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 124310037SARM gem5 Developers hyp = 0; 124410037SARM gem5 Developers tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 124510037SARM gem5 Developers return; 124610037SARM gem5 Developers // TLBI by address, EL2, hypervisor mode 124710037SARM gem5 Developers case MISCREG_TLBIMVAH: 124810037SARM gem5 Developers case MISCREG_TLBIMVAHIS: 124910037SARM gem5 Developers assert32(tc); 125010037SARM gem5 Developers target_el = 1; // aarch32, use hyp bit 125110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 125210037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 125310037SARM gem5 Developers hyp = 1; 125410037SARM gem5 Developers tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 125510037SARM gem5 Developers return; 125610037SARM gem5 Developers // TLBI by address and asid, EL0&1, instruction side only 125710037SARM gem5 Developers case MISCREG_ITLBIMVA: 125810037SARM gem5 Developers assert32(tc); 125910037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 126010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 126110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 126210037SARM gem5 Developers tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 126310037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 126410037SARM gem5 Developers return; 126510037SARM gem5 Developers // TLBI by address and asid, EL0&1, data side only 126610037SARM gem5 Developers case MISCREG_DTLBIMVA: 126710037SARM gem5 Developers assert32(tc); 126810037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 126910037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 127010037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 127110037SARM gem5 Developers tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 127210037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 127310037SARM gem5 Developers return; 127410037SARM gem5 Developers // TLBI by ASID, EL0&1, instrution side only 127510037SARM gem5 Developers case MISCREG_ITLBIASID: 127610037SARM gem5 Developers assert32(tc); 127710037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 127810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 127910037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 128010037SARM gem5 Developers tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 128110037SARM gem5 Developers target_el); 128210037SARM gem5 Developers return; 128310037SARM gem5 Developers // TLBI by ASID EL0&1 data size only 128410037SARM gem5 Developers case MISCREG_DTLBIASID: 128510037SARM gem5 Developers assert32(tc); 128610037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 128710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 128810037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 128910037SARM gem5 Developers tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 129010037SARM gem5 Developers target_el); 129110037SARM gem5 Developers return; 129210037SARM gem5 Developers // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 129310037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 129410037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 129510037SARM gem5 Developers assert32(tc); 129610037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 129710037SARM gem5 Developers hyp = 0; 129810037SARM gem5 Developers tlbiALLN(tc, hyp, target_el); 129910037SARM gem5 Developers return; 130010037SARM gem5 Developers // TLBI all entries, EL2, hyp, 130110037SARM gem5 Developers case MISCREG_TLBIALLH: 130210037SARM gem5 Developers case MISCREG_TLBIALLHIS: 130310037SARM gem5 Developers assert32(tc); 130410037SARM gem5 Developers target_el = 1; // aarch32, use hyp bit 130510037SARM gem5 Developers hyp = 1; 130610037SARM gem5 Developers tlbiALLN(tc, hyp, target_el); 130710037SARM gem5 Developers return; 130810037SARM gem5 Developers // AArch64 TLBI: invalidate all entries EL3 130910037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 131010037SARM gem5 Developers case MISCREG_TLBI_ALLE3: 131110037SARM gem5 Developers assert64(tc); 131210037SARM gem5 Developers target_el = 3; 131310037SARM gem5 Developers secure_lookup = true; 131410037SARM gem5 Developers tlbiALL(tc, secure_lookup, target_el); 131510037SARM gem5 Developers return; 131610037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 131710037SARM gem5 Developers // case MISCREG_TLBI_ALLE2IS: 131810037SARM gem5 Developers // case MISCREG_TLBI_ALLE2: 131910037SARM gem5 Developers // TLBI all entries, EL0&1 132010037SARM gem5 Developers case MISCREG_TLBI_ALLE1IS: 132110037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 132210037SARM gem5 Developers // AArch64 TLBI: invalidate all entries, stage 1, current VMID 132310037SARM gem5 Developers case MISCREG_TLBI_VMALLE1IS: 132410037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 132510037SARM gem5 Developers // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 132610037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1IS: 132710037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 132810037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 132910037SARM gem5 Developers assert64(tc); 133010037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 133110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 133210037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 133310037SARM gem5 Developers tlbiALL(tc, secure_lookup, target_el); 133410037SARM gem5 Developers return; 133510037SARM gem5 Developers // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 133610037SARM gem5 Developers // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 133710037SARM gem5 Developers // from the last level of translation table walks 133810037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 133910037SARM gem5 Developers // TLBI all entries, EL0&1 134010037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 134110037SARM gem5 Developers case MISCREG_TLBI_VAE3_Xt: 134210037SARM gem5 Developers // TLBI by VA, EL3 regime stage 1, last level walk 134310037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 134410037SARM gem5 Developers case MISCREG_TLBI_VALE3_Xt: 134510037SARM gem5 Developers assert64(tc); 134610037SARM gem5 Developers target_el = 3; 134710037SARM gem5 Developers asid = 0xbeef; // does not matter, tlbi is global 134810037SARM gem5 Developers secure_lookup = true; 134910037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 135010037SARM gem5 Developers return; 135110037SARM gem5 Developers // TLBI by VA, EL2 135210037SARM gem5 Developers case MISCREG_TLBI_VAE2IS_Xt: 135310037SARM gem5 Developers case MISCREG_TLBI_VAE2_Xt: 135410037SARM gem5 Developers // TLBI by VA, EL2, stage1 last level walk 135510037SARM gem5 Developers case MISCREG_TLBI_VALE2IS_Xt: 135610037SARM gem5 Developers case MISCREG_TLBI_VALE2_Xt: 135710037SARM gem5 Developers assert64(tc); 135810037SARM gem5 Developers target_el = 2; 135910037SARM gem5 Developers asid = 0xbeef; // does not matter, tlbi is global 136010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 136110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 136210037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 136310037SARM gem5 Developers return; 136410037SARM gem5 Developers // TLBI by VA EL1 & 0, stage1, ASID, current VMID 136510037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 136610037SARM gem5 Developers case MISCREG_TLBI_VAE1_Xt: 136710037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 136810037SARM gem5 Developers case MISCREG_TLBI_VALE1_Xt: 136910037SARM gem5 Developers assert64(tc); 137010037SARM gem5 Developers asid = bits(newVal, 63, 48); 137110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 137210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 137310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 137410037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 137510037SARM gem5 Developers return; 137610037SARM gem5 Developers // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 137710037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 137810037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 137910037SARM gem5 Developers case MISCREG_TLBI_ASIDE1_Xt: 138010037SARM gem5 Developers assert64(tc); 138110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 138210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 138310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 138410037SARM gem5 Developers sys = tc->getSystemPtr(); 138510037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 138610037SARM gem5 Developers oc = sys->getThreadContext(x); 13878284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 13888284SAli.Saidi@ARM.com asid = bits(newVal, 63, 48); 13898284SAli.Saidi@ARM.com if (haveLargeAsid64) 13908284SAli.Saidi@ARM.com asid &= mask(8); 139110037SARM gem5 Developers oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 139210709SAndreas.Sandberg@ARM.com oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 139310037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 139410037SARM gem5 Developers if (checker) { 139510037SARM gem5 Developers checker->getITBPtr()->flushAsid(asid, 139610037SARM gem5 Developers secure_lookup, target_el); 139710037SARM gem5 Developers checker->getDTBPtr()->flushAsid(asid, 139810037SARM gem5 Developers secure_lookup, target_el); 139910037SARM gem5 Developers } 140010037SARM gem5 Developers } 140110037SARM gem5 Developers return; 140210037SARM gem5 Developers // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 140310037SARM gem5 Developers // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 140410037SARM gem5 Developers // entries from the last level of translation table walks 140510037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 140610037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 140710037SARM gem5 Developers case MISCREG_TLBI_VAAE1_Xt: 140810037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 140910037SARM gem5 Developers case MISCREG_TLBI_VAALE1_Xt: 141010037SARM gem5 Developers assert64(tc); 141110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 141210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 141310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 141410037SARM gem5 Developers sys = tc->getSystemPtr(); 141510037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 141610037SARM gem5 Developers // @todo: extra controls on TLBI broadcast? 141710037SARM gem5 Developers oc = sys->getThreadContext(x); 141810037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 141910037SARM gem5 Developers Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 142010037SARM gem5 Developers oc->getITBPtr()->flushMva(va, 142110037SARM gem5 Developers secure_lookup, false, target_el); 142210037SARM gem5 Developers oc->getDTBPtr()->flushMva(va, 142310037SARM gem5 Developers secure_lookup, false, target_el); 142410037SARM gem5 Developers 142510037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 142610037SARM gem5 Developers if (checker) { 14278887Sgeoffrey.blake@arm.com checker->getITBPtr()->flushMva(va, 14288887Sgeoffrey.blake@arm.com secure_lookup, false, target_el); 14298733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushMva(va, 143010037SARM gem5 Developers secure_lookup, false, target_el); 143110037SARM gem5 Developers } 143210037SARM gem5 Developers } 143310037SARM gem5 Developers return; 14348733Sgeoffrey.blake@arm.com // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 14358284SAli.Saidi@ARM.com case MISCREG_TLBI_IPAS2LE1IS_Xt: 14367408Sgblack@eecs.umich.edu case MISCREG_TLBI_IPAS2LE1_Xt: 143710037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1IS_Xt: 143810037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1_Xt: 143910037SARM gem5 Developers assert64(tc); 144010037SARM gem5 Developers // @todo: implement these as part of Virtualization 144110037SARM gem5 Developers warn("Not doing anything for write of miscreg ITLB_IPAS2\n"); 144210037SARM gem5 Developers return; 144311584SDylan.Johnson@ARM.com case MISCREG_ACTLR: 144411584SDylan.Johnson@ARM.com warn("Not doing anything for write of miscreg ACTLR\n"); 144511584SDylan.Johnson@ARM.com break; 144611584SDylan.Johnson@ARM.com 144711584SDylan.Johnson@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 144811584SDylan.Johnson@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 144911584SDylan.Johnson@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 145011584SDylan.Johnson@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 145111584SDylan.Johnson@ARM.com pmu->setMiscReg(misc_reg, newVal); 145211584SDylan.Johnson@ARM.com break; 145311584SDylan.Johnson@ARM.com 145411584SDylan.Johnson@ARM.com 145511584SDylan.Johnson@ARM.com case MISCREG_HSTR: // TJDBX, now redifined to be RES0 145611584SDylan.Johnson@ARM.com { 145711584SDylan.Johnson@ARM.com HSTR hstrMask = 0; 145811584SDylan.Johnson@ARM.com hstrMask.tjdbx = 1; 145911584SDylan.Johnson@ARM.com newVal &= ~((uint32_t) hstrMask); 146011584SDylan.Johnson@ARM.com break; 146111584SDylan.Johnson@ARM.com } 146211584SDylan.Johnson@ARM.com case MISCREG_HCPTR: 146311584SDylan.Johnson@ARM.com { 14647405SAli.Saidi@ARM.com // If a CP bit in NSACR is 0 then the corresponding bit in 14657583SAli.Saidi@arm.com // HCPTR is RAO/WI. Same applies to NSASEDIS 14667583SAli.Saidi@arm.com secure_lookup = haveSecurity && 14677583SAli.Saidi@arm.com inSecureState(readMiscRegNoEffect(MISCREG_SCR), 146810461SAndreas.Sandberg@ARM.com readMiscRegNoEffect(MISCREG_CPSR)); 146910461SAndreas.Sandberg@ARM.com if (!secure_lookup) { 147010461SAndreas.Sandberg@ARM.com MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 147110461SAndreas.Sandberg@ARM.com MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 147210461SAndreas.Sandberg@ARM.com newVal = (newVal & ~mask) | (oldValue & mask); 147310461SAndreas.Sandberg@ARM.com } 14747583SAli.Saidi@arm.com break; 147510461SAndreas.Sandberg@ARM.com } 147610461SAndreas.Sandberg@ARM.com case MISCREG_HDFAR: // alias for secure DFAR 147710037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 147810037SARM gem5 Developers break; 147910037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 148010037SARM gem5 Developers misc_reg = MISCREG_IFAR_S; 148110037SARM gem5 Developers break; 148210037SARM gem5 Developers case MISCREG_ATS1CPR: 148310037SARM gem5 Developers case MISCREG_ATS1CPW: 148410037SARM gem5 Developers case MISCREG_ATS1CUR: 148510037SARM gem5 Developers case MISCREG_ATS1CUW: 148610037SARM gem5 Developers case MISCREG_ATS12NSOPR: 148710037SARM gem5 Developers case MISCREG_ATS12NSOPW: 148810037SARM gem5 Developers case MISCREG_ATS12NSOUR: 148910037SARM gem5 Developers case MISCREG_ATS12NSOUW: 149010037SARM gem5 Developers case MISCREG_ATS1HR: 149110037SARM gem5 Developers case MISCREG_ATS1HW: 149210037SARM gem5 Developers { 149310037SARM gem5 Developers unsigned flags = 0; 149410037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 149510037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 149610037SARM gem5 Developers Fault fault; 149710037SARM gem5 Developers switch(misc_reg) { 149810037SARM gem5 Developers case MISCREG_ATS1CPR: 149910037SARM gem5 Developers flags = TLB::MustBeOne; 150010037SARM gem5 Developers tranType = TLB::S1CTran; 150110037SARM gem5 Developers mode = BaseTLB::Read; 150210037SARM gem5 Developers break; 150310037SARM gem5 Developers case MISCREG_ATS1CPW: 150410037SARM gem5 Developers flags = TLB::MustBeOne; 150510037SARM gem5 Developers tranType = TLB::S1CTran; 150610037SARM gem5 Developers mode = BaseTLB::Write; 150710037SARM gem5 Developers break; 150810037SARM gem5 Developers case MISCREG_ATS1CUR: 150910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 151010037SARM gem5 Developers tranType = TLB::S1CTran; 151110037SARM gem5 Developers mode = BaseTLB::Read; 151210037SARM gem5 Developers break; 151310037SARM gem5 Developers case MISCREG_ATS1CUW: 15147436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 151511608Snikos.nikoleris@arm.com tranType = TLB::S1CTran; 151610037SARM gem5 Developers mode = BaseTLB::Write; 151710037SARM gem5 Developers break; 15187436Sdam.sunwoo@arm.com case MISCREG_ATS12NSOPR: 15197436Sdam.sunwoo@arm.com if (!haveSecurity) 152010037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 152110037SARM gem5 Developers flags = TLB::MustBeOne; 152210037SARM gem5 Developers tranType = TLB::S1S2NsTran; 152310037SARM gem5 Developers mode = BaseTLB::Read; 152410037SARM gem5 Developers break; 152510037SARM gem5 Developers case MISCREG_ATS12NSOPW: 152610037SARM gem5 Developers if (!haveSecurity) 152710037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPW"); 152810037SARM gem5 Developers flags = TLB::MustBeOne; 152910037SARM gem5 Developers tranType = TLB::S1S2NsTran; 153010037SARM gem5 Developers mode = BaseTLB::Write; 153110037SARM gem5 Developers break; 153210037SARM gem5 Developers case MISCREG_ATS12NSOUR: 153310037SARM gem5 Developers if (!haveSecurity) 153410037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 153510037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 153610037SARM gem5 Developers tranType = TLB::S1S2NsTran; 153710037SARM gem5 Developers mode = BaseTLB::Read; 153810037SARM gem5 Developers break; 153910037SARM gem5 Developers case MISCREG_ATS12NSOUW: 154010037SARM gem5 Developers if (!haveSecurity) 154110037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 154210037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 154310037SARM gem5 Developers tranType = TLB::S1S2NsTran; 154410037SARM gem5 Developers mode = BaseTLB::Write; 154510037SARM gem5 Developers break; 154610037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 154710037SARM gem5 Developers flags = TLB::MustBeOne; 154810037SARM gem5 Developers tranType = TLB::HypMode; 154910037SARM gem5 Developers mode = BaseTLB::Read; 155010037SARM gem5 Developers break; 155110037SARM gem5 Developers case MISCREG_ATS1HW: 155210037SARM gem5 Developers flags = TLB::MustBeOne; 155310037SARM gem5 Developers tranType = TLB::HypMode; 155410037SARM gem5 Developers mode = BaseTLB::Write; 155510037SARM gem5 Developers break; 155610037SARM gem5 Developers } 155710037SARM gem5 Developers // If we're in timing mode then doing the translation in 155810037SARM gem5 Developers // functional mode then we're slightly distorting performance 155910037SARM gem5 Developers // results obtained from simulations. The translation should be 156010037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 156110037SARM gem5 Developers // can't be an atomic translation because that causes problems 156210037SARM gem5 Developers // with unexpected atomic snoop requests. 156310037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 156410037SARM gem5 Developers Request req(0, val, 1, flags, Request::funcMasterId, 156510037SARM gem5 Developers tc->pcState().pc(), tc->contextId(), 156610037SARM gem5 Developers tc->threadId()); 156710037SARM gem5 Developers fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 156810037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 156910037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 157010037SARM gem5 Developers 157110037SARM gem5 Developers MiscReg newVal; 157210037SARM gem5 Developers if (fault == NoFault) { 157310037SARM gem5 Developers Addr paddr = req.getPaddr(); 157410037SARM gem5 Developers if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 157510037SARM gem5 Developers ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 157610037SARM gem5 Developers newVal = (paddr & mask(39, 12)) | 157710037SARM gem5 Developers (tc->getDTBPtr()->getAttr()); 15787436Sdam.sunwoo@arm.com } else { 157910037SARM gem5 Developers newVal = (paddr & 0xfffff000) | 158010037SARM gem5 Developers (tc->getDTBPtr()->getAttr()); 158110037SARM gem5 Developers } 158210037SARM gem5 Developers DPRINTF(MiscRegs, 158310037SARM gem5 Developers "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 158410037SARM gem5 Developers val, newVal); 158510037SARM gem5 Developers } else { 158611560Sandreas.sandberg@arm.com ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 158711435Smitch.hayenga@arm.com // Set fault bit and FSR 158810653Sandreas.hansson@arm.com FSR fsr = armFault->getFsr(tc); 158910037SARM gem5 Developers 159010037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 159110037SARM gem5 Developers if (newVal) { 159210037SARM gem5 Developers // LPAE - rearange fault status 15937436Sdam.sunwoo@arm.com newVal |= ((fsr >> 0) & 0x3f) << 1; 159410653Sandreas.hansson@arm.com } else { 159510037SARM gem5 Developers // VMSA - rearange fault status 159610037SARM gem5 Developers newVal |= ((fsr >> 0) & 0xf) << 1; 159710037SARM gem5 Developers newVal |= ((fsr >> 10) & 0x1) << 5; 159810037SARM gem5 Developers newVal |= ((fsr >> 12) & 0x1) << 6; 159910037SARM gem5 Developers } 160010037SARM gem5 Developers newVal |= 0x1; // F bit 160110037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 160210037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 16037436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 16047436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 160510037SARM gem5 Developers val, fsr, newVal); 160610037SARM gem5 Developers } 160710037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 160810037SARM gem5 Developers return; 160910037SARM gem5 Developers } 161010037SARM gem5 Developers case MISCREG_TTBCR: 161110037SARM gem5 Developers { 161210037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 161310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 161410037SARM gem5 Developers TTBCR ttbcrMask = 0; 161510037SARM gem5 Developers TTBCR ttbcrNew = newVal; 161610037SARM gem5 Developers 161710037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 161810037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 161910037SARM gem5 Developers if (haveSecurity) { 162010037SARM gem5 Developers ttbcrMask.pd0 = ones; 162110037SARM gem5 Developers ttbcrMask.pd1 = ones; 162210037SARM gem5 Developers } 162310037SARM gem5 Developers ttbcrMask.epd0 = ones; 162410037SARM gem5 Developers ttbcrMask.irgn0 = ones; 162510037SARM gem5 Developers ttbcrMask.orgn0 = ones; 162610037SARM gem5 Developers ttbcrMask.sh0 = ones; 16277436Sdam.sunwoo@arm.com ttbcrMask.ps = ones; // T1SZ 162810037SARM gem5 Developers ttbcrMask.a1 = ones; 16297436Sdam.sunwoo@arm.com ttbcrMask.epd1 = ones; 16307436Sdam.sunwoo@arm.com ttbcrMask.irgn1 = ones; 163110037SARM gem5 Developers ttbcrMask.orgn1 = ones; 163210037SARM gem5 Developers ttbcrMask.sh1 = ones; 163310037SARM gem5 Developers if (haveLPAE) 163410037SARM gem5 Developers ttbcrMask.eae = ones; 163510037SARM gem5 Developers 163610037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 163710037SARM gem5 Developers newVal = newVal & ttbcrMask; 163810037SARM gem5 Developers } else { 163910037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 164010037SARM gem5 Developers } 164110037SARM gem5 Developers } 164210037SARM gem5 Developers case MISCREG_TTBR0: 164310037SARM gem5 Developers case MISCREG_TTBR1: 164410037SARM gem5 Developers { 164510037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 164610037SARM gem5 Developers if (haveLPAE) { 164710037SARM gem5 Developers if (ttbcr.eae) { 164810037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 164910037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 165010037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 165110037SARM gem5 Developers newVal = (newVal & (~ttbrMask)); 165210037SARM gem5 Developers } 165310037SARM gem5 Developers } 165410037SARM gem5 Developers } 165510037SARM gem5 Developers case MISCREG_SCTLR_EL1: 165610037SARM gem5 Developers { 165710037SARM gem5 Developers tc->getITBPtr()->invalidateMiscReg(); 165810037SARM gem5 Developers tc->getDTBPtr()->invalidateMiscReg(); 165910037SARM gem5 Developers SCTLR new_sctlr = newVal; 166010037SARM gem5 Developers setMiscRegNoEffect(misc_reg, newVal); 166110037SARM gem5 Developers if (new_sctlr.c) 166210037SARM gem5 Developers updateBootUncacheable(misc_reg, tc); 166310037SARM gem5 Developers return; 166410037SARM gem5 Developers } 166510037SARM gem5 Developers case MISCREG_CONTEXTIDR: 166610037SARM gem5 Developers case MISCREG_PRRR: 166710037SARM gem5 Developers case MISCREG_NMRR: 166810037SARM gem5 Developers case MISCREG_MAIR0: 166910037SARM gem5 Developers case MISCREG_MAIR1: 167010037SARM gem5 Developers case MISCREG_DACR: 167110037SARM gem5 Developers case MISCREG_VTTBR: 167210037SARM gem5 Developers case MISCREG_SCR_EL3: 167310037SARM gem5 Developers case MISCREG_TCR_EL1: 167410037SARM gem5 Developers case MISCREG_TCR_EL2: 167510037SARM gem5 Developers case MISCREG_TCR_EL3: 167610508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL2: 167710508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL3: 167810508SAli.Saidi@ARM.com case MISCREG_TTBR0_EL1: 167910508SAli.Saidi@ARM.com case MISCREG_TTBR1_EL1: 168010508SAli.Saidi@ARM.com case MISCREG_TTBR0_EL2: 168110508SAli.Saidi@ARM.com case MISCREG_TTBR0_EL3: 16827749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 16837749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 16847749SAli.Saidi@ARM.com break; 168510037SARM gem5 Developers case MISCREG_NZCV: 168610037SARM gem5 Developers { 16877749SAli.Saidi@ARM.com CPSR cpsr = val; 168810037SARM gem5 Developers 168910037SARM gem5 Developers tc->setCCReg(CCREG_NZ, cpsr.nz); 169011575SDylan.Johnson@ARM.com tc->setCCReg(CCREG_C, cpsr.c); 169110037SARM gem5 Developers tc->setCCReg(CCREG_V, cpsr.v); 169210037SARM gem5 Developers } 169310037SARM gem5 Developers break; 169410508SAli.Saidi@ARM.com case MISCREG_DAIF: 169510508SAli.Saidi@ARM.com { 169611573SDylan.Johnson@ARM.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 169710037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 169810037SARM gem5 Developers newVal = cpsr; 169910037SARM gem5 Developers misc_reg = MISCREG_CPSR; 170010037SARM gem5 Developers } 17017749SAli.Saidi@ARM.com break; 17027749SAli.Saidi@ARM.com case MISCREG_SP_EL0: 17037749SAli.Saidi@ARM.com tc->setIntReg(INTREG_SP0, newVal); 170410037SARM gem5 Developers break; 170510037SARM gem5 Developers case MISCREG_SP_EL1: 170610037SARM gem5 Developers tc->setIntReg(INTREG_SP1, newVal); 170710037SARM gem5 Developers break; 170810338SCurtis.Dunham@arm.com case MISCREG_SP_EL2: 170910338SCurtis.Dunham@arm.com tc->setIntReg(INTREG_SP2, newVal); 171010338SCurtis.Dunham@arm.com break; 171110037SARM gem5 Developers case MISCREG_SPSEL: 171210037SARM gem5 Developers { 171310037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 171410037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 171510037SARM gem5 Developers newVal = cpsr; 171610037SARM gem5 Developers misc_reg = MISCREG_CPSR; 171710037SARM gem5 Developers } 171810037SARM gem5 Developers break; 171910037SARM gem5 Developers case MISCREG_CURRENTEL: 172010037SARM gem5 Developers { 172110037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 172210037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 172310037SARM gem5 Developers newVal = cpsr; 172410037SARM gem5 Developers misc_reg = MISCREG_CPSR; 172510037SARM gem5 Developers } 172610037SARM gem5 Developers break; 172710037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 172810037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 172910037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 173010037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 173110037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 173210037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 173310037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 173410037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 173510037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 173610037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 173710037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 173810037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 173910037SARM gem5 Developers { 174010037SARM gem5 Developers RequestPtr req = new Request; 174110037SARM gem5 Developers unsigned flags = 0; 174210037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 174310037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 174410037SARM gem5 Developers Fault fault; 174510037SARM gem5 Developers switch(misc_reg) { 174610037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 174710037SARM gem5 Developers flags = TLB::MustBeOne; 174810037SARM gem5 Developers tranType = TLB::S1CTran; 174910037SARM gem5 Developers mode = BaseTLB::Read; 175010037SARM gem5 Developers break; 175110037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 175210037SARM gem5 Developers flags = TLB::MustBeOne; 175310037SARM gem5 Developers tranType = TLB::S1CTran; 175410037SARM gem5 Developers mode = BaseTLB::Write; 175510037SARM gem5 Developers break; 175610037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 175710037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 175810037SARM gem5 Developers tranType = TLB::S1CTran; 175910037SARM gem5 Developers mode = BaseTLB::Read; 176011608Snikos.nikoleris@arm.com break; 176110037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 176210037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 176310037SARM gem5 Developers tranType = TLB::S1CTran; 176410037SARM gem5 Developers mode = BaseTLB::Write; 176510037SARM gem5 Developers break; 176610037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 176711577SDylan.Johnson@ARM.com flags = TLB::MustBeOne; 176810037SARM gem5 Developers tranType = TLB::HypMode; 176910037SARM gem5 Developers mode = BaseTLB::Read; 177010037SARM gem5 Developers break; 177110037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 177211577SDylan.Johnson@ARM.com flags = TLB::MustBeOne; 177310037SARM gem5 Developers tranType = TLB::HypMode; 177410037SARM gem5 Developers mode = BaseTLB::Write; 177510037SARM gem5 Developers break; 177610037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 177711577SDylan.Johnson@ARM.com flags = TLB::MustBeOne | TLB::UserMode; 177810037SARM gem5 Developers tranType = TLB::S1S2NsTran; 177910037SARM gem5 Developers mode = BaseTLB::Read; 178010037SARM gem5 Developers break; 178110037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 178211577SDylan.Johnson@ARM.com flags = TLB::MustBeOne | TLB::UserMode; 178310037SARM gem5 Developers tranType = TLB::S1S2NsTran; 178410037SARM gem5 Developers mode = BaseTLB::Write; 178510037SARM gem5 Developers break; 178610037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 178711577SDylan.Johnson@ARM.com flags = TLB::MustBeOne; 178810037SARM gem5 Developers tranType = TLB::S1S2NsTran; 178910037SARM gem5 Developers mode = BaseTLB::Read; 179010037SARM gem5 Developers break; 179110037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 179211577SDylan.Johnson@ARM.com flags = TLB::MustBeOne; 179310037SARM gem5 Developers tranType = TLB::S1S2NsTran; 179410037SARM gem5 Developers mode = BaseTLB::Write; 179510037SARM gem5 Developers break; 179610037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 179711577SDylan.Johnson@ARM.com flags = TLB::MustBeOne; 179810037SARM gem5 Developers tranType = TLB::HypMode; // There is no TZ mode defined. 179910037SARM gem5 Developers mode = BaseTLB::Read; 180010037SARM gem5 Developers break; 180110037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 180211577SDylan.Johnson@ARM.com flags = TLB::MustBeOne; 180310037SARM gem5 Developers tranType = TLB::HypMode; // There is no TZ mode defined. 180410037SARM gem5 Developers mode = BaseTLB::Write; 180510037SARM gem5 Developers break; 180610037SARM gem5 Developers } 180711577SDylan.Johnson@ARM.com // If we're in timing mode then doing the translation in 180810037SARM gem5 Developers // functional mode then we're slightly distorting performance 180910037SARM gem5 Developers // results obtained from simulations. The translation should be 181010037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 181110037SARM gem5 Developers // can't be an atomic translation because that causes problems 181211577SDylan.Johnson@ARM.com // with unexpected atomic snoop requests. 181310037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 181410037SARM gem5 Developers req->setVirt(0, val, 1, flags, Request::funcMasterId, 181510037SARM gem5 Developers tc->pcState().pc()); 181610037SARM gem5 Developers req->setThreadContext(tc->contextId(), tc->threadId()); 181711577SDylan.Johnson@ARM.com fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 181810037SARM gem5 Developers tranType); 181910037SARM gem5 Developers 182010037SARM gem5 Developers MiscReg newVal; 182110037SARM gem5 Developers if (fault == NoFault) { 182211577SDylan.Johnson@ARM.com Addr paddr = req->getPaddr(); 182310037SARM gem5 Developers uint64_t attr = tc->getDTBPtr()->getAttr(); 182410037SARM gem5 Developers uint64_t attr1 = attr >> 56; 182510037SARM gem5 Developers if (!attr1 || attr1 ==0x44) { 182610037SARM gem5 Developers attr |= 0x100; 182710037SARM gem5 Developers attr &= ~ uint64_t(0x80); 182810037SARM gem5 Developers } 182910037SARM gem5 Developers newVal = (paddr & mask(47, 12)) | attr; 183010037SARM gem5 Developers DPRINTF(MiscRegs, 183110037SARM gem5 Developers "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 183210037SARM gem5 Developers val, newVal); 183311560Sandreas.sandberg@arm.com } else { 183410037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 183511435Smitch.hayenga@arm.com // Set fault bit and FSR 183610037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 183710037SARM gem5 Developers 183810037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 183910037SARM gem5 Developers // rearange fault status 184010037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 184110037SARM gem5 Developers newVal |= 0x1; // F bit 184210037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 184310037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 184410037SARM gem5 Developers DPRINTF(MiscRegs, 184510037SARM gem5 Developers "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 184610037SARM gem5 Developers val, fsr, newVal); 184710037SARM gem5 Developers } 184810037SARM gem5 Developers delete req; 184910037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 185010037SARM gem5 Developers return; 185110037SARM gem5 Developers } 185210037SARM gem5 Developers case MISCREG_SPSR_EL3: 185310037SARM gem5 Developers case MISCREG_SPSR_EL2: 185410037SARM gem5 Developers case MISCREG_SPSR_EL1: 185510037SARM gem5 Developers // Force bits 23:21 to 0 185610037SARM gem5 Developers newVal = val & ~(0x7 << 21); 185711577SDylan.Johnson@ARM.com break; 185811577SDylan.Johnson@ARM.com case MISCREG_L2CTLR: 185911577SDylan.Johnson@ARM.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 186011577SDylan.Johnson@ARM.com miscRegName[misc_reg], uint32_t(val)); 186111577SDylan.Johnson@ARM.com break; 186211577SDylan.Johnson@ARM.com 186311577SDylan.Johnson@ARM.com // Generic Timer registers 186411577SDylan.Johnson@ARM.com case MISCREG_CNTFRQ: 186511577SDylan.Johnson@ARM.com case MISCREG_CNTFRQ_EL0: 186611577SDylan.Johnson@ARM.com getSystemCounter(tc)->setFreq(val); 186711577SDylan.Johnson@ARM.com break; 186811577SDylan.Johnson@ARM.com case MISCREG_CNTP_CVAL: 186911577SDylan.Johnson@ARM.com case MISCREG_CNTP_CVAL_EL0: 187011577SDylan.Johnson@ARM.com getArchTimer(tc, tc->cpuId())->setCompareValue(val); 187111577SDylan.Johnson@ARM.com break; 187211577SDylan.Johnson@ARM.com case MISCREG_CNTP_TVAL: 187310037SARM gem5 Developers case MISCREG_CNTP_TVAL_EL0: 187410037SARM gem5 Developers getArchTimer(tc, tc->cpuId())->setTimerValue(val); 187510037SARM gem5 Developers break; 187610037SARM gem5 Developers case MISCREG_CNTP_CTL: 187710037SARM gem5 Developers case MISCREG_CNTP_CTL_EL0: 187810037SARM gem5 Developers getArchTimer(tc, tc->cpuId())->setControl(val); 187910037SARM gem5 Developers break; 188010037SARM gem5 Developers // PL1 phys. timer, secure 188110037SARM gem5 Developers // AArch64 188210037SARM gem5 Developers case MISCREG_CNTPS_CVAL_EL1: 188310037SARM gem5 Developers case MISCREG_CNTPS_TVAL_EL1: 188410037SARM gem5 Developers case MISCREG_CNTPS_CTL_EL1: 188510037SARM gem5 Developers // PL2 phys. timer, non-secure 188610037SARM gem5 Developers // AArch32 18878549Sdaniel.johnson@arm.com case MISCREG_CNTHCTL: 18888549Sdaniel.johnson@arm.com case MISCREG_CNTHP_CVAL: 18898549Sdaniel.johnson@arm.com case MISCREG_CNTHP_TVAL: 189010037SARM gem5 Developers case MISCREG_CNTHP_CTL: 189110037SARM gem5 Developers // AArch64 189210037SARM gem5 Developers case MISCREG_CNTHCTL_EL2: 189310844Sandreas.sandberg@arm.com case MISCREG_CNTHP_CVAL_EL2: 189410844Sandreas.sandberg@arm.com case MISCREG_CNTHP_TVAL_EL2: 189510844Sandreas.sandberg@arm.com case MISCREG_CNTHP_CTL_EL2: 189610844Sandreas.sandberg@arm.com // Virtual timer 189710844Sandreas.sandberg@arm.com // AArch32 189810037SARM gem5 Developers case MISCREG_CNTV_CVAL: 18997405SAli.Saidi@ARM.com case MISCREG_CNTV_TVAL: 19007405SAli.Saidi@ARM.com case MISCREG_CNTV_CTL: 19017405SAli.Saidi@ARM.com // AArch64 19027405SAli.Saidi@ARM.com // case MISCREG_CNTV_CVAL_EL2: 19037405SAli.Saidi@ARM.com // case MISCREG_CNTV_TVAL_EL2: 190410037SARM gem5 Developers // case MISCREG_CNTV_CTL_EL2: 190510709SAndreas.Sandberg@ARM.com break; 190610709SAndreas.Sandberg@ARM.com } 190710037SARM gem5 Developers } 190810709SAndreas.Sandberg@ARM.com setMiscRegNoEffect(misc_reg, newVal); 190910037SARM gem5 Developers} 191010037SARM gem5 Developers 191110037SARM gem5 Developersvoid 191210037SARM gem5 DevelopersISA::updateBootUncacheable(int sctlr_idx, ThreadContext *tc) 191310037SARM gem5 Developers{ 191410037SARM gem5 Developers System *sys; 191510037SARM gem5 Developers ThreadContext *oc; 191610037SARM gem5 Developers 191710037SARM gem5 Developers // Check if all CPUs are booted with caches enabled 191810037SARM gem5 Developers // so we can stop enforcing coherency of some kernel 191910037SARM gem5 Developers // structures manually. 192010037SARM gem5 Developers sys = tc->getSystemPtr(); 192110037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 192210037SARM gem5 Developers oc = sys->getThreadContext(x); 192310037SARM gem5 Developers // @todo: double check this for security 192410037SARM gem5 Developers SCTLR other_sctlr = oc->readMiscRegNoEffect(sctlr_idx); 192510037SARM gem5 Developers if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 192610037SARM gem5 Developers return; 192710037SARM gem5 Developers } 192810037SARM gem5 Developers 192910037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 193010037SARM gem5 Developers oc = sys->getThreadContext(x); 193110037SARM gem5 Developers oc->getDTBPtr()->allCpusCaching(); 193210037SARM gem5 Developers oc->getITBPtr()->allCpusCaching(); 193310037SARM gem5 Developers 193410037SARM gem5 Developers // If CheckerCPU is connected, need to notify it. 193510037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 193610037SARM gem5 Developers if (checker) { 193710037SARM gem5 Developers checker->getDTBPtr()->allCpusCaching(); 193810037SARM gem5 Developers checker->getITBPtr()->allCpusCaching(); 193910037SARM gem5 Developers } 194010037SARM gem5 Developers } 194110037SARM gem5 Developers} 194210037SARM gem5 Developers 194310037SARM gem5 Developersvoid 194410037SARM gem5 DevelopersISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid, bool secure_lookup, 194510037SARM gem5 Developers uint8_t target_el) 194610037SARM gem5 Developers{ 194710037SARM gem5 Developers if (haveLargeAsid64) 194810037SARM gem5 Developers asid &= mask(8); 194910037SARM gem5 Developers Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 195010037SARM gem5 Developers System *sys = tc->getSystemPtr(); 195110037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 195210037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 195310037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 195410037SARM gem5 Developers oc->getITBPtr()->flushMvaAsid(va, asid, 195510037SARM gem5 Developers secure_lookup, target_el); 195610037SARM gem5 Developers oc->getDTBPtr()->flushMvaAsid(va, asid, 195710037SARM gem5 Developers secure_lookup, target_el); 195810037SARM gem5 Developers 195910037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 196010037SARM gem5 Developers if (checker) { 196110037SARM gem5 Developers checker->getITBPtr()->flushMvaAsid( 196210037SARM gem5 Developers va, asid, secure_lookup, target_el); 196310037SARM gem5 Developers checker->getDTBPtr()->flushMvaAsid( 196410037SARM gem5 Developers va, asid, secure_lookup, target_el); 196510037SARM gem5 Developers } 196610037SARM gem5 Developers } 196710037SARM gem5 Developers} 196810037SARM gem5 Developers 196910037SARM gem5 Developersvoid 197010037SARM gem5 DevelopersISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 197110037SARM gem5 Developers{ 197210037SARM gem5 Developers System *sys = tc->getSystemPtr(); 197310037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 197410037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 197510037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 197610037SARM gem5 Developers oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 197710037SARM gem5 Developers oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 197810037SARM gem5 Developers 197910037SARM gem5 Developers // If CheckerCPU is connected, need to notify it of a flush 198010037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 198110037SARM gem5 Developers if (checker) { 198210037SARM gem5 Developers checker->getITBPtr()->flushAllSecurity(secure_lookup, 198310037SARM gem5 Developers target_el); 198410037SARM gem5 Developers checker->getDTBPtr()->flushAllSecurity(secure_lookup, 198510037SARM gem5 Developers target_el); 198610037SARM gem5 Developers } 198710037SARM gem5 Developers } 198810037SARM gem5 Developers} 198910037SARM gem5 Developers 199010037SARM gem5 Developersvoid 199110037SARM gem5 DevelopersISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 199210844Sandreas.sandberg@arm.com{ 199310844Sandreas.sandberg@arm.com System *sys = tc->getSystemPtr(); 199410037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 199510844Sandreas.sandberg@arm.com ThreadContext *oc = sys->getThreadContext(x); 199610844Sandreas.sandberg@arm.com assert(oc->getITBPtr() && oc->getDTBPtr()); 199710844Sandreas.sandberg@arm.com oc->getITBPtr()->flushAllNs(hyp, target_el); 199810844Sandreas.sandberg@arm.com oc->getDTBPtr()->flushAllNs(hyp, target_el); 199910844Sandreas.sandberg@arm.com 200010844Sandreas.sandberg@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 200110844Sandreas.sandberg@arm.com if (checker) { 200210844Sandreas.sandberg@arm.com checker->getITBPtr()->flushAllNs(hyp, target_el); 200310844Sandreas.sandberg@arm.com checker->getDTBPtr()->flushAllNs(hyp, target_el); 200410844Sandreas.sandberg@arm.com } 200510037SARM gem5 Developers } 200610037SARM gem5 Developers} 200711150Smitch.hayenga@arm.com 200810844Sandreas.sandberg@arm.comvoid 200910037SARM gem5 DevelopersISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 201010037SARM gem5 Developers uint8_t target_el) 20117405SAli.Saidi@ARM.com{ 20129384SAndreas.Sandberg@arm.com System *sys = tc->getSystemPtr(); 20139384SAndreas.Sandberg@arm.com for (int x = 0; x < sys->numContexts(); x++) { 20149384SAndreas.Sandberg@arm.com ThreadContext *oc = sys->getThreadContext(x); 20159384SAndreas.Sandberg@arm.com assert(oc->getITBPtr() && oc->getDTBPtr()); 20169384SAndreas.Sandberg@arm.com oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 20179384SAndreas.Sandberg@arm.com secure_lookup, hyp, target_el); 2018 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 2019 secure_lookup, hyp, target_el); 2020 2021 CheckerCPU *checker = oc->getCheckerCpuPtr(); 2022 if (checker) { 2023 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 2024 secure_lookup, hyp, target_el); 2025 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 2026 secure_lookup, hyp, target_el); 2027 } 2028 } 2029} 2030 2031::GenericTimer::SystemCounter * 2032ISA::getSystemCounter(ThreadContext *tc) 2033{ 2034 ::GenericTimer::SystemCounter *cnt = ((ArmSystem *) tc->getSystemPtr())-> 2035 getSystemCounter(); 2036 if (cnt == NULL) { 2037 panic("System counter not available\n"); 2038 } 2039 return cnt; 2040} 2041 2042::GenericTimer::ArchTimer * 2043ISA::getArchTimer(ThreadContext *tc, int cpu_id) 2044{ 2045 ::GenericTimer::ArchTimer *timer = ((ArmSystem *) tc->getSystemPtr())-> 2046 getArchTimer(cpu_id); 2047 if (timer == NULL) { 2048 panic("Architected timer not available\n"); 2049 } 2050 return timer; 2051} 2052 2053} 2054 2055ArmISA::ISA * 2056ArmISAParams::create() 2057{ 2058 return new ArmISA::ISA(this); 2059} 2060