sve_mem.hh revision 13955
113955Sgiacomo.gabrielli@arm.com/* 213955Sgiacomo.gabrielli@arm.com * Copyright (c) 2017 ARM Limited 313955Sgiacomo.gabrielli@arm.com * All rights reserved 413955Sgiacomo.gabrielli@arm.com * 513955Sgiacomo.gabrielli@arm.com * The license below extends only to copyright in the software and shall 613955Sgiacomo.gabrielli@arm.com * not be construed as granting a license to any other intellectual 713955Sgiacomo.gabrielli@arm.com * property including but not limited to intellectual property relating 813955Sgiacomo.gabrielli@arm.com * to a hardware implementation of the functionality of the software 913955Sgiacomo.gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 1013955Sgiacomo.gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 1113955Sgiacomo.gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 1213955Sgiacomo.gabrielli@arm.com * modified or unmodified, in source code or in binary form. 1313955Sgiacomo.gabrielli@arm.com * 1413955Sgiacomo.gabrielli@arm.com * Redistribution and use in source and binary forms, with or without 1513955Sgiacomo.gabrielli@arm.com * modification, are permitted provided that the following conditions are 1613955Sgiacomo.gabrielli@arm.com * met: redistributions of source code must retain the above copyright 1713955Sgiacomo.gabrielli@arm.com * notice, this list of conditions and the following disclaimer; 1813955Sgiacomo.gabrielli@arm.com * redistributions in binary form must reproduce the above copyright 1913955Sgiacomo.gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the 2013955Sgiacomo.gabrielli@arm.com * documentation and/or other materials provided with the distribution; 2113955Sgiacomo.gabrielli@arm.com * neither the name of the copyright holders nor the names of its 2213955Sgiacomo.gabrielli@arm.com * contributors may be used to endorse or promote products derived from 2313955Sgiacomo.gabrielli@arm.com * this software without specific prior written permission. 2413955Sgiacomo.gabrielli@arm.com * 2513955Sgiacomo.gabrielli@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2613955Sgiacomo.gabrielli@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2713955Sgiacomo.gabrielli@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2813955Sgiacomo.gabrielli@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2913955Sgiacomo.gabrielli@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3013955Sgiacomo.gabrielli@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3113955Sgiacomo.gabrielli@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3213955Sgiacomo.gabrielli@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3313955Sgiacomo.gabrielli@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3413955Sgiacomo.gabrielli@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3513955Sgiacomo.gabrielli@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3613955Sgiacomo.gabrielli@arm.com * 3713955Sgiacomo.gabrielli@arm.com * Authors: Giacomo Gabrielli 3813955Sgiacomo.gabrielli@arm.com */ 3913955Sgiacomo.gabrielli@arm.com 4013955Sgiacomo.gabrielli@arm.com#ifndef __ARCH_ARM_SVE_MEM_HH__ 4113955Sgiacomo.gabrielli@arm.com#define __ARCH_ARM_SVE_MEM_HH__ 4213955Sgiacomo.gabrielli@arm.com 4313955Sgiacomo.gabrielli@arm.com#include "arch/arm/insts/static_inst.hh" 4413955Sgiacomo.gabrielli@arm.com#include "arch/arm/tlb.hh" 4513955Sgiacomo.gabrielli@arm.com 4613955Sgiacomo.gabrielli@arm.comnamespace ArmISA 4713955Sgiacomo.gabrielli@arm.com{ 4813955Sgiacomo.gabrielli@arm.com 4913955Sgiacomo.gabrielli@arm.comclass SveMemVecFillSpill : public ArmStaticInst 5013955Sgiacomo.gabrielli@arm.com{ 5113955Sgiacomo.gabrielli@arm.com protected: 5213955Sgiacomo.gabrielli@arm.com IntRegIndex dest; 5313955Sgiacomo.gabrielli@arm.com IntRegIndex base; 5413955Sgiacomo.gabrielli@arm.com uint64_t imm; 5513955Sgiacomo.gabrielli@arm.com 5613955Sgiacomo.gabrielli@arm.com /// True if the base register is SP (used for SP alignment checking). 5713955Sgiacomo.gabrielli@arm.com bool baseIsSP; 5813955Sgiacomo.gabrielli@arm.com 5913955Sgiacomo.gabrielli@arm.com unsigned memAccessFlags; 6013955Sgiacomo.gabrielli@arm.com 6113955Sgiacomo.gabrielli@arm.com SveMemVecFillSpill(const char *mnem, ExtMachInst _machInst, 6213955Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 6313955Sgiacomo.gabrielli@arm.com IntRegIndex _base, uint64_t _imm) 6413955Sgiacomo.gabrielli@arm.com : ArmStaticInst(mnem, _machInst, __opClass), 6513955Sgiacomo.gabrielli@arm.com dest(_dest), base(_base), imm(_imm), 6613955Sgiacomo.gabrielli@arm.com memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne) 6713955Sgiacomo.gabrielli@arm.com { 6813955Sgiacomo.gabrielli@arm.com baseIsSP = isSP(_base); 6913955Sgiacomo.gabrielli@arm.com } 7013955Sgiacomo.gabrielli@arm.com 7113955Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 7213955Sgiacomo.gabrielli@arm.com}; 7313955Sgiacomo.gabrielli@arm.com 7413955Sgiacomo.gabrielli@arm.comclass SveMemPredFillSpill : public ArmStaticInst 7513955Sgiacomo.gabrielli@arm.com{ 7613955Sgiacomo.gabrielli@arm.com protected: 7713955Sgiacomo.gabrielli@arm.com IntRegIndex dest; 7813955Sgiacomo.gabrielli@arm.com IntRegIndex base; 7913955Sgiacomo.gabrielli@arm.com uint64_t imm; 8013955Sgiacomo.gabrielli@arm.com 8113955Sgiacomo.gabrielli@arm.com /// True if the base register is SP (used for SP alignment checking). 8213955Sgiacomo.gabrielli@arm.com bool baseIsSP; 8313955Sgiacomo.gabrielli@arm.com 8413955Sgiacomo.gabrielli@arm.com unsigned memAccessFlags; 8513955Sgiacomo.gabrielli@arm.com 8613955Sgiacomo.gabrielli@arm.com SveMemPredFillSpill(const char *mnem, ExtMachInst _machInst, 8713955Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 8813955Sgiacomo.gabrielli@arm.com IntRegIndex _base, uint64_t _imm) 8913955Sgiacomo.gabrielli@arm.com : ArmStaticInst(mnem, _machInst, __opClass), 9013955Sgiacomo.gabrielli@arm.com dest(_dest), base(_base), imm(_imm), 9113955Sgiacomo.gabrielli@arm.com memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne) 9213955Sgiacomo.gabrielli@arm.com { 9313955Sgiacomo.gabrielli@arm.com baseIsSP = isSP(_base); 9413955Sgiacomo.gabrielli@arm.com } 9513955Sgiacomo.gabrielli@arm.com 9613955Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 9713955Sgiacomo.gabrielli@arm.com}; 9813955Sgiacomo.gabrielli@arm.com 9913955Sgiacomo.gabrielli@arm.comclass SveContigMemSS : public ArmStaticInst 10013955Sgiacomo.gabrielli@arm.com{ 10113955Sgiacomo.gabrielli@arm.com protected: 10213955Sgiacomo.gabrielli@arm.com IntRegIndex dest; 10313955Sgiacomo.gabrielli@arm.com IntRegIndex gp; 10413955Sgiacomo.gabrielli@arm.com IntRegIndex base; 10513955Sgiacomo.gabrielli@arm.com IntRegIndex offset; 10613955Sgiacomo.gabrielli@arm.com 10713955Sgiacomo.gabrielli@arm.com /// True if the base register is SP (used for SP alignment checking). 10813955Sgiacomo.gabrielli@arm.com bool baseIsSP; 10913955Sgiacomo.gabrielli@arm.com 11013955Sgiacomo.gabrielli@arm.com unsigned memAccessFlags; 11113955Sgiacomo.gabrielli@arm.com 11213955Sgiacomo.gabrielli@arm.com SveContigMemSS(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 11313955Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, 11413955Sgiacomo.gabrielli@arm.com IntRegIndex _offset) 11513955Sgiacomo.gabrielli@arm.com : ArmStaticInst(mnem, _machInst, __opClass), 11613955Sgiacomo.gabrielli@arm.com dest(_dest), gp(_gp), base(_base), offset(_offset), 11713955Sgiacomo.gabrielli@arm.com memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne) 11813955Sgiacomo.gabrielli@arm.com { 11913955Sgiacomo.gabrielli@arm.com baseIsSP = isSP(_base); 12013955Sgiacomo.gabrielli@arm.com } 12113955Sgiacomo.gabrielli@arm.com 12213955Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 12313955Sgiacomo.gabrielli@arm.com}; 12413955Sgiacomo.gabrielli@arm.com 12513955Sgiacomo.gabrielli@arm.comclass SveContigMemSI : public ArmStaticInst 12613955Sgiacomo.gabrielli@arm.com{ 12713955Sgiacomo.gabrielli@arm.com protected: 12813955Sgiacomo.gabrielli@arm.com IntRegIndex dest; 12913955Sgiacomo.gabrielli@arm.com IntRegIndex gp; 13013955Sgiacomo.gabrielli@arm.com IntRegIndex base; 13113955Sgiacomo.gabrielli@arm.com uint64_t imm; 13213955Sgiacomo.gabrielli@arm.com 13313955Sgiacomo.gabrielli@arm.com /// True if the base register is SP (used for SP alignment checking). 13413955Sgiacomo.gabrielli@arm.com bool baseIsSP; 13513955Sgiacomo.gabrielli@arm.com 13613955Sgiacomo.gabrielli@arm.com unsigned memAccessFlags; 13713955Sgiacomo.gabrielli@arm.com 13813955Sgiacomo.gabrielli@arm.com SveContigMemSI(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 13913955Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, 14013955Sgiacomo.gabrielli@arm.com uint64_t _imm) 14113955Sgiacomo.gabrielli@arm.com : ArmStaticInst(mnem, _machInst, __opClass), 14213955Sgiacomo.gabrielli@arm.com dest(_dest), gp(_gp), base(_base), imm(_imm), 14313955Sgiacomo.gabrielli@arm.com memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne) 14413955Sgiacomo.gabrielli@arm.com { 14513955Sgiacomo.gabrielli@arm.com baseIsSP = isSP(_base); 14613955Sgiacomo.gabrielli@arm.com } 14713955Sgiacomo.gabrielli@arm.com 14813955Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 14913955Sgiacomo.gabrielli@arm.com}; 15013955Sgiacomo.gabrielli@arm.com 15113955Sgiacomo.gabrielli@arm.com} // namespace ArmISA 15213955Sgiacomo.gabrielli@arm.com 15313955Sgiacomo.gabrielli@arm.com#endif // __ARCH_ARM_SVE_MEM_HH__ 154