pred_inst.hh revision 7143:c81f34f9e075 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_PREDINST_HH__
43#define __ARCH_ARM_INSTS_PREDINST_HH__
44
45#include "arch/arm/insts/static_inst.hh"
46#include "base/trace.hh"
47
48namespace ArmISA
49{
50static inline uint32_t
51rotate_imm(uint32_t immValue, int rotateValue)
52{
53    return ((immValue >> (rotateValue & 31)) |
54            (immValue << (32 - (rotateValue & 31))));
55}
56
57static inline uint32_t
58modified_imm(uint8_t ctrlImm, uint8_t dataImm)
59{
60    uint32_t bigData = dataImm;
61    uint32_t bigCtrl = ctrlImm;
62    if (bigCtrl < 4) {
63        switch (bigCtrl) {
64          case 0:
65            return bigData;
66          case 1:
67            return bigData | (bigData << 16);
68          case 2:
69            return (bigData << 8) | (bigData << 24);
70          case 3:
71            return (bigData << 0) | (bigData << 8) |
72                   (bigData << 16) | (bigData << 24);
73        }
74    }
75    bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1);
76    bigData |= (1 << 7);
77    return bigData << (32 - bigCtrl);
78}
79
80
81/**
82 * Base class for predicated integer operations.
83 */
84class PredOp : public ArmStaticInst
85{
86  protected:
87
88    ConditionCode condCode;
89
90    /// Constructor
91    PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
92           ArmStaticInst(mnem, _machInst, __opClass),
93           condCode((ConditionCode)(unsigned)machInst.condCode)
94    {
95    }
96};
97
98/**
99 * Base class for predicated immediate operations.
100 */
101class PredImmOp : public PredOp
102{
103    protected:
104
105    uint32_t imm;
106    uint32_t rotated_imm;
107    uint32_t rotated_carry;
108    uint32_t rotate;
109
110    /// Constructor
111    PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
112              PredOp(mnem, _machInst, __opClass),
113              imm(machInst.imm), rotated_imm(0), rotated_carry(0),
114              rotate(machInst.rotate << 1)
115    {
116        rotated_imm = rotate_imm(imm, rotate);
117        if (rotate != 0)
118            rotated_carry = bits(rotated_imm, 31);
119    }
120
121    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
122};
123
124/**
125 * Base class for predicated integer operations.
126 */
127class PredIntOp : public PredOp
128{
129    protected:
130
131    uint32_t shift_size;
132    uint32_t shift;
133
134    /// Constructor
135    PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
136              PredOp(mnem, _machInst, __opClass),
137              shift_size(machInst.shiftSize), shift(machInst.shift)
138    {
139    }
140
141    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
142};
143
144class DataImmOp : public PredOp
145{
146  protected:
147    IntRegIndex dest, op1;
148    uint32_t imm;
149    // Whether the carry flag should be modified if that's an option for
150    // this instruction.
151    bool rotC;
152
153    DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
154              IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
155        PredOp(mnem, _machInst, __opClass),
156        dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
157    {}
158
159    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
160};
161
162class DataRegOp : public PredOp
163{
164  protected:
165    IntRegIndex dest, op1, op2;
166    int32_t shiftAmt;
167    ArmShiftType shiftType;
168
169    DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
170              IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
171              int32_t _shiftAmt, ArmShiftType _shiftType) :
172        PredOp(mnem, _machInst, __opClass),
173        dest(_dest), op1(_op1), op2(_op2),
174        shiftAmt(_shiftAmt), shiftType(_shiftType)
175    {}
176
177    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
178};
179
180class DataRegRegOp : public PredOp
181{
182  protected:
183    IntRegIndex dest, op1, op2, shift;
184    ArmShiftType shiftType;
185
186    DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
187                 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
188                 IntRegIndex _shift, ArmShiftType _shiftType) :
189        PredOp(mnem, _machInst, __opClass),
190        dest(_dest), op1(_op1), op2(_op2), shift(_shift),
191        shiftType(_shiftType)
192    {}
193
194    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
195};
196
197/**
198 * Base class for predicated macro-operations.
199 */
200class PredMacroOp : public PredOp
201{
202    protected:
203
204    uint32_t numMicroops;
205    StaticInstPtr * microOps;
206
207    /// Constructor
208    PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
209                PredOp(mnem, _machInst, __opClass),
210                numMicroops(0)
211    {
212        // We rely on the subclasses of this object to handle the
213        // initialization of the micro-operations, since they are
214        // all of variable length
215        flags[IsMacroop] = true;
216    }
217
218    ~PredMacroOp()
219    {
220        if (numMicroops)
221            delete [] microOps;
222    }
223
224    StaticInstPtr
225    fetchMicroop(MicroPC microPC)
226    {
227        assert(microPC < numMicroops);
228        return microOps[microPC];
229    }
230
231    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
232};
233
234/**
235 * Base class for predicated micro-operations.
236 */
237class PredMicroop : public PredOp
238{
239    /// Constructor
240    PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
241                PredOp(mnem, _machInst, __opClass)
242    {
243        flags[IsMicroop] = true;
244    }
245};
246}
247
248#endif //__ARCH_ARM_INSTS_PREDINST_HH__
249