pred_inst.hh revision 7142:c63c06703d0f 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_PREDINST_HH__
43#define __ARCH_ARM_INSTS_PREDINST_HH__
44
45#include "arch/arm/insts/static_inst.hh"
46#include "base/trace.hh"
47
48namespace ArmISA
49{
50static inline uint32_t
51rotate_imm(uint32_t immValue, int rotateValue)
52{
53    return ((immValue >> (rotateValue & 31)) |
54            (immValue << (32 - (rotateValue & 31))));
55}
56
57static inline uint32_t
58modified_imm(uint8_t ctrlImm, uint8_t dataImm)
59{
60    uint32_t bigData = dataImm;
61    uint32_t bigCtrl = ctrlImm;
62    if (bigCtrl < 4) {
63        switch (bigCtrl) {
64          case 0:
65            return bigData;
66          case 1:
67            return bigData | (bigData << 16);
68          case 2:
69            return (bigData << 8) | (bigData << 24);
70          case 3:
71            return (bigData << 0) | (bigData << 8) |
72                   (bigData << 16) | (bigData << 24);
73        }
74    }
75    bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1);
76    bigData |= (1 << 7);
77    return bigData << (32 - bigCtrl);
78}
79
80
81/**
82 * Base class for predicated integer operations.
83 */
84class PredOp : public ArmStaticInst
85{
86  protected:
87
88    ConditionCode condCode;
89
90    /// Constructor
91    PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
92           ArmStaticInst(mnem, _machInst, __opClass),
93           condCode((ConditionCode)(unsigned)machInst.condCode)
94    {
95    }
96};
97
98/**
99 * Base class for predicated immediate operations.
100 */
101class PredImmOpBase : public PredOp
102{
103    protected:
104
105    uint32_t imm;
106    uint32_t rotated_imm;
107    uint32_t rotated_carry;
108
109    /// Constructor
110    PredImmOpBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
111                  PredOp(mnem, _machInst, __opClass),
112                  imm(machInst.imm), rotated_imm(0), rotated_carry(0)
113    {
114    }
115
116    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
117};
118
119/**
120 * Base class for regular predicated immediate operations.
121 */
122class PredImmOp : public PredImmOpBase
123{
124    protected:
125
126    uint32_t rotate;
127
128    /// Constructor
129    PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
130              PredImmOpBase(mnem, _machInst, __opClass),
131              rotate(machInst.rotate << 1)
132    {
133        rotated_imm = rotate_imm(imm, rotate);
134        if (rotate != 0)
135            rotated_carry = bits(rotated_imm, 31);
136    }
137};
138
139/**
140 * Base class for modified predicated immediate operations.
141 */
142class PredModImmOp : public PredImmOpBase
143{
144    protected:
145
146    uint8_t ctrlImm;
147    uint8_t dataImm;
148
149
150    /// Constructor
151    PredModImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
152                 PredImmOpBase(mnem, _machInst, __opClass),
153                 ctrlImm(bits(machInst.instBits, 26) << 3 |
154                         bits(machInst.instBits, 14, 12)),
155                 dataImm(bits(machInst.instBits, 7, 0))
156    {
157        rotated_imm = modified_imm(ctrlImm, dataImm);
158        rotated_carry = bits(rotated_imm, 31);
159    }
160};
161
162/**
163 * Base class for predicated integer operations.
164 */
165class PredIntOp : public PredOp
166{
167    protected:
168
169    uint32_t shift_size;
170    uint32_t shift;
171
172    /// Constructor
173    PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
174              PredOp(mnem, _machInst, __opClass),
175              shift_size(machInst.shiftSize), shift(machInst.shift)
176    {
177    }
178
179    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
180};
181
182class DataImmOp : public PredOp
183{
184  protected:
185    IntRegIndex dest, op1;
186    uint32_t imm;
187    // Whether the carry flag should be modified if that's an option for
188    // this instruction.
189    bool rotC;
190
191    DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
192              IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
193        PredOp(mnem, _machInst, __opClass),
194        dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
195    {}
196
197    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
198};
199
200class DataRegOp : public PredOp
201{
202  protected:
203    IntRegIndex dest, op1, op2;
204    int32_t shiftAmt;
205    ArmShiftType shiftType;
206
207    DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
208              IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
209              int32_t _shiftAmt, ArmShiftType _shiftType) :
210        PredOp(mnem, _machInst, __opClass),
211        dest(_dest), op1(_op1), op2(_op2),
212        shiftAmt(_shiftAmt), shiftType(_shiftType)
213    {}
214
215    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
216};
217
218class DataRegRegOp : public PredOp
219{
220  protected:
221    IntRegIndex dest, op1, op2, shift;
222    ArmShiftType shiftType;
223
224    DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
225                 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
226                 IntRegIndex _shift, ArmShiftType _shiftType) :
227        PredOp(mnem, _machInst, __opClass),
228        dest(_dest), op1(_op1), op2(_op2), shift(_shift),
229        shiftType(_shiftType)
230    {}
231
232    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
233};
234
235/**
236 * Base class for predicated macro-operations.
237 */
238class PredMacroOp : public PredOp
239{
240    protected:
241
242    uint32_t numMicroops;
243    StaticInstPtr * microOps;
244
245    /// Constructor
246    PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
247                PredOp(mnem, _machInst, __opClass),
248                numMicroops(0)
249    {
250        // We rely on the subclasses of this object to handle the
251        // initialization of the micro-operations, since they are
252        // all of variable length
253        flags[IsMacroop] = true;
254    }
255
256    ~PredMacroOp()
257    {
258        if (numMicroops)
259            delete [] microOps;
260    }
261
262    StaticInstPtr
263    fetchMicroop(MicroPC microPC)
264    {
265        assert(microPC < numMicroops);
266        return microOps[microPC];
267    }
268
269    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
270};
271
272/**
273 * Base class for predicated micro-operations.
274 */
275class PredMicroop : public PredOp
276{
277    /// Constructor
278    PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
279                PredOp(mnem, _machInst, __opClass)
280    {
281        flags[IsMicroop] = true;
282    }
283};
284}
285
286#endif //__ARCH_ARM_INSTS_PREDINST_HH__
287