1/* 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by the University of Cambridge Computer 6 * Laboratory as part of the CTSRD Project, with support from the UK Higher 7 * Education Innovation Fund (HEIF). 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are 11 * met: redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer; 13 * redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution; 16 * neither the name of the copyright holders nor the names of its 17 * contributors may be used to endorse or promote products derived from 18 * this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#ifndef __ARCH_ARM_FREEBSD_SYSTEM_HH__ 34#define __ARCH_ARM_FREEBSD_SYSTEM_HH__ 35 36#include <cstdio> 37#include <map> 38#include <string> 39#include <vector> 40 41#include "arch/arm/system.hh" 42#include "base/output.hh" 43#include "kern/freebsd/events.hh" 44#include "params/FreebsdArmSystem.hh" 45#include "sim/core.hh" 46 47class FreebsdArmSystem : public GenericArmSystem 48{ 49 public: 50 /** Boilerplate params code */ 51 typedef FreebsdArmSystemParams Params; 52 const Params * 53 params() const 54 { 55 return dynamic_cast<const Params *>(_params); 56 } 57 58 /** When enabled, dump stats/task info on context switches for 59 * Streamline and per-thread cache occupancy studies, etc. */ 60 bool enableContextSwitchStatsDump; 61 62 /** This map stores a mapping of OS process IDs to internal Task IDs. The 63 * mapping is done because the stats system doesn't tend to like vectors 64 * that are much greater than 1000 items and the entire process space is 65 * 65K. */ 66 std::map<uint32_t, uint32_t> taskMap; 67 68 /** This is a file that is placed in the run directory that prints out 69 * mappings between taskIds and OS process IDs */ 70 std::ostream* taskFile; 71 72 FreebsdArmSystem(Params *p); 73 ~FreebsdArmSystem(); 74 75 void initState(); 76 77 void startup(); 78 79 /** This function creates a new task Id for the given pid. 80 * @param tc thread context that is currentyl executing */ 81 void mapPid(ThreadContext* tc, uint32_t pid); 82 83 private: 84 /** Event to halt the simulator if the kernel calls panic() */ 85 PCEvent *kernelPanicEvent; 86 87 /** Event to halt the simulator if the kernel calls oopses */ 88 PCEvent *kernelOopsEvent; 89 90 /** 91 * PC based event to skip udelay(<time>) calls and quiesce the 92 * processor for the appropriate amount of time. This is not functionally 93 * required but does speed up simulation. 94 */ 95 FreeBSD::UDelayEvent *uDelaySkipEvent; 96 97 /** Another PC based skip event for const_udelay(). Similar to the udelay 98 * skip, but this function precomputes the first multiply that is done 99 * in the generic case since the parameter is known at compile time. 100 * Thus we need to do some division to get back to us. 101 */ 102 FreeBSD::UDelayEvent *constUDelaySkipEvent; 103 104 /** These variables store addresses of important data structures 105 * that are normaly kept coherent at boot with cache mainetence operations. 106 * Since these operations aren't supported in gem5, we keep them coherent 107 * by making them uncacheable until all processors in the system boot. 108 */ 109 Addr secDataPtrAddr; 110 Addr secDataAddr; 111 Addr penReleaseAddr; 112 Addr pen64ReleaseAddr; 113 Addr bootReleaseAddr; 114}; 115 116#endif // __ARCH_ARM_FREEBSD_SYSTEM_HH__ 117 118