faults.cc revision 8232 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 */
44
45#include "arch/arm/faults.hh"
46#include "base/trace.hh"
47#include "cpu/base.hh"
48#include "cpu/thread_context.hh"
49#include "debug/Faults.hh"
50
51namespace ArmISA
52{
53
54template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
55    {"reset", 0x00, MODE_SVC, 0, 0, true, true};
56
57template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
58    {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
59
60template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
61    {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
62
63template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
64    {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
65
66template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
67    {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
68
69template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
70    {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
71
72template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
73    {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
74
75template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals =
76    {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
77
78template<> ArmFault::FaultVals ArmFaultVals<ReExec>::vals =
79    {"ReExec Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
80
81Addr
82ArmFault::getVector(ThreadContext *tc)
83{
84    // ARM ARM B1-3
85
86    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
87
88    // panic if SCTLR.VE because I have no idea what to do with vectored
89    // interrupts
90    assert(!sctlr.ve);
91
92    if (!sctlr.v)
93        return offset();
94    return offset() + HighVecs;
95
96}
97
98#if FULL_SYSTEM
99
100void
101ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
102{
103    // ARM ARM B1.6.3
104    FaultBase::invoke(tc);
105    countStat()++;
106
107    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
108    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
109    CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
110                      tc->readIntReg(INTREG_CONDCODES);
111    Addr curPc M5_VAR_USED = tc->pcState().pc();
112    ITSTATE it = tc->pcState().itstate();
113    saved_cpsr.it2 = it.top6;
114    saved_cpsr.it1 = it.bottom2;
115
116    cpsr.mode = nextMode();
117    cpsr.it1 = cpsr.it2 = 0;
118    cpsr.j = 0;
119
120    cpsr.t = sctlr.te;
121    cpsr.a = cpsr.a | abortDisable();
122    cpsr.f = cpsr.f | fiqDisable();
123    cpsr.i = 1;
124    cpsr.e = sctlr.ee;
125    tc->setMiscReg(MISCREG_CPSR, cpsr);
126    tc->setIntReg(INTREG_LR, curPc +
127            (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
128
129    switch (nextMode()) {
130      case MODE_FIQ:
131        tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
132        break;
133      case MODE_IRQ:
134        tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
135        break;
136      case MODE_SVC:
137        tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
138        break;
139      case MODE_UNDEFINED:
140        tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
141        break;
142      case MODE_ABORT:
143        tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
144        break;
145      default:
146        panic("unknown Mode\n");
147    }
148
149    Addr newPc = getVector(tc);
150    DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
151            name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
152    PCState pc(newPc);
153    pc.thumb(cpsr.t);
154    pc.nextThumb(pc.thumb());
155    pc.jazelle(cpsr.j);
156    pc.nextJazelle(pc.jazelle());
157    tc->pcState(pc);
158}
159
160void
161Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
162{
163    tc->getCpuPtr()->clearInterrupts();
164    tc->clearArchRegs();
165    ArmFault::invoke(tc, inst);
166}
167
168#else
169
170void
171UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
172{
173    // If the mnemonic isn't defined this has to be an unknown instruction.
174    assert(unknown || mnemonic != NULL);
175    if (disabled) {
176        panic("Attempted to execute disabled instruction "
177                "'%s' (inst 0x%08x)", mnemonic, machInst);
178    } else if (unknown) {
179        panic("Attempted to execute unknown instruction (inst 0x%08x)",
180              machInst);
181    } else {
182        panic("Attempted to execute unimplemented instruction "
183                "'%s' (inst 0x%08x)", mnemonic, machInst);
184    }
185}
186
187void
188SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
189{
190    // As of now, there isn't a 32 bit thumb version of this instruction.
191    assert(!machInst.bigThumb);
192    uint32_t callNum;
193    callNum = tc->readIntReg(INTREG_R7);
194    tc->syscall(callNum);
195
196    // Advance the PC since that won't happen automatically.
197    PCState pc = tc->pcState();
198    assert(inst);
199    inst->advancePC(pc);
200    tc->pcState(pc);
201}
202
203#endif // FULL_SYSTEM
204
205template<class T>
206void
207AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
208{
209    ArmFaultVals<T>::invoke(tc, inst);
210    FSR fsr = 0;
211    fsr.fsLow = bits(status, 3, 0);
212    fsr.fsHigh = bits(status, 4);
213    fsr.domain = domain;
214    fsr.wnr = (write ? 1 : 0);
215    fsr.ext = 0;
216    tc->setMiscReg(T::FsrIndex, fsr);
217    tc->setMiscReg(T::FarIndex, faultAddr);
218}
219
220void
221FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
222    DPRINTF(Faults, "Invoking FlushPipe Fault\n");
223
224    // Set the PC to the next instruction of the faulting instruction.
225    // Net effect is simply squashing all instructions behind and
226    // start refetching from the next instruction.
227    PCState pc = tc->pcState();
228    assert(inst);
229    inst->advancePC(pc);
230    tc->pcState(pc);
231}
232
233void
234ReExec::invoke(ThreadContext *tc, StaticInstPtr inst) {
235    DPRINTF(Faults, "Invoking ReExec Fault\n");
236
237    // Set the PC to then the faulting instruction.
238    // Net effect is simply squashing all instructions including this
239    // instruction and refetching/rexecuting current instruction
240    PCState pc = tc->pcState();
241    tc->pcState(pc);
242}
243
244template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
245                                                StaticInstPtr inst);
246template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
247                                            StaticInstPtr inst);
248
249// return via SUBS pc, lr, xxx; rfe, movs, ldm
250
251} // namespace ArmISA
252