faults.cc revision 8202
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 36313Sgblack@eecs.umich.edu * All rights reserved 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 66313Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 76313Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 86313Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 96313Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 106313Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 116313Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 126313Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 136313Sgblack@eecs.umich.edu * 146313Sgblack@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156313Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 166313Sgblack@eecs.umich.edu * All rights reserved. 176313Sgblack@eecs.umich.edu * 186313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 196313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 206313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 216313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 226313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 236313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 246313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 256313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 266313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 276313Sgblack@eecs.umich.edu * this software without specific prior written permission. 286313Sgblack@eecs.umich.edu * 296313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316335Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336335Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346335Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356335Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366335Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406313Sgblack@eecs.umich.edu * 416313Sgblack@eecs.umich.edu * Authors: Ali Saidi 426335Sgblack@eecs.umich.edu * Gabe Black 436335Sgblack@eecs.umich.edu */ 447741Sgblack@eecs.umich.edu 456335Sgblack@eecs.umich.edu#include "arch/arm/faults.hh" 466335Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 476313Sgblack@eecs.umich.edu#include "cpu/base.hh" 486337Sgblack@eecs.umich.edu#include "base/trace.hh" 496337Sgblack@eecs.umich.edu 506337Sgblack@eecs.umich.edunamespace ArmISA 516337Sgblack@eecs.umich.edu{ 526337Sgblack@eecs.umich.edu 536337Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals = 546337Sgblack@eecs.umich.edu {"reset", 0x00, MODE_SVC, 0, 0, true, true}; 556337Sgblack@eecs.umich.edu 566337Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals = 576337Sgblack@eecs.umich.edu {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ; 586337Sgblack@eecs.umich.edu 596337Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals = 606337Sgblack@eecs.umich.edu {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false}; 616337Sgblack@eecs.umich.edu 626337Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals = 636337Sgblack@eecs.umich.edu {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false}; 646337Sgblack@eecs.umich.edu 656337Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals = 666337Sgblack@eecs.umich.edu {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false}; 676337Sgblack@eecs.umich.edu 686337Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = 696337Sgblack@eecs.umich.edu {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false}; 706337Sgblack@eecs.umich.edu 716337Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = 726337Sgblack@eecs.umich.edu {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true}; 736337Sgblack@eecs.umich.edu 746337Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals = 756337Sgblack@eecs.umich.edu {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values 766337Sgblack@eecs.umich.edu 776337Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<ReExec>::vals = 786337Sgblack@eecs.umich.edu {"ReExec Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values 796337Sgblack@eecs.umich.edu 806337Sgblack@eecs.umich.eduAddr 816337Sgblack@eecs.umich.eduArmFault::getVector(ThreadContext *tc) 826313Sgblack@eecs.umich.edu{ 836313Sgblack@eecs.umich.edu // ARM ARM B1-3 846337Sgblack@eecs.umich.edu 856337Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 866337Sgblack@eecs.umich.edu 876337Sgblack@eecs.umich.edu // panic if SCTLR.VE because I have no idea what to do with vectored 887741Sgblack@eecs.umich.edu // interrupts 897741Sgblack@eecs.umich.edu assert(!sctlr.ve); 906335Sgblack@eecs.umich.edu 916335Sgblack@eecs.umich.edu if (!sctlr.v) 926335Sgblack@eecs.umich.edu return offset(); 936335Sgblack@eecs.umich.edu return offset() + HighVecs; 946335Sgblack@eecs.umich.edu 956335Sgblack@eecs.umich.edu} 966335Sgblack@eecs.umich.edu 976335Sgblack@eecs.umich.edu#if FULL_SYSTEM 986335Sgblack@eecs.umich.edu 996335Sgblack@eecs.umich.eduvoid 1006335Sgblack@eecs.umich.eduArmFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1016335Sgblack@eecs.umich.edu{ 1027703Sgblack@eecs.umich.edu // ARM ARM B1.6.3 1036335Sgblack@eecs.umich.edu FaultBase::invoke(tc); 1046335Sgblack@eecs.umich.edu countStat()++; 1056335Sgblack@eecs.umich.edu 1067741Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 1077741Sgblack@eecs.umich.edu CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1087741Sgblack@eecs.umich.edu CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | 1097741Sgblack@eecs.umich.edu tc->readIntReg(INTREG_CONDCODES); 1107741Sgblack@eecs.umich.edu Addr curPc M5_VAR_USED = tc->pcState().pc(); 1117741Sgblack@eecs.umich.edu 1126335Sgblack@eecs.umich.edu 1136335Sgblack@eecs.umich.edu cpsr.mode = nextMode(); 1146335Sgblack@eecs.umich.edu cpsr.it1 = cpsr.it2 = 0; 1156335Sgblack@eecs.umich.edu cpsr.j = 0; 1166335Sgblack@eecs.umich.edu 1177741Sgblack@eecs.umich.edu cpsr.t = sctlr.te; 1186335Sgblack@eecs.umich.edu cpsr.a = cpsr.a | abortDisable(); 1196335Sgblack@eecs.umich.edu cpsr.f = cpsr.f | fiqDisable(); 1206335Sgblack@eecs.umich.edu cpsr.i = 1; 1216335Sgblack@eecs.umich.edu cpsr.e = sctlr.ee; 1226335Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CPSR, cpsr); 1236335Sgblack@eecs.umich.edu tc->setIntReg(INTREG_LR, curPc + 1246335Sgblack@eecs.umich.edu (saved_cpsr.t ? thumbPcOffset() : armPcOffset())); 1256335Sgblack@eecs.umich.edu 1266335Sgblack@eecs.umich.edu switch (nextMode()) { 1277703Sgblack@eecs.umich.edu case MODE_FIQ: 1287703Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 1297703Sgblack@eecs.umich.edu break; 1307703Sgblack@eecs.umich.edu case MODE_IRQ: 1317703Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 1327703Sgblack@eecs.umich.edu break; 1337703Sgblack@eecs.umich.edu case MODE_SVC: 1347703Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 1357703Sgblack@eecs.umich.edu break; 1367703Sgblack@eecs.umich.edu case MODE_UNDEFINED: 1376335Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 1387703Sgblack@eecs.umich.edu break; 1397703Sgblack@eecs.umich.edu case MODE_ABORT: 1407703Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 1417703Sgblack@eecs.umich.edu break; 1426335Sgblack@eecs.umich.edu default: 1436313Sgblack@eecs.umich.edu panic("unknown Mode\n"); 1446313Sgblack@eecs.umich.edu } 1456313Sgblack@eecs.umich.edu 1466313Sgblack@eecs.umich.edu Addr newPc = getVector(tc); 1476313Sgblack@eecs.umich.edu DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n", 1486335Sgblack@eecs.umich.edu name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc); 1496335Sgblack@eecs.umich.edu PCState pc(newPc); 1506335Sgblack@eecs.umich.edu pc.thumb(cpsr.t); 1516335Sgblack@eecs.umich.edu pc.nextThumb(pc.thumb()); 1526335Sgblack@eecs.umich.edu pc.jazelle(cpsr.j); 1536335Sgblack@eecs.umich.edu pc.nextJazelle(pc.jazelle()); 1546335Sgblack@eecs.umich.edu tc->pcState(pc); 1556335Sgblack@eecs.umich.edu} 1566335Sgblack@eecs.umich.edu 1576335Sgblack@eecs.umich.eduvoid 1586335Sgblack@eecs.umich.eduReset::invoke(ThreadContext *tc, StaticInstPtr inst) 1596335Sgblack@eecs.umich.edu{ 1606335Sgblack@eecs.umich.edu tc->getCpuPtr()->clearInterrupts(); 1616335Sgblack@eecs.umich.edu tc->clearArchRegs(); 1626335Sgblack@eecs.umich.edu ArmFault::invoke(tc); 1636335Sgblack@eecs.umich.edu} 1646335Sgblack@eecs.umich.edu 1656335Sgblack@eecs.umich.edu#else 1666335Sgblack@eecs.umich.edu 1676335Sgblack@eecs.umich.eduvoid 1686335Sgblack@eecs.umich.eduUndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) 1696335Sgblack@eecs.umich.edu{ 1706335Sgblack@eecs.umich.edu // If the mnemonic isn't defined this has to be an unknown instruction. 1716335Sgblack@eecs.umich.edu assert(unknown || mnemonic != NULL); 1726335Sgblack@eecs.umich.edu if (disabled) { 1736335Sgblack@eecs.umich.edu panic("Attempted to execute disabled instruction " 1746335Sgblack@eecs.umich.edu "'%s' (inst 0x%08x)", mnemonic, machInst); 1756335Sgblack@eecs.umich.edu } else if (unknown) { 1766335Sgblack@eecs.umich.edu panic("Attempted to execute unknown instruction (inst 0x%08x)", 1776335Sgblack@eecs.umich.edu machInst); 1787741Sgblack@eecs.umich.edu } else { 1796335Sgblack@eecs.umich.edu panic("Attempted to execute unimplemented instruction " 1807741Sgblack@eecs.umich.edu "'%s' (inst 0x%08x)", mnemonic, machInst); 1816335Sgblack@eecs.umich.edu } 1827741Sgblack@eecs.umich.edu} 1836335Sgblack@eecs.umich.edu 1846335Sgblack@eecs.umich.eduvoid 1856335Sgblack@eecs.umich.eduSupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst) 1866335Sgblack@eecs.umich.edu{ 1876335Sgblack@eecs.umich.edu // As of now, there isn't a 32 bit thumb version of this instruction. 1886335Sgblack@eecs.umich.edu assert(!machInst.bigThumb); 1896335Sgblack@eecs.umich.edu uint32_t callNum; 1906335Sgblack@eecs.umich.edu callNum = tc->readIntReg(INTREG_R7); 1916335Sgblack@eecs.umich.edu tc->syscall(callNum); 1926335Sgblack@eecs.umich.edu 1936335Sgblack@eecs.umich.edu // Advance the PC since that won't happen automatically. 1946335Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 1956335Sgblack@eecs.umich.edu assert(inst); 1966335Sgblack@eecs.umich.edu inst->advancePC(pc); 1976335Sgblack@eecs.umich.edu tc->pcState(pc); 1986335Sgblack@eecs.umich.edu} 1996335Sgblack@eecs.umich.edu 2006335Sgblack@eecs.umich.edu#endif // FULL_SYSTEM 2016335Sgblack@eecs.umich.edu 2026335Sgblack@eecs.umich.edutemplate<class T> 2036335Sgblack@eecs.umich.eduvoid 2046335Sgblack@eecs.umich.eduAbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst) 2056335Sgblack@eecs.umich.edu{ 2066335Sgblack@eecs.umich.edu ArmFaultVals<T>::invoke(tc); 2076335Sgblack@eecs.umich.edu FSR fsr = 0; 2086335Sgblack@eecs.umich.edu fsr.fsLow = bits(status, 3, 0); 2096335Sgblack@eecs.umich.edu fsr.fsHigh = bits(status, 4); 2106335Sgblack@eecs.umich.edu fsr.domain = domain; 2116335Sgblack@eecs.umich.edu fsr.wnr = (write ? 1 : 0); 2126335Sgblack@eecs.umich.edu fsr.ext = 0; 2136335Sgblack@eecs.umich.edu tc->setMiscReg(T::FsrIndex, fsr); 2146335Sgblack@eecs.umich.edu tc->setMiscReg(T::FarIndex, faultAddr); 2156335Sgblack@eecs.umich.edu} 2166335Sgblack@eecs.umich.edu 2176335Sgblack@eecs.umich.eduvoid 2186335Sgblack@eecs.umich.eduFlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) { 2196335Sgblack@eecs.umich.edu DPRINTF(Faults, "Invoking FlushPipe Fault\n"); 2206335Sgblack@eecs.umich.edu 2216335Sgblack@eecs.umich.edu // Set the PC to the next instruction of the faulting instruction. 2226335Sgblack@eecs.umich.edu // Net effect is simply squashing all instructions behind and 2236335Sgblack@eecs.umich.edu // start refetching from the next instruction. 2247741Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 2257741Sgblack@eecs.umich.edu assert(inst); 2267741Sgblack@eecs.umich.edu pc.forcedItState(inst->machInst.newItstate); 2277741Sgblack@eecs.umich.edu inst->advancePC(pc); 2287741Sgblack@eecs.umich.edu tc->pcState(pc); 2297741Sgblack@eecs.umich.edu} 2307741Sgblack@eecs.umich.edu 2317741Sgblack@eecs.umich.eduvoid 2327741Sgblack@eecs.umich.eduReExec::invoke(ThreadContext *tc, StaticInstPtr inst) { 2337741Sgblack@eecs.umich.edu DPRINTF(Faults, "Invoking ReExec Fault\n"); 2347741Sgblack@eecs.umich.edu 2357741Sgblack@eecs.umich.edu // Set the PC to then the faulting instruction. 2367741Sgblack@eecs.umich.edu // Net effect is simply squashing all instructions including this 2377741Sgblack@eecs.umich.edu // instruction and refetching/rexecuting current instruction 2387741Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 2396335Sgblack@eecs.umich.edu tc->pcState(pc); 2406335Sgblack@eecs.umich.edu} 2416335Sgblack@eecs.umich.edu 2426335Sgblack@eecs.umich.edutemplate void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc, 2436335Sgblack@eecs.umich.edu StaticInstPtr inst); 2446335Sgblack@eecs.umich.edutemplate void AbortFault<DataAbort>::invoke(ThreadContext *tc, 2456335Sgblack@eecs.umich.edu StaticInstPtr inst); 2466335Sgblack@eecs.umich.edu 2476335Sgblack@eecs.umich.edu// return via SUBS pc, lr, xxx; rfe, movs, ldm 2486335Sgblack@eecs.umich.edu 2496335Sgblack@eecs.umich.edu} // namespace ArmISA 2506335Sgblack@eecs.umich.edu