faults.cc revision 7093 
14202Sbinkertn@umich.edu/*
24202Sbinkertn@umich.edu * Copyright (c) 2010 ARM Limited
34202Sbinkertn@umich.edu * All rights reserved
44202Sbinkertn@umich.edu *
54202Sbinkertn@umich.edu * The license below extends only to copyright in the software and shall
64202Sbinkertn@umich.edu * not be construed as granting a license to any other intellectual
74202Sbinkertn@umich.edu * property including but not limited to intellectual property relating
84202Sbinkertn@umich.edu * to a hardware implementation of the functionality of the software
94202Sbinkertn@umich.edu * licensed hereunder.  You may use the software subject to the license
104202Sbinkertn@umich.edu * terms below provided that you ensure that this notice is replicated
114202Sbinkertn@umich.edu * unmodified and in its entirety in all distributions of the software,
124202Sbinkertn@umich.edu * modified or unmodified, in source code or in binary form.
134202Sbinkertn@umich.edu *
144202Sbinkertn@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan
154202Sbinkertn@umich.edu * Copyright (c) 2007-2008 The Florida State University
164202Sbinkertn@umich.edu * All rights reserved.
174202Sbinkertn@umich.edu *
184202Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without
194202Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are
204202Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright
214202Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer;
224202Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright
234202Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the
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274202Sbinkertn@umich.edu * this software without specific prior written permission.
284202Sbinkertn@umich.edu *
294202Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
304202Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
314202Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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334202Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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354202Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
364202Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
374202Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 */
44
45#include "arch/arm/faults.hh"
46#include "cpu/thread_context.hh"
47#include "cpu/base.hh"
48#include "base/trace.hh"
49
50namespace ArmISA
51{
52
53template<> ArmFaultBase::FaultVals ArmFault<Reset>::vals =
54    {"reset", 0x00, MODE_SVC, 0, 0, true, true};
55
56template<> ArmFaultBase::FaultVals ArmFault<UndefinedInstruction>::vals =
57    {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
58
59template<> ArmFaultBase::FaultVals ArmFault<SupervisorCall>::vals =
60    {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
61
62template<> ArmFaultBase::FaultVals ArmFault<PrefetchAbort>::vals =
63    {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
64
65template<> ArmFaultBase::FaultVals ArmFault<DataAbort>::vals =
66    {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
67
68template<> ArmFaultBase::FaultVals ArmFault<Interrupt>::vals =
69    {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
70
71template<> ArmFaultBase::FaultVals ArmFault<FastInterrupt>::vals =
72    {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
73
74Addr
75ArmFaultBase::getVector(ThreadContext *tc)
76{
77    // ARM ARM B1-3
78
79    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
80
81    // panic if SCTLR.VE because I have no idea what to do with vectored
82    // interrupts
83    assert(!sctlr.ve);
84
85    if (!sctlr.v)
86        return offset();
87    return offset() + HighVecs;
88
89}
90
91#if FULL_SYSTEM
92
93void
94ArmFaultBase::invoke(ThreadContext *tc)
95{
96    // ARM ARM B1.6.3
97    FaultBase::invoke(tc);
98    countStat()++;
99
100    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
101    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
102    CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
103                      tc->readIntReg(INTREG_CONDCODES);
104
105
106    cpsr.mode = nextMode();
107    cpsr.it1 = cpsr.it2 = 0;
108    cpsr.j = 0;
109
110    cpsr.t = sctlr.te;
111    cpsr.a = cpsr.a | abortDisable();
112    cpsr.f = cpsr.f | fiqDisable();
113    cpsr.i = 1;
114    tc->setMiscReg(MISCREG_CPSR, cpsr);
115    tc->setIntReg(INTREG_LR, tc->readPC() +
116            (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
117
118    switch (nextMode()) {
119      case MODE_FIQ:
120        tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
121        break;
122      case MODE_IRQ:
123        tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
124        break;
125      case MODE_SVC:
126        tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
127        break;
128      case MODE_UNDEFINED:
129        tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
130        break;
131      case MODE_ABORT:
132        tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
133        break;
134      default:
135        panic("unknown Mode\n");
136    }
137
138    Addr pc = tc->readPC();
139    DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n",
140            name(), cpsr, pc, tc->readIntReg(INTREG_LR));
141    Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
142    tc->setPC(newPc);
143    tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
144}
145#endif // FULL_SYSTEM
146
147// return via SUBS pc, lr, xxx; rfe, movs, ldm
148
149
150
151} // namespace ArmISA
152
153