faults.cc revision 7093
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 36313Sgblack@eecs.umich.edu * All rights reserved 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 66313Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 76313Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 86313Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 96313Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 106313Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 116313Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 126313Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 136313Sgblack@eecs.umich.edu * 146313Sgblack@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156313Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 166313Sgblack@eecs.umich.edu * All rights reserved. 176313Sgblack@eecs.umich.edu * 186313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 196313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 206313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 216313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 226313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 236313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 246313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 256313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 266313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 276313Sgblack@eecs.umich.edu * this software without specific prior written permission. 286313Sgblack@eecs.umich.edu * 296313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316335Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336335Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346335Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356335Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 378232Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 388232Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406313Sgblack@eecs.umich.edu * 416313Sgblack@eecs.umich.edu * Authors: Ali Saidi 426313Sgblack@eecs.umich.edu * Gabe Black 438829Sgblack@eecs.umich.edu */ 448829Sgblack@eecs.umich.edu 456335Sgblack@eecs.umich.edu#include "arch/arm/faults.hh" 468829Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 478829Sgblack@eecs.umich.edu#include "cpu/base.hh" 488829Sgblack@eecs.umich.edu#include "base/trace.hh" 498829Sgblack@eecs.umich.edu 508829Sgblack@eecs.umich.edunamespace ArmISA 518829Sgblack@eecs.umich.edu{ 528829Sgblack@eecs.umich.edu 538829Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<Reset>::vals = 548829Sgblack@eecs.umich.edu {"reset", 0x00, MODE_SVC, 0, 0, true, true}; 558829Sgblack@eecs.umich.edu 568829Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<UndefinedInstruction>::vals = 578829Sgblack@eecs.umich.edu {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ; 588829Sgblack@eecs.umich.edu 596335Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<SupervisorCall>::vals = 606313Sgblack@eecs.umich.edu {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false}; 616337Sgblack@eecs.umich.edu 626337Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<PrefetchAbort>::vals = 636337Sgblack@eecs.umich.edu {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false}; 646337Sgblack@eecs.umich.edu 656337Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<DataAbort>::vals = 666337Sgblack@eecs.umich.edu {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false}; 676337Sgblack@eecs.umich.edu 686337Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<Interrupt>::vals = 696337Sgblack@eecs.umich.edu {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false}; 706337Sgblack@eecs.umich.edu 716337Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<FastInterrupt>::vals = 726337Sgblack@eecs.umich.edu {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true}; 736337Sgblack@eecs.umich.edu 746337Sgblack@eecs.umich.eduAddr 756337Sgblack@eecs.umich.eduArmFaultBase::getVector(ThreadContext *tc) 766337Sgblack@eecs.umich.edu{ 776337Sgblack@eecs.umich.edu // ARM ARM B1-3 786337Sgblack@eecs.umich.edu 796337Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 806337Sgblack@eecs.umich.edu 816337Sgblack@eecs.umich.edu // panic if SCTLR.VE because I have no idea what to do with vectored 826337Sgblack@eecs.umich.edu // interrupts 836337Sgblack@eecs.umich.edu assert(!sctlr.ve); 846337Sgblack@eecs.umich.edu 856337Sgblack@eecs.umich.edu if (!sctlr.v) 866337Sgblack@eecs.umich.edu return offset(); 876337Sgblack@eecs.umich.edu return offset() + HighVecs; 886337Sgblack@eecs.umich.edu 896337Sgblack@eecs.umich.edu} 906337Sgblack@eecs.umich.edu 916337Sgblack@eecs.umich.edu#if FULL_SYSTEM 926337Sgblack@eecs.umich.edu 936337Sgblack@eecs.umich.eduvoid 946337Sgblack@eecs.umich.eduArmFaultBase::invoke(ThreadContext *tc) 956313Sgblack@eecs.umich.edu{ 966313Sgblack@eecs.umich.edu // ARM ARM B1.6.3 976337Sgblack@eecs.umich.edu FaultBase::invoke(tc); 986337Sgblack@eecs.umich.edu countStat()++; 996337Sgblack@eecs.umich.edu 1006337Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 1017741Sgblack@eecs.umich.edu CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1027741Sgblack@eecs.umich.edu CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | 1036335Sgblack@eecs.umich.edu tc->readIntReg(INTREG_CONDCODES); 1046335Sgblack@eecs.umich.edu 1056335Sgblack@eecs.umich.edu 1066335Sgblack@eecs.umich.edu cpsr.mode = nextMode(); 1076335Sgblack@eecs.umich.edu cpsr.it1 = cpsr.it2 = 0; 1086335Sgblack@eecs.umich.edu cpsr.j = 0; 1096335Sgblack@eecs.umich.edu 1106335Sgblack@eecs.umich.edu cpsr.t = sctlr.te; 1116335Sgblack@eecs.umich.edu cpsr.a = cpsr.a | abortDisable(); 1126335Sgblack@eecs.umich.edu cpsr.f = cpsr.f | fiqDisable(); 1136335Sgblack@eecs.umich.edu cpsr.i = 1; 1146335Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CPSR, cpsr); 1157703Sgblack@eecs.umich.edu tc->setIntReg(INTREG_LR, tc->readPC() + 1166335Sgblack@eecs.umich.edu (saved_cpsr.t ? thumbPcOffset() : armPcOffset())); 1176335Sgblack@eecs.umich.edu 1186335Sgblack@eecs.umich.edu switch (nextMode()) { 1197741Sgblack@eecs.umich.edu case MODE_FIQ: 1207741Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 1217741Sgblack@eecs.umich.edu break; 1227741Sgblack@eecs.umich.edu case MODE_IRQ: 1237741Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 1247741Sgblack@eecs.umich.edu break; 1258829Sgblack@eecs.umich.edu case MODE_SVC: 1268829Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 1276335Sgblack@eecs.umich.edu break; 1286335Sgblack@eecs.umich.edu case MODE_UNDEFINED: 1296335Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 1306335Sgblack@eecs.umich.edu break; 1317741Sgblack@eecs.umich.edu case MODE_ABORT: 1326335Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 1336335Sgblack@eecs.umich.edu break; 1346335Sgblack@eecs.umich.edu default: 1356335Sgblack@eecs.umich.edu panic("unknown Mode\n"); 1366335Sgblack@eecs.umich.edu } 1376335Sgblack@eecs.umich.edu 1386335Sgblack@eecs.umich.edu Addr pc = tc->readPC(); 1396335Sgblack@eecs.umich.edu DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n", 1406335Sgblack@eecs.umich.edu name(), cpsr, pc, tc->readIntReg(INTREG_LR)); 1417703Sgblack@eecs.umich.edu Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0); 1427703Sgblack@eecs.umich.edu tc->setPC(newPc); 1437703Sgblack@eecs.umich.edu tc->setNextPC(newPc + cpsr.t ? 2 : 4 ); 1447703Sgblack@eecs.umich.edu} 1457703Sgblack@eecs.umich.edu#endif // FULL_SYSTEM 1467703Sgblack@eecs.umich.edu 1477703Sgblack@eecs.umich.edu// return via SUBS pc, lr, xxx; rfe, movs, ldm 1487703Sgblack@eecs.umich.edu 1497703Sgblack@eecs.umich.edu 1507703Sgblack@eecs.umich.edu 1517703Sgblack@eecs.umich.edu} // namespace ArmISA 1527703Sgblack@eecs.umich.edu 1537703Sgblack@eecs.umich.edu