faults.cc revision 7412
12SN/A/* 21762SN/A * Copyright (c) 2010 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152SN/A * Copyright (c) 2007-2008 The Florida State University 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 324183Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332439SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342680Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364183Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374183Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384183Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402201SN/A * 412680Sktlim@umich.edu * Authors: Ali Saidi 422201SN/A * Gabe Black 435258Sksewell@umich.edu */ 442201SN/A 452222SN/A#include "arch/arm/faults.hh" 462680Sktlim@umich.edu#include "cpu/thread_context.hh" 472222SN/A#include "cpu/base.hh" 482680Sktlim@umich.edu#include "base/trace.hh" 492680Sktlim@umich.edu 502222SN/Anamespace ArmISA 512680Sktlim@umich.edu{ 522222SN/A 532201SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals = 542612SN/A {"reset", 0x00, MODE_SVC, 0, 0, true, true}; 552680Sktlim@umich.edu 562612SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals = 575258Sksewell@umich.edu {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ; 582612SN/A 595004Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals = 604184Ssaidi@eecs.umich.edu {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false}; 615004Sgblack@eecs.umich.edu 624183Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals = 634183Sgblack@eecs.umich.edu {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false}; 644183Sgblack@eecs.umich.edu 654434Ssaidi@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals = 664183Sgblack@eecs.umich.edu {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false}; 674434Ssaidi@eecs.umich.edu 684183Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = 695004Sgblack@eecs.umich.edu {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false}; 705004Sgblack@eecs.umich.edu 715004Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = 725004Sgblack@eecs.umich.edu {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true}; 735004Sgblack@eecs.umich.edu 744184Ssaidi@eecs.umich.eduAddr 75ArmFault::getVector(ThreadContext *tc) 76{ 77 // ARM ARM B1-3 78 79 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 80 81 // panic if SCTLR.VE because I have no idea what to do with vectored 82 // interrupts 83 assert(!sctlr.ve); 84 85 if (!sctlr.v) 86 return offset(); 87 return offset() + HighVecs; 88 89} 90 91#if FULL_SYSTEM 92 93void 94ArmFault::invoke(ThreadContext *tc) 95{ 96 // ARM ARM B1.6.3 97 FaultBase::invoke(tc); 98 countStat()++; 99 100 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 101 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 102 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | 103 tc->readIntReg(INTREG_CONDCODES); 104 105 106 cpsr.mode = nextMode(); 107 cpsr.it1 = cpsr.it2 = 0; 108 cpsr.j = 0; 109 110 cpsr.t = sctlr.te; 111 cpsr.a = cpsr.a | abortDisable(); 112 cpsr.f = cpsr.f | fiqDisable(); 113 cpsr.i = 1; 114 cpsr.e = sctlr.ee; 115 tc->setMiscReg(MISCREG_CPSR, cpsr); 116 tc->setIntReg(INTREG_LR, tc->readPC() + 117 (saved_cpsr.t ? thumbPcOffset() : armPcOffset())); 118 119 switch (nextMode()) { 120 case MODE_FIQ: 121 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 122 break; 123 case MODE_IRQ: 124 tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 125 break; 126 case MODE_SVC: 127 tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 128 break; 129 case MODE_UNDEFINED: 130 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 131 break; 132 case MODE_ABORT: 133 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 134 break; 135 default: 136 panic("unknown Mode\n"); 137 } 138 139 Addr pc = tc->readPC(); 140 Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0); 141 DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x newVector: %#x\n", 142 name(), cpsr, pc, tc->readIntReg(INTREG_LR), newPc); 143 tc->setPC(newPc); 144 tc->setNextPC(newPc + cpsr.t ? 2 : 4 ); 145 tc->setMicroPC(0); 146 tc->setNextMicroPC(1); 147} 148 149void 150Reset::invoke(ThreadContext *tc) 151{ 152 tc->getCpuPtr()->clearInterrupts(); 153 tc->clearArchRegs(); 154 ArmFault::invoke(tc); 155} 156 157#else 158 159void 160UndefinedInstruction::invoke(ThreadContext *tc) 161{ 162 assert(unknown || mnemonic != NULL); 163 if (unknown) { 164 panic("Attempted to execute unknown instruction " 165 "(inst 0x%08x, opcode 0x%x, binary:%s)", 166 machInst, machInst.opcode, inst2string(machInst)); 167 } else { 168 panic("Attempted to execute unimplemented instruction '%s' " 169 "(inst 0x%08x, opcode 0x%x, binary:%s)", 170 mnemonic, machInst, machInst.opcode, inst2string(machInst)); 171 } 172} 173 174void 175SupervisorCall::invoke(ThreadContext *tc) 176{ 177 // As of now, there isn't a 32 bit thumb version of this instruction. 178 assert(!machInst.bigThumb); 179 uint32_t callNum; 180 if (machInst.thumb) { 181 callNum = bits(machInst, 7, 0); 182 } else { 183 callNum = bits(machInst, 23, 0); 184 } 185 if (callNum == 0) { 186 callNum = tc->readIntReg(INTREG_R7); 187 } 188 tc->syscall(callNum); 189 190 // Advance the PC since that won't happen automatically. 191 tc->setPC(tc->readNextPC()); 192 tc->setNextPC(tc->readNextNPC()); 193 tc->setMicroPC(0); 194 tc->setNextMicroPC(1); 195} 196 197#endif // FULL_SYSTEM 198 199template<class T> 200void 201AbortFault<T>::invoke(ThreadContext *tc) 202{ 203 ArmFaultVals<T>::invoke(tc); 204 FSR fsr = 0; 205 fsr.fsLow = bits(status, 3, 0); 206 fsr.fsHigh = bits(status, 4); 207 fsr.domain = domain; 208 fsr.wnr = (write ? 1 : 0); 209 fsr.ext = 0; 210 tc->setMiscReg(T::FsrIndex, fsr); 211 tc->setMiscReg(T::FarIndex, faultAddr); 212} 213 214template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc); 215template void AbortFault<DataAbort>::invoke(ThreadContext *tc); 216 217// return via SUBS pc, lr, xxx; rfe, movs, ldm 218 219 220 221} // namespace ArmISA 222 223