faults.cc revision 14128
16019Shines@cs.fsu.edu/* 214128Sgiacomo.travaglini@arm.com * Copyright (c) 2010, 2012-2014, 2016-2019 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416735Sgblack@eecs.umich.edu * Authors: Ali Saidi 426735Sgblack@eecs.umich.edu * Gabe Black 4310037SARM gem5 Developers * Giacomo Gabrielli 4410037SARM gem5 Developers * Thomas Grocutt 456019Shines@cs.fsu.edu */ 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#include "arch/arm/faults.hh" 4811793Sbrandon.potter@amd.com 4911793Sbrandon.potter@amd.com#include "arch/arm/insts/static_inst.hh" 5010037SARM gem5 Developers#include "arch/arm/system.hh" 5110037SARM gem5 Developers#include "arch/arm/utility.hh" 5210037SARM gem5 Developers#include "base/compiler.hh" 538229Snate@binkert.org#include "base/trace.hh" 548229Snate@binkert.org#include "cpu/base.hh" 556019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 568232Snate@binkert.org#include "debug/Faults.hh" 578782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edunamespace ArmISA 606019Shines@cs.fsu.edu{ 616019Shines@cs.fsu.edu 6210037SARM gem5 Developersuint8_t ArmFault::shortDescFaultSources[] = { 6310037SARM gem5 Developers 0x01, // AlignmentFault 6410037SARM gem5 Developers 0x04, // InstructionCacheMaintenance 6510037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 6610037SARM gem5 Developers 0x0c, // SynchExtAbtOnTranslTableWalkL1 6710037SARM gem5 Developers 0x0e, // SynchExtAbtOnTranslTableWalkL2 6810037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID) 6910037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 7010037SARM gem5 Developers 0x1c, // SynchPtyErrOnTranslTableWalkL1 7110037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 7210037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID) 7310037SARM gem5 Developers 0xff, // TranslationL0 (INVALID) 7410037SARM gem5 Developers 0x05, // TranslationL1 7510037SARM gem5 Developers 0x07, // TranslationL2 7610037SARM gem5 Developers 0xff, // TranslationL3 (INVALID) 7710037SARM gem5 Developers 0xff, // AccessFlagL0 (INVALID) 7810037SARM gem5 Developers 0x03, // AccessFlagL1 7910037SARM gem5 Developers 0x06, // AccessFlagL2 8010037SARM gem5 Developers 0xff, // AccessFlagL3 (INVALID) 8110037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 8210037SARM gem5 Developers 0x09, // DomainL1 8310037SARM gem5 Developers 0x0b, // DomainL2 8410037SARM gem5 Developers 0xff, // DomainL3 (INVALID) 8510037SARM gem5 Developers 0xff, // PermissionL0 (INVALID) 8610037SARM gem5 Developers 0x0d, // PermissionL1 8710037SARM gem5 Developers 0x0f, // PermissionL2 8810037SARM gem5 Developers 0xff, // PermissionL3 (INVALID) 8910037SARM gem5 Developers 0x02, // DebugEvent 9010037SARM gem5 Developers 0x08, // SynchronousExternalAbort 9110037SARM gem5 Developers 0x10, // TLBConflictAbort 9210037SARM gem5 Developers 0x19, // SynchPtyErrOnMemoryAccess 9310037SARM gem5 Developers 0x16, // AsynchronousExternalAbort 9410037SARM gem5 Developers 0x18, // AsynchPtyErrOnMemoryAccess 9510037SARM gem5 Developers 0xff, // AddressSizeL0 (INVALID) 9610037SARM gem5 Developers 0xff, // AddressSizeL1 (INVALID) 9710037SARM gem5 Developers 0xff, // AddressSizeL2 (INVALID) 9810037SARM gem5 Developers 0xff, // AddressSizeL3 (INVALID) 9910037SARM gem5 Developers 0x40, // PrefetchTLBMiss 10010037SARM gem5 Developers 0x80 // PrefetchUncacheable 10110037SARM gem5 Developers}; 1026019Shines@cs.fsu.edu 10310037SARM gem5 Developersstatic_assert(sizeof(ArmFault::shortDescFaultSources) == 10410037SARM gem5 Developers ArmFault::NumFaultSources, 10510037SARM gem5 Developers "Invalid size of ArmFault::shortDescFaultSources[]"); 1066019Shines@cs.fsu.edu 10710037SARM gem5 Developersuint8_t ArmFault::longDescFaultSources[] = { 10810037SARM gem5 Developers 0x21, // AlignmentFault 10910037SARM gem5 Developers 0xff, // InstructionCacheMaintenance (INVALID) 11010037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 11110037SARM gem5 Developers 0x15, // SynchExtAbtOnTranslTableWalkL1 11210037SARM gem5 Developers 0x16, // SynchExtAbtOnTranslTableWalkL2 11310037SARM gem5 Developers 0x17, // SynchExtAbtOnTranslTableWalkL3 11410037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 11510037SARM gem5 Developers 0x1d, // SynchPtyErrOnTranslTableWalkL1 11610037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 11710037SARM gem5 Developers 0x1f, // SynchPtyErrOnTranslTableWalkL3 11810037SARM gem5 Developers 0xff, // TranslationL0 (INVALID) 11910037SARM gem5 Developers 0x05, // TranslationL1 12010037SARM gem5 Developers 0x06, // TranslationL2 12110037SARM gem5 Developers 0x07, // TranslationL3 12210037SARM gem5 Developers 0xff, // AccessFlagL0 (INVALID) 12310037SARM gem5 Developers 0x09, // AccessFlagL1 12410037SARM gem5 Developers 0x0a, // AccessFlagL2 12510037SARM gem5 Developers 0x0b, // AccessFlagL3 12610037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 12710037SARM gem5 Developers 0x3d, // DomainL1 12810037SARM gem5 Developers 0x3e, // DomainL2 12910037SARM gem5 Developers 0xff, // DomainL3 (RESERVED) 13010037SARM gem5 Developers 0xff, // PermissionL0 (INVALID) 13110037SARM gem5 Developers 0x0d, // PermissionL1 13210037SARM gem5 Developers 0x0e, // PermissionL2 13310037SARM gem5 Developers 0x0f, // PermissionL3 13410037SARM gem5 Developers 0x22, // DebugEvent 13510037SARM gem5 Developers 0x10, // SynchronousExternalAbort 13610037SARM gem5 Developers 0x30, // TLBConflictAbort 13710037SARM gem5 Developers 0x18, // SynchPtyErrOnMemoryAccess 13810037SARM gem5 Developers 0x11, // AsynchronousExternalAbort 13910037SARM gem5 Developers 0x19, // AsynchPtyErrOnMemoryAccess 14010037SARM gem5 Developers 0xff, // AddressSizeL0 (INVALID) 14110037SARM gem5 Developers 0xff, // AddressSizeL1 (INVALID) 14210037SARM gem5 Developers 0xff, // AddressSizeL2 (INVALID) 14310037SARM gem5 Developers 0xff, // AddressSizeL3 (INVALID) 14410037SARM gem5 Developers 0x40, // PrefetchTLBMiss 14510037SARM gem5 Developers 0x80 // PrefetchUncacheable 14610037SARM gem5 Developers}; 1476019Shines@cs.fsu.edu 14810037SARM gem5 Developersstatic_assert(sizeof(ArmFault::longDescFaultSources) == 14910037SARM gem5 Developers ArmFault::NumFaultSources, 15010037SARM gem5 Developers "Invalid size of ArmFault::longDescFaultSources[]"); 1516019Shines@cs.fsu.edu 15210037SARM gem5 Developersuint8_t ArmFault::aarch64FaultSources[] = { 15310037SARM gem5 Developers 0x21, // AlignmentFault 15410037SARM gem5 Developers 0xff, // InstructionCacheMaintenance (INVALID) 15510037SARM gem5 Developers 0x14, // SynchExtAbtOnTranslTableWalkL0 15610037SARM gem5 Developers 0x15, // SynchExtAbtOnTranslTableWalkL1 15710037SARM gem5 Developers 0x16, // SynchExtAbtOnTranslTableWalkL2 15810037SARM gem5 Developers 0x17, // SynchExtAbtOnTranslTableWalkL3 15910037SARM gem5 Developers 0x1c, // SynchPtyErrOnTranslTableWalkL0 16010037SARM gem5 Developers 0x1d, // SynchPtyErrOnTranslTableWalkL1 16110037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 16210037SARM gem5 Developers 0x1f, // SynchPtyErrOnTranslTableWalkL3 16310037SARM gem5 Developers 0x04, // TranslationL0 16410037SARM gem5 Developers 0x05, // TranslationL1 16510037SARM gem5 Developers 0x06, // TranslationL2 16610037SARM gem5 Developers 0x07, // TranslationL3 16710037SARM gem5 Developers 0x08, // AccessFlagL0 16810037SARM gem5 Developers 0x09, // AccessFlagL1 16910037SARM gem5 Developers 0x0a, // AccessFlagL2 17010037SARM gem5 Developers 0x0b, // AccessFlagL3 17110037SARM gem5 Developers // @todo: Section & Page Domain Fault in AArch64? 17210037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 17310037SARM gem5 Developers 0xff, // DomainL1 (INVALID) 17410037SARM gem5 Developers 0xff, // DomainL2 (INVALID) 17510037SARM gem5 Developers 0xff, // DomainL3 (INVALID) 17610037SARM gem5 Developers 0x0c, // PermissionL0 17710037SARM gem5 Developers 0x0d, // PermissionL1 17810037SARM gem5 Developers 0x0e, // PermissionL2 17910037SARM gem5 Developers 0x0f, // PermissionL3 18012571Sgiacomo.travaglini@arm.com 0x22, // DebugEvent 18110037SARM gem5 Developers 0x10, // SynchronousExternalAbort 18210037SARM gem5 Developers 0x30, // TLBConflictAbort 18310037SARM gem5 Developers 0x18, // SynchPtyErrOnMemoryAccess 18410037SARM gem5 Developers 0xff, // AsynchronousExternalAbort (INVALID) 18510037SARM gem5 Developers 0xff, // AsynchPtyErrOnMemoryAccess (INVALID) 18610037SARM gem5 Developers 0x00, // AddressSizeL0 18710037SARM gem5 Developers 0x01, // AddressSizeL1 18810037SARM gem5 Developers 0x02, // AddressSizeL2 18910037SARM gem5 Developers 0x03, // AddressSizeL3 19010037SARM gem5 Developers 0x40, // PrefetchTLBMiss 19110037SARM gem5 Developers 0x80 // PrefetchUncacheable 19210037SARM gem5 Developers}; 1936019Shines@cs.fsu.edu 19410037SARM gem5 Developersstatic_assert(sizeof(ArmFault::aarch64FaultSources) == 19510037SARM gem5 Developers ArmFault::NumFaultSources, 19610037SARM gem5 Developers "Invalid size of ArmFault::aarch64FaultSources[]"); 1976019Shines@cs.fsu.edu 19810037SARM gem5 Developers// Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode, 19910037SARM gem5 Developers// {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap, 20010037SARM gem5 Developers// {A, F} disable, class, stat 20112517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals( 20210037SARM gem5 Developers // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED 20310037SARM gem5 Developers // location in AArch64) 20410037SARM gem5 Developers "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 20512517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, true, true, EC_UNKNOWN 20612517Srekai.gonzalezalberquilla@arm.com); 20712517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals( 20810037SARM gem5 Developers "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 20912517Srekai.gonzalezalberquilla@arm.com 4, 2, 0, 0, true, false, false, EC_UNKNOWN 21012517Srekai.gonzalezalberquilla@arm.com); 21112517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals( 21210037SARM gem5 Developers "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 21312517Srekai.gonzalezalberquilla@arm.com 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP 21412517Srekai.gonzalezalberquilla@arm.com); 21512517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals( 21610037SARM gem5 Developers "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 21712517Srekai.gonzalezalberquilla@arm.com 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP 21812517Srekai.gonzalezalberquilla@arm.com); 21912517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals( 22010037SARM gem5 Developers "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 22112517Srekai.gonzalezalberquilla@arm.com 4, 4, 4, 4, true, false, false, EC_HVC 22212517Srekai.gonzalezalberquilla@arm.com); 22312517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals( 22410037SARM gem5 Developers "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 22512517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP 22612517Srekai.gonzalezalberquilla@arm.com); 22712517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals( 22810037SARM gem5 Developers "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 22912517Srekai.gonzalezalberquilla@arm.com 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP 23012517Srekai.gonzalezalberquilla@arm.com); 23112517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals( 23210037SARM gem5 Developers "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 23312517Srekai.gonzalezalberquilla@arm.com 8, 8, 0, 0, true, true, false, EC_INVALID 23412517Srekai.gonzalezalberquilla@arm.com); 23512517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals( 23610037SARM gem5 Developers // @todo: double check these values 23710037SARM gem5 Developers "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 23812517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, false, false, EC_UNKNOWN 23912517Srekai.gonzalezalberquilla@arm.com); 24012517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals( 24112512Sgiacomo.travaglini@arm.com "Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON, 24212517Srekai.gonzalezalberquilla@arm.com 4, 2, 0, 0, false, false, false, EC_UNKNOWN 24312517Srekai.gonzalezalberquilla@arm.com); 24412517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals( 24510037SARM gem5 Developers "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 24612517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, false, true, false, EC_UNKNOWN 24712517Srekai.gonzalezalberquilla@arm.com); 24812517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals( 24910037SARM gem5 Developers "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 25012517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, false, true, false, EC_INVALID 25112517Srekai.gonzalezalberquilla@arm.com); 25212517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals( 25310037SARM gem5 Developers "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 25412517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, false, true, true, EC_UNKNOWN 25512517Srekai.gonzalezalberquilla@arm.com); 25612517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals( 25710037SARM gem5 Developers "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 25812517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, false, true, true, EC_INVALID 25912517Srekai.gonzalezalberquilla@arm.com); 26012764Sgiacomo.travaglini@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals( 26112764Sgiacomo.travaglini@arm.com "Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 26212764Sgiacomo.travaglini@arm.com 4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST 26312764Sgiacomo.travaglini@arm.com); 26412517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals( 26510037SARM gem5 Developers // Some dummy values (SupervisorTrap is AArch64-only) 26610037SARM gem5 Developers "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 26712517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, false, false, EC_UNKNOWN 26812517Srekai.gonzalezalberquilla@arm.com); 26912517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals( 27010037SARM gem5 Developers // Some dummy values (PCAlignmentFault is AArch64-only) 27110037SARM gem5 Developers "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 27212517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT 27312517Srekai.gonzalezalberquilla@arm.com); 27412517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals( 27510037SARM gem5 Developers // Some dummy values (SPAlignmentFault is AArch64-only) 27610037SARM gem5 Developers "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 27712517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT 27812517Srekai.gonzalezalberquilla@arm.com); 27912517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals( 28010037SARM gem5 Developers // Some dummy values (SError is AArch64-only) 28110037SARM gem5 Developers "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 28212517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, true, true, EC_SERROR 28312517Srekai.gonzalezalberquilla@arm.com); 28412517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals( 28512299Sandreas.sandberg@arm.com // Some dummy values (SoftwareBreakpoint is AArch64-only) 28612299Sandreas.sandberg@arm.com "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 28712517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT 28812517Srekai.gonzalezalberquilla@arm.com); 28912517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals( 29010037SARM gem5 Developers // Some dummy values 29110037SARM gem5 Developers "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 29212517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, true, true, EC_UNKNOWN 29312517Srekai.gonzalezalberquilla@arm.com); 2946019Shines@cs.fsu.edu 29510037SARM gem5 DevelopersAddr 2967362Sgblack@eecs.umich.eduArmFault::getVector(ThreadContext *tc) 2976735Sgblack@eecs.umich.edu{ 29810037SARM gem5 Developers Addr base; 2996019Shines@cs.fsu.edu 30010037SARM gem5 Developers // Check for invalid modes 30110037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 30213396Sgiacomo.travaglini@arm.com assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON); 30310037SARM gem5 Developers assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); 3047400SAli.Saidi@ARM.com 30510037SARM gem5 Developers switch (cpsr.mode) 30610037SARM gem5 Developers { 30710037SARM gem5 Developers case MODE_MON: 30810037SARM gem5 Developers base = tc->readMiscReg(MISCREG_MVBAR); 30910037SARM gem5 Developers break; 31010037SARM gem5 Developers case MODE_HYP: 31110037SARM gem5 Developers base = tc->readMiscReg(MISCREG_HVBAR); 31210037SARM gem5 Developers break; 31310037SARM gem5 Developers default: 31413394Sgiacomo.travaglini@arm.com SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 31510037SARM gem5 Developers if (sctlr.v) { 31610037SARM gem5 Developers base = HighVecs; 31710037SARM gem5 Developers } else { 31813396Sgiacomo.travaglini@arm.com base = ArmSystem::haveSecurity(tc) ? 31913396Sgiacomo.travaglini@arm.com tc->readMiscReg(MISCREG_VBAR) : 0; 32010037SARM gem5 Developers } 32110037SARM gem5 Developers break; 32210037SARM gem5 Developers } 32313396Sgiacomo.travaglini@arm.com 32410037SARM gem5 Developers return base + offset(tc); 3256019Shines@cs.fsu.edu} 3266019Shines@cs.fsu.edu 32710037SARM gem5 DevelopersAddr 32810037SARM gem5 DevelopersArmFault::getVector64(ThreadContext *tc) 32910037SARM gem5 Developers{ 33010037SARM gem5 Developers Addr vbar; 33110037SARM gem5 Developers switch (toEL) { 33210037SARM gem5 Developers case EL3: 33310037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 33410037SARM gem5 Developers vbar = tc->readMiscReg(MISCREG_VBAR_EL3); 33510037SARM gem5 Developers break; 33611574SCurtis.Dunham@arm.com case EL2: 33711574SCurtis.Dunham@arm.com assert(ArmSystem::haveVirtualization(tc)); 33811574SCurtis.Dunham@arm.com vbar = tc->readMiscReg(MISCREG_VBAR_EL2); 33911574SCurtis.Dunham@arm.com break; 34010037SARM gem5 Developers case EL1: 34110037SARM gem5 Developers vbar = tc->readMiscReg(MISCREG_VBAR_EL1); 34210037SARM gem5 Developers break; 34310037SARM gem5 Developers default: 34410037SARM gem5 Developers panic("Invalid target exception level"); 34510037SARM gem5 Developers break; 34610037SARM gem5 Developers } 34712511Schuan.zhu@arm.com return vbar + offset64(tc); 34810037SARM gem5 Developers} 34910037SARM gem5 Developers 35010037SARM gem5 DevelopersMiscRegIndex 35110037SARM gem5 DevelopersArmFault::getSyndromeReg64() const 35210037SARM gem5 Developers{ 35310037SARM gem5 Developers switch (toEL) { 35410037SARM gem5 Developers case EL1: 35510037SARM gem5 Developers return MISCREG_ESR_EL1; 35610037SARM gem5 Developers case EL2: 35710037SARM gem5 Developers return MISCREG_ESR_EL2; 35810037SARM gem5 Developers case EL3: 35910037SARM gem5 Developers return MISCREG_ESR_EL3; 36010037SARM gem5 Developers default: 36110037SARM gem5 Developers panic("Invalid exception level"); 36210037SARM gem5 Developers break; 36310037SARM gem5 Developers } 36410037SARM gem5 Developers} 36510037SARM gem5 Developers 36610037SARM gem5 DevelopersMiscRegIndex 36710037SARM gem5 DevelopersArmFault::getFaultAddrReg64() const 36810037SARM gem5 Developers{ 36910037SARM gem5 Developers switch (toEL) { 37010037SARM gem5 Developers case EL1: 37110037SARM gem5 Developers return MISCREG_FAR_EL1; 37210037SARM gem5 Developers case EL2: 37310037SARM gem5 Developers return MISCREG_FAR_EL2; 37410037SARM gem5 Developers case EL3: 37510037SARM gem5 Developers return MISCREG_FAR_EL3; 37610037SARM gem5 Developers default: 37710037SARM gem5 Developers panic("Invalid exception level"); 37810037SARM gem5 Developers break; 37910037SARM gem5 Developers } 38010037SARM gem5 Developers} 38110037SARM gem5 Developers 38210037SARM gem5 Developersvoid 38310037SARM gem5 DevelopersArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 38410037SARM gem5 Developers{ 38510037SARM gem5 Developers uint32_t value; 38610037SARM gem5 Developers uint32_t exc_class = (uint32_t) ec(tc); 38710037SARM gem5 Developers uint32_t issVal = iss(); 38812402Sgiacomo.travaglini@arm.com 38910037SARM gem5 Developers assert(!from64 || ArmSystem::highestELIs64(tc)); 39010037SARM gem5 Developers 39110037SARM gem5 Developers value = exc_class << 26; 39210037SARM gem5 Developers 39310037SARM gem5 Developers // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24, 39410037SARM gem5 Developers // 0x25) for which the ISS information is not valid (ARMv7). 39510037SARM gem5 Developers // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not 39610037SARM gem5 Developers // valid it is treated as RES1. 39710037SARM gem5 Developers if (to64) { 39810037SARM gem5 Developers value |= 1 << 25; 39910037SARM gem5 Developers } else if ((bits(exc_class, 5, 3) != 4) || 40010037SARM gem5 Developers (bits(exc_class, 2) && bits(issVal, 24))) { 40110037SARM gem5 Developers if (!machInst.thumb || machInst.bigThumb) 40210037SARM gem5 Developers value |= 1 << 25; 40310037SARM gem5 Developers } 40410037SARM gem5 Developers // Condition code valid for EC[5:4] nonzero 40510037SARM gem5 Developers if (!from64 && ((bits(exc_class, 5, 4) == 0) && 40610037SARM gem5 Developers (bits(exc_class, 3, 0) != 0))) { 40710037SARM gem5 Developers if (!machInst.thumb) { 40810037SARM gem5 Developers uint32_t cond; 40910037SARM gem5 Developers ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode; 41010037SARM gem5 Developers // If its on unconditional instruction report with a cond code of 41110037SARM gem5 Developers // 0xE, ie the unconditional code 41210037SARM gem5 Developers cond = (condCode == COND_UC) ? COND_AL : condCode; 41310037SARM gem5 Developers value |= cond << 20; 41410037SARM gem5 Developers value |= 1 << 24; 41510037SARM gem5 Developers } 41610037SARM gem5 Developers value |= bits(issVal, 19, 0); 41710037SARM gem5 Developers } else { 41810037SARM gem5 Developers value |= issVal; 41910037SARM gem5 Developers } 42010037SARM gem5 Developers tc->setMiscReg(syndrome_reg, value); 42110037SARM gem5 Developers} 42210037SARM gem5 Developers 42310037SARM gem5 Developersvoid 42412569Sgiacomo.travaglini@arm.comArmFault::update(ThreadContext *tc) 4256019Shines@cs.fsu.edu{ 42610037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 42710037SARM gem5 Developers 42812569Sgiacomo.travaglini@arm.com // Determine source exception level and mode 42912569Sgiacomo.travaglini@arm.com fromMode = (OperatingMode) (uint8_t) cpsr.mode; 43012569Sgiacomo.travaglini@arm.com fromEL = opModeToEL(fromMode); 43112569Sgiacomo.travaglini@arm.com if (opModeIs64(fromMode)) 43212569Sgiacomo.travaglini@arm.com from64 = true; 43310037SARM gem5 Developers 43412569Sgiacomo.travaglini@arm.com // Determine target exception level (aarch64) or target execution 43512569Sgiacomo.travaglini@arm.com // mode (aarch32). 43612569Sgiacomo.travaglini@arm.com if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) { 43712569Sgiacomo.travaglini@arm.com toMode = MODE_MON; 43812569Sgiacomo.travaglini@arm.com toEL = EL3; 43912569Sgiacomo.travaglini@arm.com } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) { 44012569Sgiacomo.travaglini@arm.com toMode = MODE_HYP; 44112569Sgiacomo.travaglini@arm.com toEL = EL2; 44212569Sgiacomo.travaglini@arm.com hypRouted = true; 44312569Sgiacomo.travaglini@arm.com } else { 44412569Sgiacomo.travaglini@arm.com toMode = nextMode(); 44512569Sgiacomo.travaglini@arm.com toEL = opModeToEL(toMode); 44612569Sgiacomo.travaglini@arm.com } 44712402Sgiacomo.travaglini@arm.com 44812569Sgiacomo.travaglini@arm.com if (fromEL > toEL) 44912569Sgiacomo.travaglini@arm.com toEL = fromEL; 45010037SARM gem5 Developers 45114128Sgiacomo.travaglini@arm.com // Check for Set Priviledge Access Never, if PAN is supported 45214128Sgiacomo.travaglini@arm.com AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1); 45314128Sgiacomo.travaglini@arm.com if (mmfr1.pan) { 45414128Sgiacomo.travaglini@arm.com if (toEL == EL1) { 45514128Sgiacomo.travaglini@arm.com const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 45614128Sgiacomo.travaglini@arm.com span = !sctlr.span; 45714128Sgiacomo.travaglini@arm.com } 45814128Sgiacomo.travaglini@arm.com 45914128Sgiacomo.travaglini@arm.com const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 46014128Sgiacomo.travaglini@arm.com if (toEL == EL2 && hcr.e2h && hcr.tge) { 46114128Sgiacomo.travaglini@arm.com const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2); 46214128Sgiacomo.travaglini@arm.com span = !sctlr.span; 46314128Sgiacomo.travaglini@arm.com } 46414128Sgiacomo.travaglini@arm.com } 46514128Sgiacomo.travaglini@arm.com 46612569Sgiacomo.travaglini@arm.com to64 = ELIs64(tc, toEL); 46712569Sgiacomo.travaglini@arm.com 46812569Sgiacomo.travaglini@arm.com // The fault specific informations have been updated; it is 46912569Sgiacomo.travaglini@arm.com // now possible to use them inside the fault. 47012569Sgiacomo.travaglini@arm.com faultUpdated = true; 47112569Sgiacomo.travaglini@arm.com} 47212569Sgiacomo.travaglini@arm.com 47312569Sgiacomo.travaglini@arm.comvoid 47412569Sgiacomo.travaglini@arm.comArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 47512569Sgiacomo.travaglini@arm.com{ 47612569Sgiacomo.travaglini@arm.com 47712569Sgiacomo.travaglini@arm.com // Update fault state informations, like the starting mode (aarch32) 47812569Sgiacomo.travaglini@arm.com // or EL (aarch64) and the ending mode or EL. 47912569Sgiacomo.travaglini@arm.com // From the update function we are also evaluating if the fault must 48012569Sgiacomo.travaglini@arm.com // be handled in AArch64 mode (to64). 48112569Sgiacomo.travaglini@arm.com update(tc); 48212569Sgiacomo.travaglini@arm.com 48312569Sgiacomo.travaglini@arm.com if (to64) { 48412569Sgiacomo.travaglini@arm.com // Invoke exception handler in AArch64 state 48512569Sgiacomo.travaglini@arm.com invoke64(tc, inst); 48612569Sgiacomo.travaglini@arm.com return; 48710037SARM gem5 Developers } 48810037SARM gem5 Developers 48910037SARM gem5 Developers // ARMv7 (ARM ARM issue C B1.9) 49010037SARM gem5 Developers 49110037SARM gem5 Developers bool have_security = ArmSystem::haveSecurity(tc); 49210037SARM gem5 Developers 4936735Sgblack@eecs.umich.edu FaultBase::invoke(tc); 4948782Sgblack@eecs.umich.edu if (!FullSystem) 4958782Sgblack@eecs.umich.edu return; 4966735Sgblack@eecs.umich.edu countStat()++; 4976019Shines@cs.fsu.edu 4986735Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 49910037SARM gem5 Developers SCR scr = tc->readMiscReg(MISCREG_SCR); 5008303SAli.Saidi@ARM.com CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR); 50110338SCurtis.Dunham@arm.com saved_cpsr.nz = tc->readCCReg(CCREG_NZ); 50210338SCurtis.Dunham@arm.com saved_cpsr.c = tc->readCCReg(CCREG_C); 50310338SCurtis.Dunham@arm.com saved_cpsr.v = tc->readCCReg(CCREG_V); 50410338SCurtis.Dunham@arm.com saved_cpsr.ge = tc->readCCReg(CCREG_GE); 5058303SAli.Saidi@ARM.com 5067720Sgblack@eecs.umich.edu Addr curPc M5_VAR_USED = tc->pcState().pc(); 5078205SAli.Saidi@ARM.com ITSTATE it = tc->pcState().itstate(); 5088205SAli.Saidi@ARM.com saved_cpsr.it2 = it.top6; 5098205SAli.Saidi@ARM.com saved_cpsr.it1 = it.bottom2; 5106735Sgblack@eecs.umich.edu 51110037SARM gem5 Developers // if we have a valid instruction then use it to annotate this fault with 51210037SARM gem5 Developers // extra information. This is used to generate the correct fault syndrome 51310037SARM gem5 Developers // information 51413896Sgiacomo.travaglini@arm.com ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst); 51510037SARM gem5 Developers 51610037SARM gem5 Developers // Ensure Secure state if initially in Monitor mode 51710037SARM gem5 Developers if (have_security && saved_cpsr.mode == MODE_MON) { 51810037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 51910037SARM gem5 Developers if (scr.ns) { 52010037SARM gem5 Developers scr.ns = 0; 52110037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_SCR, scr); 52210037SARM gem5 Developers } 52310037SARM gem5 Developers } 52410037SARM gem5 Developers 52512569Sgiacomo.travaglini@arm.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 52612569Sgiacomo.travaglini@arm.com cpsr.mode = toMode; 52712569Sgiacomo.travaglini@arm.com 52810037SARM gem5 Developers // some bits are set differently if we have been routed to hyp mode 52910037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 53010037SARM gem5 Developers SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR); 53110037SARM gem5 Developers cpsr.t = hsctlr.te; 53210037SARM gem5 Developers cpsr.e = hsctlr.ee; 53310037SARM gem5 Developers if (!scr.ea) {cpsr.a = 1;} 53410037SARM gem5 Developers if (!scr.fiq) {cpsr.f = 1;} 53510037SARM gem5 Developers if (!scr.irq) {cpsr.i = 1;} 53610037SARM gem5 Developers } else if (cpsr.mode == MODE_MON) { 53710037SARM gem5 Developers // Special case handling when entering monitor mode 53810037SARM gem5 Developers cpsr.t = sctlr.te; 53910037SARM gem5 Developers cpsr.e = sctlr.ee; 54010037SARM gem5 Developers cpsr.a = 1; 54110037SARM gem5 Developers cpsr.f = 1; 54210037SARM gem5 Developers cpsr.i = 1; 54310037SARM gem5 Developers } else { 54410037SARM gem5 Developers cpsr.t = sctlr.te; 54510037SARM gem5 Developers cpsr.e = sctlr.ee; 54610037SARM gem5 Developers 54710037SARM gem5 Developers // The *Disable functions are virtual and different per fault 54810037SARM gem5 Developers cpsr.a = cpsr.a | abortDisable(tc); 54910037SARM gem5 Developers cpsr.f = cpsr.f | fiqDisable(tc); 55010037SARM gem5 Developers cpsr.i = 1; 55110037SARM gem5 Developers } 5526735Sgblack@eecs.umich.edu cpsr.it1 = cpsr.it2 = 0; 5536735Sgblack@eecs.umich.edu cpsr.j = 0; 55414128Sgiacomo.travaglini@arm.com cpsr.pan = span ? 1 : saved_cpsr.pan; 5556735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CPSR, cpsr); 55610037SARM gem5 Developers 5578518Sgeoffrey.blake@arm.com // Make sure mailbox sets to one always 5588518Sgeoffrey.blake@arm.com tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 5596735Sgblack@eecs.umich.edu 56010037SARM gem5 Developers // Clear the exclusive monitor 56110037SARM gem5 Developers tc->setMiscReg(MISCREG_LOCKFLAG, 0); 56210037SARM gem5 Developers 56310037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 56410037SARM gem5 Developers tc->setMiscReg(MISCREG_ELR_HYP, curPc + 56510037SARM gem5 Developers (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true))); 56610037SARM gem5 Developers } else { 56710037SARM gem5 Developers tc->setIntReg(INTREG_LR, curPc + 56810037SARM gem5 Developers (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false))); 56910037SARM gem5 Developers } 57010037SARM gem5 Developers 57110037SARM gem5 Developers switch (cpsr.mode) { 5726735Sgblack@eecs.umich.edu case MODE_FIQ: 5736735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 5746735Sgblack@eecs.umich.edu break; 5756735Sgblack@eecs.umich.edu case MODE_IRQ: 5766735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 5776735Sgblack@eecs.umich.edu break; 5786735Sgblack@eecs.umich.edu case MODE_SVC: 5796735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 5806735Sgblack@eecs.umich.edu break; 58110037SARM gem5 Developers case MODE_MON: 58210037SARM gem5 Developers assert(have_security); 58310037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr); 5846735Sgblack@eecs.umich.edu break; 5856735Sgblack@eecs.umich.edu case MODE_ABORT: 5866735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 5876735Sgblack@eecs.umich.edu break; 58810037SARM gem5 Developers case MODE_UNDEFINED: 58910037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 59010037SARM gem5 Developers if (ec(tc) != EC_UNKNOWN) 59110037SARM gem5 Developers setSyndrome(tc, MISCREG_HSR); 59210037SARM gem5 Developers break; 59310037SARM gem5 Developers case MODE_HYP: 59412589Snikos.nikoleris@arm.com assert(ArmSystem::haveVirtualization(tc)); 59510037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr); 59610037SARM gem5 Developers setSyndrome(tc, MISCREG_HSR); 59710037SARM gem5 Developers break; 5986735Sgblack@eecs.umich.edu default: 5996735Sgblack@eecs.umich.edu panic("unknown Mode\n"); 6007093Sgblack@eecs.umich.edu } 6017093Sgblack@eecs.umich.edu 6027720Sgblack@eecs.umich.edu Addr newPc = getVector(tc); 60313896Sgiacomo.travaglini@arm.com DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x " 60413896Sgiacomo.travaglini@arm.com "%s\n", name(), cpsr, curPc, tc->readIntReg(INTREG_LR), 60513896Sgiacomo.travaglini@arm.com newPc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) : 60613896Sgiacomo.travaglini@arm.com std::string()); 6077720Sgblack@eecs.umich.edu PCState pc(newPc); 6087720Sgblack@eecs.umich.edu pc.thumb(cpsr.t); 6097720Sgblack@eecs.umich.edu pc.nextThumb(pc.thumb()); 6107720Sgblack@eecs.umich.edu pc.jazelle(cpsr.j); 6117720Sgblack@eecs.umich.edu pc.nextJazelle(pc.jazelle()); 61210037SARM gem5 Developers pc.aarch64(!cpsr.width); 61310037SARM gem5 Developers pc.nextAArch64(!cpsr.width); 61412763Sgiacomo.travaglini@arm.com pc.illegalExec(false); 6157720Sgblack@eecs.umich.edu tc->pcState(pc); 6166019Shines@cs.fsu.edu} 6177189Sgblack@eecs.umich.edu 6187400SAli.Saidi@ARM.comvoid 61910417Sandreas.hansson@arm.comArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) 62010037SARM gem5 Developers{ 62110037SARM gem5 Developers // Determine actual misc. register indices for ELR_ELx and SPSR_ELx 62210037SARM gem5 Developers MiscRegIndex elr_idx, spsr_idx; 62310037SARM gem5 Developers switch (toEL) { 62410037SARM gem5 Developers case EL1: 62510037SARM gem5 Developers elr_idx = MISCREG_ELR_EL1; 62610037SARM gem5 Developers spsr_idx = MISCREG_SPSR_EL1; 62710037SARM gem5 Developers break; 62811574SCurtis.Dunham@arm.com case EL2: 62911574SCurtis.Dunham@arm.com assert(ArmSystem::haveVirtualization(tc)); 63011574SCurtis.Dunham@arm.com elr_idx = MISCREG_ELR_EL2; 63111574SCurtis.Dunham@arm.com spsr_idx = MISCREG_SPSR_EL2; 63211574SCurtis.Dunham@arm.com break; 63310037SARM gem5 Developers case EL3: 63410037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 63510037SARM gem5 Developers elr_idx = MISCREG_ELR_EL3; 63610037SARM gem5 Developers spsr_idx = MISCREG_SPSR_EL3; 63710037SARM gem5 Developers break; 63810037SARM gem5 Developers default: 63910037SARM gem5 Developers panic("Invalid target exception level"); 64010037SARM gem5 Developers break; 64110037SARM gem5 Developers } 64210037SARM gem5 Developers 64310037SARM gem5 Developers // Save process state into SPSR_ELx 64410037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 64510037SARM gem5 Developers CPSR spsr = cpsr; 64610338SCurtis.Dunham@arm.com spsr.nz = tc->readCCReg(CCREG_NZ); 64710338SCurtis.Dunham@arm.com spsr.c = tc->readCCReg(CCREG_C); 64810338SCurtis.Dunham@arm.com spsr.v = tc->readCCReg(CCREG_V); 64910037SARM gem5 Developers if (from64) { 65010037SARM gem5 Developers // Force some bitfields to 0 65110037SARM gem5 Developers spsr.q = 0; 65210037SARM gem5 Developers spsr.it1 = 0; 65310037SARM gem5 Developers spsr.j = 0; 65410037SARM gem5 Developers spsr.ge = 0; 65510037SARM gem5 Developers spsr.it2 = 0; 65610037SARM gem5 Developers spsr.t = 0; 65710037SARM gem5 Developers } else { 65810338SCurtis.Dunham@arm.com spsr.ge = tc->readCCReg(CCREG_GE); 65910037SARM gem5 Developers ITSTATE it = tc->pcState().itstate(); 66010037SARM gem5 Developers spsr.it2 = it.top6; 66110037SARM gem5 Developers spsr.it1 = it.bottom2; 66210037SARM gem5 Developers // Force some bitfields to 0 66310037SARM gem5 Developers spsr.ss = 0; 66410037SARM gem5 Developers } 66510037SARM gem5 Developers tc->setMiscReg(spsr_idx, spsr); 66610037SARM gem5 Developers 66710037SARM gem5 Developers // Save preferred return address into ELR_ELx 66810037SARM gem5 Developers Addr curr_pc = tc->pcState().pc(); 66910037SARM gem5 Developers Addr ret_addr = curr_pc; 67010037SARM gem5 Developers if (from64) 67110037SARM gem5 Developers ret_addr += armPcElrOffset(); 67210037SARM gem5 Developers else 67310037SARM gem5 Developers ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset(); 67410037SARM gem5 Developers tc->setMiscReg(elr_idx, ret_addr); 67510037SARM gem5 Developers 67612511Schuan.zhu@arm.com Addr vec_address = getVector64(tc); 67712511Schuan.zhu@arm.com 67810037SARM gem5 Developers // Update process state 67910037SARM gem5 Developers OperatingMode64 mode = 0; 68010037SARM gem5 Developers mode.spX = 1; 68110037SARM gem5 Developers mode.el = toEL; 68210037SARM gem5 Developers mode.width = 0; 68310037SARM gem5 Developers cpsr.mode = mode; 68410037SARM gem5 Developers cpsr.daif = 0xf; 68510037SARM gem5 Developers cpsr.il = 0; 68610037SARM gem5 Developers cpsr.ss = 0; 68714128Sgiacomo.travaglini@arm.com cpsr.pan = span ? 1 : spsr.pan; 68810037SARM gem5 Developers tc->setMiscReg(MISCREG_CPSR, cpsr); 68910037SARM gem5 Developers 69013896Sgiacomo.travaglini@arm.com // If we have a valid instruction then use it to annotate this fault with 69113896Sgiacomo.travaglini@arm.com // extra information. This is used to generate the correct fault syndrome 69213896Sgiacomo.travaglini@arm.com // information 69313896Sgiacomo.travaglini@arm.com ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst); 69413896Sgiacomo.travaglini@arm.com 69510037SARM gem5 Developers // Set PC to start of exception handler 69612511Schuan.zhu@arm.com Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL); 69710037SARM gem5 Developers DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x " 69813896Sgiacomo.travaglini@arm.com "elr:%#x newVec: %#x %s\n", name(), cpsr, curr_pc, ret_addr, 69913896Sgiacomo.travaglini@arm.com new_pc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) : 70013896Sgiacomo.travaglini@arm.com std::string()); 70110037SARM gem5 Developers PCState pc(new_pc); 70210037SARM gem5 Developers pc.aarch64(!cpsr.width); 70310037SARM gem5 Developers pc.nextAArch64(!cpsr.width); 70412763Sgiacomo.travaglini@arm.com pc.illegalExec(false); 70510037SARM gem5 Developers tc->pcState(pc); 70610037SARM gem5 Developers 70710037SARM gem5 Developers // Save exception syndrome 70810037SARM gem5 Developers if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ)) 70910037SARM gem5 Developers setSyndrome(tc, getSyndromeReg64()); 71010037SARM gem5 Developers} 71110037SARM gem5 Developers 71213896Sgiacomo.travaglini@arm.comArmStaticInst * 71313896Sgiacomo.travaglini@arm.comArmFault::instrAnnotate(const StaticInstPtr &inst) 71413896Sgiacomo.travaglini@arm.com{ 71513896Sgiacomo.travaglini@arm.com if (inst) { 71613896Sgiacomo.travaglini@arm.com auto arm_inst = static_cast<ArmStaticInst *>(inst.get()); 71713896Sgiacomo.travaglini@arm.com arm_inst->annotateFault(this); 71813896Sgiacomo.travaglini@arm.com return arm_inst; 71913896Sgiacomo.travaglini@arm.com } else { 72013896Sgiacomo.travaglini@arm.com return nullptr; 72113896Sgiacomo.travaglini@arm.com } 72213896Sgiacomo.travaglini@arm.com} 72313896Sgiacomo.travaglini@arm.com 72413396Sgiacomo.travaglini@arm.comAddr 72513396Sgiacomo.travaglini@arm.comReset::getVector(ThreadContext *tc) 72613396Sgiacomo.travaglini@arm.com{ 72713396Sgiacomo.travaglini@arm.com Addr base; 72813396Sgiacomo.travaglini@arm.com 72913396Sgiacomo.travaglini@arm.com // Check for invalid modes 73013396Sgiacomo.travaglini@arm.com CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 73113396Sgiacomo.travaglini@arm.com assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON); 73213396Sgiacomo.travaglini@arm.com assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); 73313396Sgiacomo.travaglini@arm.com 73413396Sgiacomo.travaglini@arm.com // RVBAR is aliased (implemented as) MVBAR in gem5, since the two 73513396Sgiacomo.travaglini@arm.com // are mutually exclusive; there is no need to check here for 73613396Sgiacomo.travaglini@arm.com // which register to use since they hold the same value 73713396Sgiacomo.travaglini@arm.com base = tc->readMiscReg(MISCREG_MVBAR); 73813396Sgiacomo.travaglini@arm.com 73913396Sgiacomo.travaglini@arm.com return base + offset(tc); 74013396Sgiacomo.travaglini@arm.com} 74113396Sgiacomo.travaglini@arm.com 74210037SARM gem5 Developersvoid 74310417Sandreas.hansson@arm.comReset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7447400SAli.Saidi@ARM.com{ 7458782Sgblack@eecs.umich.edu if (FullSystem) { 74611150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupts(tc->threadId()); 7478782Sgblack@eecs.umich.edu tc->clearArchRegs(); 7488782Sgblack@eecs.umich.edu } 74910037SARM gem5 Developers if (!ArmSystem::highestELIs64(tc)) { 75010037SARM gem5 Developers ArmFault::invoke(tc, inst); 75110037SARM gem5 Developers tc->setMiscReg(MISCREG_VMPIDR, 75210037SARM gem5 Developers getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc)); 75310037SARM gem5 Developers 75410037SARM gem5 Developers // Unless we have SMC code to get us there, boot in HYP! 75510037SARM gem5 Developers if (ArmSystem::haveVirtualization(tc) && 75610037SARM gem5 Developers !ArmSystem::haveSecurity(tc)) { 75710037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 75810037SARM gem5 Developers cpsr.mode = MODE_HYP; 75910037SARM gem5 Developers tc->setMiscReg(MISCREG_CPSR, cpsr); 76010037SARM gem5 Developers } 76110037SARM gem5 Developers } else { 76210037SARM gem5 Developers // Advance the PC to the IMPLEMENTATION DEFINED reset value 76313396Sgiacomo.travaglini@arm.com PCState pc = ArmSystem::resetAddr(tc); 76410037SARM gem5 Developers pc.aarch64(true); 76510037SARM gem5 Developers pc.nextAArch64(true); 76610037SARM gem5 Developers tc->pcState(pc); 76710037SARM gem5 Developers } 7687400SAli.Saidi@ARM.com} 7697400SAli.Saidi@ARM.com 7707189Sgblack@eecs.umich.eduvoid 77110417Sandreas.hansson@arm.comUndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7727189Sgblack@eecs.umich.edu{ 7738782Sgblack@eecs.umich.edu if (FullSystem) { 7748782Sgblack@eecs.umich.edu ArmFault::invoke(tc, inst); 7758806Sgblack@eecs.umich.edu return; 7768806Sgblack@eecs.umich.edu } 7778806Sgblack@eecs.umich.edu 7788806Sgblack@eecs.umich.edu // If the mnemonic isn't defined this has to be an unknown instruction. 7798806Sgblack@eecs.umich.edu assert(unknown || mnemonic != NULL); 78013895Sgiacomo.travaglini@arm.com auto arm_inst = static_cast<ArmStaticInst *>(inst.get()); 7818806Sgblack@eecs.umich.edu if (disabled) { 7828806Sgblack@eecs.umich.edu panic("Attempted to execute disabled instruction " 78313895Sgiacomo.travaglini@arm.com "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding()); 7848806Sgblack@eecs.umich.edu } else if (unknown) { 7858806Sgblack@eecs.umich.edu panic("Attempted to execute unknown instruction (inst 0x%08x)", 78613895Sgiacomo.travaglini@arm.com arm_inst->encoding()); 7877189Sgblack@eecs.umich.edu } else { 7888806Sgblack@eecs.umich.edu panic("Attempted to execute unimplemented instruction " 78913895Sgiacomo.travaglini@arm.com "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding()); 7907189Sgblack@eecs.umich.edu } 7917189Sgblack@eecs.umich.edu} 7927189Sgblack@eecs.umich.edu 79310037SARM gem5 Developersbool 79410037SARM gem5 DevelopersUndefinedInstruction::routeToHyp(ThreadContext *tc) const 79510037SARM gem5 Developers{ 79610037SARM gem5 Developers bool toHyp; 79710037SARM gem5 Developers 79810037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 79910037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 80010037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 80110037SARM gem5 Developers 80210037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 80310037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 80410037SARM gem5 Developers // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 80510037SARM gem5 Developers toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 80610037SARM gem5 Developers return toHyp; 80710037SARM gem5 Developers} 80810037SARM gem5 Developers 80910037SARM gem5 Developersuint32_t 81010037SARM gem5 DevelopersUndefinedInstruction::iss() const 81110037SARM gem5 Developers{ 81212402Sgiacomo.travaglini@arm.com 81312402Sgiacomo.travaglini@arm.com // If UndefinedInstruction is routed to hypervisor, iss field is 0. 81412402Sgiacomo.travaglini@arm.com if (hypRouted) { 81512402Sgiacomo.travaglini@arm.com return 0; 81612402Sgiacomo.travaglini@arm.com } 81712402Sgiacomo.travaglini@arm.com 81810037SARM gem5 Developers if (overrideEc == EC_INVALID) 81910037SARM gem5 Developers return issRaw; 82010037SARM gem5 Developers 82110037SARM gem5 Developers uint32_t new_iss = 0; 82210037SARM gem5 Developers uint32_t op0, op1, op2, CRn, CRm, Rt, dir; 82310037SARM gem5 Developers 82410037SARM gem5 Developers dir = bits(machInst, 21, 21); 82510037SARM gem5 Developers op0 = bits(machInst, 20, 19); 82610037SARM gem5 Developers op1 = bits(machInst, 18, 16); 82710037SARM gem5 Developers CRn = bits(machInst, 15, 12); 82810037SARM gem5 Developers CRm = bits(machInst, 11, 8); 82910037SARM gem5 Developers op2 = bits(machInst, 7, 5); 83010037SARM gem5 Developers Rt = bits(machInst, 4, 0); 83110037SARM gem5 Developers 83210037SARM gem5 Developers new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 | 83310037SARM gem5 Developers Rt << 5 | CRm << 1 | dir; 83410037SARM gem5 Developers 83510037SARM gem5 Developers return new_iss; 83610037SARM gem5 Developers} 83710037SARM gem5 Developers 8387197Sgblack@eecs.umich.eduvoid 83910417Sandreas.hansson@arm.comSupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 8407197Sgblack@eecs.umich.edu{ 8418782Sgblack@eecs.umich.edu if (FullSystem) { 8428782Sgblack@eecs.umich.edu ArmFault::invoke(tc, inst); 8438806Sgblack@eecs.umich.edu return; 8448806Sgblack@eecs.umich.edu } 8457197Sgblack@eecs.umich.edu 8468806Sgblack@eecs.umich.edu // As of now, there isn't a 32 bit thumb version of this instruction. 8478806Sgblack@eecs.umich.edu assert(!machInst.bigThumb); 8488806Sgblack@eecs.umich.edu uint32_t callNum; 84910037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 85010037SARM gem5 Developers OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode; 85110037SARM gem5 Developers if (opModeIs64(mode)) 85210037SARM gem5 Developers callNum = tc->readIntReg(INTREG_X8); 85310037SARM gem5 Developers else 85410037SARM gem5 Developers callNum = tc->readIntReg(INTREG_R7); 85511877Sbrandon.potter@amd.com Fault fault; 85611877Sbrandon.potter@amd.com tc->syscall(callNum, &fault); 8578806Sgblack@eecs.umich.edu 8588806Sgblack@eecs.umich.edu // Advance the PC since that won't happen automatically. 8598806Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 8608806Sgblack@eecs.umich.edu assert(inst); 8618806Sgblack@eecs.umich.edu inst->advancePC(pc); 8628806Sgblack@eecs.umich.edu tc->pcState(pc); 8637197Sgblack@eecs.umich.edu} 8647197Sgblack@eecs.umich.edu 86510037SARM gem5 Developersbool 86610037SARM gem5 DevelopersSupervisorCall::routeToHyp(ThreadContext *tc) const 86710037SARM gem5 Developers{ 86810037SARM gem5 Developers bool toHyp; 86910037SARM gem5 Developers 87010037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 87110037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 87210037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 87310037SARM gem5 Developers 87410037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 87510037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 87610037SARM gem5 Developers // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 87710037SARM gem5 Developers toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 87810037SARM gem5 Developers return toHyp; 87910037SARM gem5 Developers} 88010037SARM gem5 Developers 88110037SARM gem5 DevelopersExceptionClass 88210037SARM gem5 DevelopersSupervisorCall::ec(ThreadContext *tc) const 88310037SARM gem5 Developers{ 88410037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : 88510037SARM gem5 Developers (from64 ? EC_SVC_64 : vals.ec); 88610037SARM gem5 Developers} 88710037SARM gem5 Developers 88810037SARM gem5 Developersuint32_t 88910037SARM gem5 DevelopersSupervisorCall::iss() const 89010037SARM gem5 Developers{ 89110037SARM gem5 Developers // Even if we have a 24 bit imm from an arm32 instruction then we only use 89210037SARM gem5 Developers // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC). 89310037SARM gem5 Developers return issRaw & 0xFFFF; 89410037SARM gem5 Developers} 89510037SARM gem5 Developers 89610037SARM gem5 Developersuint32_t 89710037SARM gem5 DevelopersSecureMonitorCall::iss() const 89810037SARM gem5 Developers{ 89910037SARM gem5 Developers if (from64) 90010037SARM gem5 Developers return bits(machInst, 20, 5); 90110037SARM gem5 Developers return 0; 90210037SARM gem5 Developers} 90310037SARM gem5 Developers 90410037SARM gem5 DevelopersExceptionClass 90510037SARM gem5 DevelopersUndefinedInstruction::ec(ThreadContext *tc) const 90610037SARM gem5 Developers{ 90712402Sgiacomo.travaglini@arm.com // If UndefinedInstruction is routed to hypervisor, 90812402Sgiacomo.travaglini@arm.com // HSR.EC field is 0. 90912402Sgiacomo.travaglini@arm.com if (hypRouted) 91012402Sgiacomo.travaglini@arm.com return EC_UNKNOWN; 91112402Sgiacomo.travaglini@arm.com else 91212402Sgiacomo.travaglini@arm.com return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 91310037SARM gem5 Developers} 91410037SARM gem5 Developers 91510037SARM gem5 Developers 91610037SARM gem5 DevelopersHypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) : 91710037SARM gem5 Developers ArmFaultVals<HypervisorCall>(_machInst, _imm) 91810037SARM gem5 Developers{} 91910037SARM gem5 Developers 92010037SARM gem5 DevelopersExceptionClass 92111576SDylan.Johnson@ARM.comHypervisorCall::ec(ThreadContext *tc) const 92211576SDylan.Johnson@ARM.com{ 92311576SDylan.Johnson@ARM.com return from64 ? EC_HVC_64 : vals.ec; 92411576SDylan.Johnson@ARM.com} 92511576SDylan.Johnson@ARM.com 92611576SDylan.Johnson@ARM.comExceptionClass 92710037SARM gem5 DevelopersHypervisorTrap::ec(ThreadContext *tc) const 92810037SARM gem5 Developers{ 92910037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 93010037SARM gem5 Developers} 93110037SARM gem5 Developers 93210037SARM gem5 Developerstemplate<class T> 93310037SARM gem5 DevelopersFaultOffset 93410037SARM gem5 DevelopersArmFaultVals<T>::offset(ThreadContext *tc) 93510037SARM gem5 Developers{ 93610037SARM gem5 Developers bool isHypTrap = false; 93710037SARM gem5 Developers 93810037SARM gem5 Developers // Normally we just use the exception vector from the table at the top if 93910037SARM gem5 Developers // this file, however if this exception has caused a transition to hype 94010037SARM gem5 Developers // mode, and its an exception type that would only do this if it has been 94110037SARM gem5 Developers // trapped then we use the hyp trap vector instead of the normal vector 94210037SARM gem5 Developers if (vals.hypTrappable) { 94310037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 94410037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 94510037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 94610037SARM gem5 Developers isHypTrap = spsr.mode != MODE_HYP; 94710037SARM gem5 Developers } 94810037SARM gem5 Developers } 94910037SARM gem5 Developers return isHypTrap ? 0x14 : vals.offset; 95010037SARM gem5 Developers} 95110037SARM gem5 Developers 95212511Schuan.zhu@arm.comtemplate<class T> 95312511Schuan.zhu@arm.comFaultOffset 95412511Schuan.zhu@arm.comArmFaultVals<T>::offset64(ThreadContext *tc) 95512511Schuan.zhu@arm.com{ 95612511Schuan.zhu@arm.com if (toEL == fromEL) { 95712511Schuan.zhu@arm.com if (opModeIsT(fromMode)) 95812511Schuan.zhu@arm.com return vals.currELTOffset; 95912511Schuan.zhu@arm.com return vals.currELHOffset; 96012511Schuan.zhu@arm.com } else { 96112511Schuan.zhu@arm.com bool lower_32 = false; 96212511Schuan.zhu@arm.com if (toEL == EL3) { 96312511Schuan.zhu@arm.com if (!inSecureState(tc) && ArmSystem::haveEL(tc, EL2)) 96412511Schuan.zhu@arm.com lower_32 = ELIs32(tc, EL2); 96512511Schuan.zhu@arm.com else 96612511Schuan.zhu@arm.com lower_32 = ELIs32(tc, EL1); 96712511Schuan.zhu@arm.com } else { 96812511Schuan.zhu@arm.com lower_32 = ELIs32(tc, static_cast<ExceptionLevel>(toEL - 1)); 96912511Schuan.zhu@arm.com } 97012511Schuan.zhu@arm.com 97112511Schuan.zhu@arm.com if (lower_32) 97212511Schuan.zhu@arm.com return vals.lowerEL32Offset; 97312511Schuan.zhu@arm.com return vals.lowerEL64Offset; 97412511Schuan.zhu@arm.com } 97512511Schuan.zhu@arm.com} 97612511Schuan.zhu@arm.com 97710037SARM gem5 Developers// void 97810037SARM gem5 Developers// SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx) 97910037SARM gem5 Developers// { 98010037SARM gem5 Developers// ESR esr = 0; 98110037SARM gem5 Developers// esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32; 98210037SARM gem5 Developers// esr.il = !machInst.thumb; 98310037SARM gem5 Developers// if (machInst.aarch64) 98410037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 20, 5); 98510037SARM gem5 Developers// else if (machInst.thumb) 98610037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 7, 0); 98710037SARM gem5 Developers// else 98810037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 15, 0); 98910037SARM gem5 Developers// tc->setMiscReg(esr_idx, esr); 99010037SARM gem5 Developers// } 99110037SARM gem5 Developers 99210037SARM gem5 Developersvoid 99310417Sandreas.hansson@arm.comSecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 99410037SARM gem5 Developers{ 99510037SARM gem5 Developers if (FullSystem) { 99610037SARM gem5 Developers ArmFault::invoke(tc, inst); 99710037SARM gem5 Developers return; 99810037SARM gem5 Developers } 99910037SARM gem5 Developers} 100010037SARM gem5 Developers 100110037SARM gem5 DevelopersExceptionClass 100210037SARM gem5 DevelopersSecureMonitorCall::ec(ThreadContext *tc) const 100310037SARM gem5 Developers{ 100410037SARM gem5 Developers return (from64 ? EC_SMC_64 : vals.ec); 100510037SARM gem5 Developers} 100610037SARM gem5 Developers 100712509Schuan.zhu@arm.combool 100812509Schuan.zhu@arm.comSupervisorTrap::routeToHyp(ThreadContext *tc) const 100912509Schuan.zhu@arm.com{ 101012509Schuan.zhu@arm.com bool toHyp = false; 101112509Schuan.zhu@arm.com 101212509Schuan.zhu@arm.com SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 101312509Schuan.zhu@arm.com HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 101412509Schuan.zhu@arm.com CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 101512509Schuan.zhu@arm.com 101612509Schuan.zhu@arm.com // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 101712509Schuan.zhu@arm.com toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); 101812509Schuan.zhu@arm.com return toHyp; 101912509Schuan.zhu@arm.com} 102012509Schuan.zhu@arm.com 102112509Schuan.zhu@arm.comuint32_t 102212509Schuan.zhu@arm.comSupervisorTrap::iss() const 102312509Schuan.zhu@arm.com{ 102412509Schuan.zhu@arm.com // If SupervisorTrap is routed to hypervisor, iss field is 0. 102512509Schuan.zhu@arm.com if (hypRouted) { 102612509Schuan.zhu@arm.com return 0; 102712509Schuan.zhu@arm.com } 102812509Schuan.zhu@arm.com return issRaw; 102912509Schuan.zhu@arm.com} 103012509Schuan.zhu@arm.com 103110037SARM gem5 DevelopersExceptionClass 103210037SARM gem5 DevelopersSupervisorTrap::ec(ThreadContext *tc) const 103310037SARM gem5 Developers{ 103412509Schuan.zhu@arm.com if (hypRouted) 103512509Schuan.zhu@arm.com return EC_UNKNOWN; 103612509Schuan.zhu@arm.com else 103712509Schuan.zhu@arm.com return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 103810037SARM gem5 Developers} 103910037SARM gem5 Developers 104010037SARM gem5 DevelopersExceptionClass 104110037SARM gem5 DevelopersSecureMonitorTrap::ec(ThreadContext *tc) const 104210037SARM gem5 Developers{ 104310037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : 104410037SARM gem5 Developers (from64 ? EC_SMC_64 : vals.ec); 104510037SARM gem5 Developers} 104610037SARM gem5 Developers 10477362Sgblack@eecs.umich.edutemplate<class T> 10487362Sgblack@eecs.umich.eduvoid 104910417Sandreas.hansson@arm.comAbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst) 10507362Sgblack@eecs.umich.edu{ 105110037SARM gem5 Developers if (tranMethod == ArmFault::UnknownTran) { 105210037SARM gem5 Developers tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran 105310037SARM gem5 Developers : ArmFault::VmsaTran; 105410037SARM gem5 Developers 105510037SARM gem5 Developers if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) { 105610037SARM gem5 Developers // See ARM ARM B3-1416 105710037SARM gem5 Developers bool override_LPAE = false; 105810037SARM gem5 Developers TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S); 105910037SARM gem5 Developers TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS); 106010037SARM gem5 Developers if (ttbcr_s.eae) { 106110037SARM gem5 Developers override_LPAE = true; 106210037SARM gem5 Developers } else { 106310037SARM gem5 Developers // Unimplemented code option, not seen in testing. May need 106410037SARM gem5 Developers // extension according to the manual exceprt above. 106510037SARM gem5 Developers DPRINTF(Faults, "Warning: Incomplete translation method " 106610037SARM gem5 Developers "override detected.\n"); 106710037SARM gem5 Developers } 106810037SARM gem5 Developers if (override_LPAE) 106910037SARM gem5 Developers tranMethod = ArmFault::LpaeTran; 107010037SARM gem5 Developers } 107110037SARM gem5 Developers } 107210037SARM gem5 Developers 107310037SARM gem5 Developers if (source == ArmFault::AsynchronousExternalAbort) { 107411150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 107510037SARM gem5 Developers } 107610037SARM gem5 Developers // Get effective fault source encoding 107710037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 107810037SARM gem5 Developers 107910037SARM gem5 Developers // source must be determined BEFORE invoking generic routines which will 108010037SARM gem5 Developers // try to set hsr etc. and are based upon source! 10818205SAli.Saidi@ARM.com ArmFaultVals<T>::invoke(tc, inst); 108210037SARM gem5 Developers 108311496Sandreas.sandberg@arm.com if (!this->to64) { // AArch32 108412570Sgiacomo.travaglini@arm.com FSR fsr = getFsr(tc); 108510037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 108610037SARM gem5 Developers tc->setMiscReg(T::HFarIndex, faultAddr); 108710037SARM gem5 Developers } else if (stage2) { 108810037SARM gem5 Developers tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf); 108910037SARM gem5 Developers tc->setMiscReg(T::HFarIndex, OVAddr); 109010037SARM gem5 Developers } else { 109110037SARM gem5 Developers tc->setMiscReg(T::FsrIndex, fsr); 109210037SARM gem5 Developers tc->setMiscReg(T::FarIndex, faultAddr); 109310037SARM gem5 Developers } 109410037SARM gem5 Developers DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\ 109510037SARM gem5 Developers "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod); 109610037SARM gem5 Developers } else { // AArch64 109710037SARM gem5 Developers // Set the FAR register. Nothing else to do if we are in AArch64 state 109810037SARM gem5 Developers // because the syndrome register has already been set inside invoke64() 109911585SDylan.Johnson@ARM.com if (stage2) { 110011585SDylan.Johnson@ARM.com // stage 2 fault, set HPFAR_EL2 to the faulting IPA 110111585SDylan.Johnson@ARM.com // and FAR_EL2 to the Original VA 110211585SDylan.Johnson@ARM.com tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr); 110311585SDylan.Johnson@ARM.com tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4); 110411585SDylan.Johnson@ARM.com 110511585SDylan.Johnson@ARM.com DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n", 110611585SDylan.Johnson@ARM.com OVAddr, faultAddr); 110711585SDylan.Johnson@ARM.com } else { 110811585SDylan.Johnson@ARM.com tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr); 110911585SDylan.Johnson@ARM.com } 111010037SARM gem5 Developers } 111110037SARM gem5 Developers} 111210037SARM gem5 Developers 111310037SARM gem5 Developerstemplate<class T> 111412570Sgiacomo.travaglini@arm.comvoid 111512570Sgiacomo.travaglini@arm.comAbortFault<T>::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 111612570Sgiacomo.travaglini@arm.com{ 111712570Sgiacomo.travaglini@arm.com srcEncoded = getFaultStatusCode(tc); 111812570Sgiacomo.travaglini@arm.com if (srcEncoded == ArmFault::FaultSourceInvalid) { 111912570Sgiacomo.travaglini@arm.com panic("Invalid fault source\n"); 112012570Sgiacomo.travaglini@arm.com } 112112570Sgiacomo.travaglini@arm.com ArmFault::setSyndrome(tc, syndrome_reg); 112212570Sgiacomo.travaglini@arm.com} 112312570Sgiacomo.travaglini@arm.com 112412570Sgiacomo.travaglini@arm.comtemplate<class T> 112512570Sgiacomo.travaglini@arm.comuint8_t 112612570Sgiacomo.travaglini@arm.comAbortFault<T>::getFaultStatusCode(ThreadContext *tc) const 112712570Sgiacomo.travaglini@arm.com{ 112812570Sgiacomo.travaglini@arm.com 112912570Sgiacomo.travaglini@arm.com panic_if(!this->faultUpdated, 113012570Sgiacomo.travaglini@arm.com "Trying to use un-updated ArmFault internal variables\n"); 113112570Sgiacomo.travaglini@arm.com 113212570Sgiacomo.travaglini@arm.com uint8_t fsc = 0; 113312570Sgiacomo.travaglini@arm.com 113412570Sgiacomo.travaglini@arm.com if (!this->to64) { 113512570Sgiacomo.travaglini@arm.com // AArch32 113612570Sgiacomo.travaglini@arm.com assert(tranMethod != ArmFault::UnknownTran); 113712570Sgiacomo.travaglini@arm.com if (tranMethod == ArmFault::LpaeTran) { 113812570Sgiacomo.travaglini@arm.com fsc = ArmFault::longDescFaultSources[source]; 113912570Sgiacomo.travaglini@arm.com } else { 114012570Sgiacomo.travaglini@arm.com fsc = ArmFault::shortDescFaultSources[source]; 114112570Sgiacomo.travaglini@arm.com } 114212570Sgiacomo.travaglini@arm.com } else { 114312570Sgiacomo.travaglini@arm.com // AArch64 114412570Sgiacomo.travaglini@arm.com fsc = ArmFault::aarch64FaultSources[source]; 114512570Sgiacomo.travaglini@arm.com } 114612570Sgiacomo.travaglini@arm.com 114712570Sgiacomo.travaglini@arm.com return fsc; 114812570Sgiacomo.travaglini@arm.com} 114912570Sgiacomo.travaglini@arm.com 115012570Sgiacomo.travaglini@arm.comtemplate<class T> 115110037SARM gem5 DevelopersFSR 115212570Sgiacomo.travaglini@arm.comAbortFault<T>::getFsr(ThreadContext *tc) const 115310037SARM gem5 Developers{ 11547362Sgblack@eecs.umich.edu FSR fsr = 0; 11558314Sgeoffrey.blake@arm.com 115612570Sgiacomo.travaglini@arm.com auto fsc = getFaultStatusCode(tc); 115712570Sgiacomo.travaglini@arm.com 115812570Sgiacomo.travaglini@arm.com // AArch32 115912570Sgiacomo.travaglini@arm.com assert(tranMethod != ArmFault::UnknownTran); 116012570Sgiacomo.travaglini@arm.com if (tranMethod == ArmFault::LpaeTran) { 116112570Sgiacomo.travaglini@arm.com fsr.status = fsc; 116212570Sgiacomo.travaglini@arm.com fsr.lpae = 1; 116310037SARM gem5 Developers } else { 116412570Sgiacomo.travaglini@arm.com fsr.fsLow = bits(fsc, 3, 0); 116512570Sgiacomo.travaglini@arm.com fsr.fsHigh = bits(fsc, 4); 116612570Sgiacomo.travaglini@arm.com fsr.domain = static_cast<uint8_t>(domain); 116710037SARM gem5 Developers } 116812570Sgiacomo.travaglini@arm.com 116912570Sgiacomo.travaglini@arm.com fsr.wnr = (write ? 1 : 0); 117012570Sgiacomo.travaglini@arm.com fsr.ext = 0; 117112570Sgiacomo.travaglini@arm.com 117210037SARM gem5 Developers return fsr; 117310037SARM gem5 Developers} 117410037SARM gem5 Developers 117510037SARM gem5 Developerstemplate<class T> 117610037SARM gem5 Developersbool 117710037SARM gem5 DevelopersAbortFault<T>::abortDisable(ThreadContext *tc) 117810037SARM gem5 Developers{ 117910037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 118010037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 118110037SARM gem5 Developers return (!scr.ns || scr.aw); 118210037SARM gem5 Developers } 118310037SARM gem5 Developers return true; 118410037SARM gem5 Developers} 118510037SARM gem5 Developers 118610037SARM gem5 Developerstemplate<class T> 118710037SARM gem5 Developersvoid 118810037SARM gem5 DevelopersAbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val) 118910037SARM gem5 Developers{ 119010037SARM gem5 Developers switch (id) 119110037SARM gem5 Developers { 119210037SARM gem5 Developers case ArmFault::S1PTW: 119310037SARM gem5 Developers s1ptw = val; 119410037SARM gem5 Developers break; 119510037SARM gem5 Developers case ArmFault::OVA: 119610037SARM gem5 Developers OVAddr = val; 119710037SARM gem5 Developers break; 119810037SARM gem5 Developers 119910037SARM gem5 Developers // Just ignore unknown ID's 120010037SARM gem5 Developers default: 120110037SARM gem5 Developers break; 120210037SARM gem5 Developers } 120310037SARM gem5 Developers} 120410037SARM gem5 Developers 120510037SARM gem5 Developerstemplate<class T> 120610037SARM gem5 Developersuint32_t 120710037SARM gem5 DevelopersAbortFault<T>::iss() const 120810037SARM gem5 Developers{ 120910037SARM gem5 Developers uint32_t val; 121010037SARM gem5 Developers 121110037SARM gem5 Developers val = srcEncoded & 0x3F; 121210037SARM gem5 Developers val |= write << 6; 121310037SARM gem5 Developers val |= s1ptw << 7; 121410037SARM gem5 Developers return (val); 121510037SARM gem5 Developers} 121610037SARM gem5 Developers 121710037SARM gem5 Developerstemplate<class T> 121810037SARM gem5 Developersbool 121910037SARM gem5 DevelopersAbortFault<T>::isMMUFault() const 122010037SARM gem5 Developers{ 122110037SARM gem5 Developers // NOTE: Not relying on LL information being aligned to lowest bits here 122210037SARM gem5 Developers return 122310037SARM gem5 Developers (source == ArmFault::AlignmentFault) || 122410037SARM gem5 Developers ((source >= ArmFault::TranslationLL) && 122510037SARM gem5 Developers (source < ArmFault::TranslationLL + 4)) || 122610037SARM gem5 Developers ((source >= ArmFault::AccessFlagLL) && 122710037SARM gem5 Developers (source < ArmFault::AccessFlagLL + 4)) || 122810037SARM gem5 Developers ((source >= ArmFault::DomainLL) && 122910037SARM gem5 Developers (source < ArmFault::DomainLL + 4)) || 123010037SARM gem5 Developers ((source >= ArmFault::PermissionLL) && 123110037SARM gem5 Developers (source < ArmFault::PermissionLL + 4)); 123210037SARM gem5 Developers} 123310037SARM gem5 Developers 123414091Sgabor.dozsa@arm.comtemplate<class T> 123514091Sgabor.dozsa@arm.combool 123614091Sgabor.dozsa@arm.comAbortFault<T>::getFaultVAddr(Addr &va) const 123714091Sgabor.dozsa@arm.com{ 123814091Sgabor.dozsa@arm.com va = (stage2 ? OVAddr : faultAddr); 123914091Sgabor.dozsa@arm.com return true; 124014091Sgabor.dozsa@arm.com} 124114091Sgabor.dozsa@arm.com 124210037SARM gem5 DevelopersExceptionClass 124310037SARM gem5 DevelopersPrefetchAbort::ec(ThreadContext *tc) const 124410037SARM gem5 Developers{ 124510037SARM gem5 Developers if (to64) { 124610037SARM gem5 Developers // AArch64 124710037SARM gem5 Developers if (toEL == fromEL) 124810037SARM gem5 Developers return EC_PREFETCH_ABORT_CURR_EL; 124910037SARM gem5 Developers else 125010037SARM gem5 Developers return EC_PREFETCH_ABORT_LOWER_EL; 125110037SARM gem5 Developers } else { 125210037SARM gem5 Developers // AArch32 125310037SARM gem5 Developers // Abort faults have different EC codes depending on whether 125410037SARM gem5 Developers // the fault originated within HYP mode, or not. So override 125510037SARM gem5 Developers // the method and add the extra adjustment of the EC value. 125610037SARM gem5 Developers 125710037SARM gem5 Developers ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec; 125810037SARM gem5 Developers 125910037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 126010037SARM gem5 Developers if (spsr.mode == MODE_HYP) { 126110037SARM gem5 Developers ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 126210037SARM gem5 Developers } 126310037SARM gem5 Developers return ec; 126410037SARM gem5 Developers } 126510037SARM gem5 Developers} 126610037SARM gem5 Developers 126710037SARM gem5 Developersbool 126810037SARM gem5 DevelopersPrefetchAbort::routeToMonitor(ThreadContext *tc) const 126910037SARM gem5 Developers{ 127010037SARM gem5 Developers SCR scr = 0; 127110037SARM gem5 Developers if (from64) 127210037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 127310037SARM gem5 Developers else 127410037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 127510037SARM gem5 Developers 127610037SARM gem5 Developers return scr.ea && !isMMUFault(); 127710037SARM gem5 Developers} 127810037SARM gem5 Developers 127910037SARM gem5 Developersbool 128010037SARM gem5 DevelopersPrefetchAbort::routeToHyp(ThreadContext *tc) const 128110037SARM gem5 Developers{ 128210037SARM gem5 Developers bool toHyp; 128310037SARM gem5 Developers 128410037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 128510037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 128610037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 128710037SARM gem5 Developers HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 128810037SARM gem5 Developers 128910037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 129010037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 129110037SARM gem5 Developers // otherwise, check whether to take to Hyp mode through Hyp Trap vector 129210037SARM gem5 Developers toHyp |= (stage2 || 129310037SARM gem5 Developers ( (source == DebugEvent) && hdcr.tde && (cpsr.mode != MODE_HYP)) || 129410037SARM gem5 Developers ( (source == SynchronousExternalAbort) && hcr.tge && (cpsr.mode == MODE_USER)) 129511581SDylan.Johnson@ARM.com ) && !inSecureState(tc); 129610037SARM gem5 Developers return toHyp; 129710037SARM gem5 Developers} 129810037SARM gem5 Developers 129910037SARM gem5 DevelopersExceptionClass 130010037SARM gem5 DevelopersDataAbort::ec(ThreadContext *tc) const 130110037SARM gem5 Developers{ 130210037SARM gem5 Developers if (to64) { 130310037SARM gem5 Developers // AArch64 130410037SARM gem5 Developers if (source == ArmFault::AsynchronousExternalAbort) { 130510367SAndrew.Bardsley@arm.com panic("Asynchronous External Abort should be handled with " 130610367SAndrew.Bardsley@arm.com "SystemErrors (SErrors)!"); 130710037SARM gem5 Developers } 130810037SARM gem5 Developers if (toEL == fromEL) 130910037SARM gem5 Developers return EC_DATA_ABORT_CURR_EL; 131010037SARM gem5 Developers else 131110037SARM gem5 Developers return EC_DATA_ABORT_LOWER_EL; 131210037SARM gem5 Developers } else { 131310037SARM gem5 Developers // AArch32 131410037SARM gem5 Developers // Abort faults have different EC codes depending on whether 131510037SARM gem5 Developers // the fault originated within HYP mode, or not. So override 131610037SARM gem5 Developers // the method and add the extra adjustment of the EC value. 131710037SARM gem5 Developers 131810037SARM gem5 Developers ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec; 131910037SARM gem5 Developers 132010037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 132110037SARM gem5 Developers if (spsr.mode == MODE_HYP) { 132210037SARM gem5 Developers ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 132310037SARM gem5 Developers } 132410037SARM gem5 Developers return ec; 132510037SARM gem5 Developers } 132610037SARM gem5 Developers} 132710037SARM gem5 Developers 132810037SARM gem5 Developersbool 132910037SARM gem5 DevelopersDataAbort::routeToMonitor(ThreadContext *tc) const 133010037SARM gem5 Developers{ 133110037SARM gem5 Developers SCR scr = 0; 133210037SARM gem5 Developers if (from64) 133310037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 133410037SARM gem5 Developers else 133510037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 133610037SARM gem5 Developers 133710037SARM gem5 Developers return scr.ea && !isMMUFault(); 133810037SARM gem5 Developers} 133910037SARM gem5 Developers 134010037SARM gem5 Developersbool 134110037SARM gem5 DevelopersDataAbort::routeToHyp(ThreadContext *tc) const 134210037SARM gem5 Developers{ 134310037SARM gem5 Developers bool toHyp; 134410037SARM gem5 Developers 134510037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 134610037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 134710037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 134810037SARM gem5 Developers HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 134910037SARM gem5 Developers 135010037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 135110037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 135210037SARM gem5 Developers // otherwise, check whether to take to Hyp mode through Hyp Trap vector 135310037SARM gem5 Developers toHyp |= (stage2 || 135410037SARM gem5 Developers ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) || 135510037SARM gem5 Developers ((source == DebugEvent) && hdcr.tde) ) 135610037SARM gem5 Developers ) || 135710037SARM gem5 Developers ( (cpsr.mode == MODE_USER) && hcr.tge && 135810037SARM gem5 Developers ((source == AlignmentFault) || 135910037SARM gem5 Developers (source == SynchronousExternalAbort)) 136010037SARM gem5 Developers ) 136111581SDylan.Johnson@ARM.com ) && !inSecureState(tc); 136210037SARM gem5 Developers return toHyp; 136310037SARM gem5 Developers} 136410037SARM gem5 Developers 136510037SARM gem5 Developersuint32_t 136610037SARM gem5 DevelopersDataAbort::iss() const 136710037SARM gem5 Developers{ 136810037SARM gem5 Developers uint32_t val; 136910037SARM gem5 Developers 137010037SARM gem5 Developers // Add on the data abort specific fields to the generic abort ISS value 137110037SARM gem5 Developers val = AbortFault<DataAbort>::iss(); 137210037SARM gem5 Developers // ISS is valid if not caused by a stage 1 page table walk, and when taken 137310037SARM gem5 Developers // to AArch64 only when directed to EL2 137410037SARM gem5 Developers if (!s1ptw && (!to64 || toEL == EL2)) { 137510037SARM gem5 Developers val |= isv << 24; 137610037SARM gem5 Developers if (isv) { 137710037SARM gem5 Developers val |= sas << 22; 137810037SARM gem5 Developers val |= sse << 21; 137910037SARM gem5 Developers val |= srt << 16; 138010037SARM gem5 Developers // AArch64 only. These assignments are safe on AArch32 as well 138110037SARM gem5 Developers // because these vars are initialized to false 138210037SARM gem5 Developers val |= sf << 15; 138310037SARM gem5 Developers val |= ar << 14; 138410037SARM gem5 Developers } 138510037SARM gem5 Developers } 138610037SARM gem5 Developers return (val); 138710037SARM gem5 Developers} 138810037SARM gem5 Developers 138910037SARM gem5 Developersvoid 139010037SARM gem5 DevelopersDataAbort::annotate(AnnotationIDs id, uint64_t val) 139110037SARM gem5 Developers{ 139210037SARM gem5 Developers AbortFault<DataAbort>::annotate(id, val); 139310037SARM gem5 Developers switch (id) 139410037SARM gem5 Developers { 139510037SARM gem5 Developers case SAS: 139610037SARM gem5 Developers isv = true; 139710037SARM gem5 Developers sas = val; 139810037SARM gem5 Developers break; 139910037SARM gem5 Developers case SSE: 140010037SARM gem5 Developers isv = true; 140110037SARM gem5 Developers sse = val; 140210037SARM gem5 Developers break; 140310037SARM gem5 Developers case SRT: 140410037SARM gem5 Developers isv = true; 140510037SARM gem5 Developers srt = val; 140610037SARM gem5 Developers break; 140710037SARM gem5 Developers case SF: 140810037SARM gem5 Developers isv = true; 140910037SARM gem5 Developers sf = val; 141010037SARM gem5 Developers break; 141110037SARM gem5 Developers case AR: 141210037SARM gem5 Developers isv = true; 141310037SARM gem5 Developers ar = val; 141410037SARM gem5 Developers break; 141510037SARM gem5 Developers // Just ignore unknown ID's 141610037SARM gem5 Developers default: 141710037SARM gem5 Developers break; 141810037SARM gem5 Developers } 141910037SARM gem5 Developers} 142010037SARM gem5 Developers 142110037SARM gem5 Developersvoid 142210417Sandreas.hansson@arm.comVirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst) 142310037SARM gem5 Developers{ 142410037SARM gem5 Developers AbortFault<VirtualDataAbort>::invoke(tc, inst); 142510037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 142610037SARM gem5 Developers hcr.va = 0; 142710037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_HCR, hcr); 142810037SARM gem5 Developers} 142910037SARM gem5 Developers 143010037SARM gem5 Developersbool 143110037SARM gem5 DevelopersInterrupt::routeToMonitor(ThreadContext *tc) const 143210037SARM gem5 Developers{ 143310037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 143410037SARM gem5 Developers SCR scr = 0; 143510037SARM gem5 Developers if (from64) 143610037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 143710037SARM gem5 Developers else 143810037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 143910037SARM gem5 Developers return scr.irq; 144010037SARM gem5 Developers} 144110037SARM gem5 Developers 144210037SARM gem5 Developersbool 144310037SARM gem5 DevelopersInterrupt::routeToHyp(ThreadContext *tc) const 144410037SARM gem5 Developers{ 144510037SARM gem5 Developers bool toHyp; 144610037SARM gem5 Developers 144710037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 144810037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 144910037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 145010037SARM gem5 Developers // Determine whether IRQs are routed to Hyp mode. 145111581SDylan.Johnson@ARM.com toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) || 145210037SARM gem5 Developers (cpsr.mode == MODE_HYP); 145310037SARM gem5 Developers return toHyp; 145410037SARM gem5 Developers} 145510037SARM gem5 Developers 145610037SARM gem5 Developersbool 145710037SARM gem5 DevelopersInterrupt::abortDisable(ThreadContext *tc) 145810037SARM gem5 Developers{ 145910037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 146010037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 146110037SARM gem5 Developers return (!scr.ns || scr.aw); 146210037SARM gem5 Developers } 146310037SARM gem5 Developers return true; 146410037SARM gem5 Developers} 146510037SARM gem5 Developers 146610037SARM gem5 DevelopersVirtualInterrupt::VirtualInterrupt() 146710037SARM gem5 Developers{} 146810037SARM gem5 Developers 146910037SARM gem5 Developersbool 147010037SARM gem5 DevelopersFastInterrupt::routeToMonitor(ThreadContext *tc) const 147110037SARM gem5 Developers{ 147210037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 147310037SARM gem5 Developers SCR scr = 0; 147410037SARM gem5 Developers if (from64) 147510037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 147610037SARM gem5 Developers else 147710037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 147810037SARM gem5 Developers return scr.fiq; 147910037SARM gem5 Developers} 148010037SARM gem5 Developers 148110037SARM gem5 Developersbool 148210037SARM gem5 DevelopersFastInterrupt::routeToHyp(ThreadContext *tc) const 148310037SARM gem5 Developers{ 148410037SARM gem5 Developers bool toHyp; 148510037SARM gem5 Developers 148610037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 148710037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 148810037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 148910037SARM gem5 Developers // Determine whether IRQs are routed to Hyp mode. 149011581SDylan.Johnson@ARM.com toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) || 149110037SARM gem5 Developers (cpsr.mode == MODE_HYP); 149210037SARM gem5 Developers return toHyp; 149310037SARM gem5 Developers} 149410037SARM gem5 Developers 149510037SARM gem5 Developersbool 149610037SARM gem5 DevelopersFastInterrupt::abortDisable(ThreadContext *tc) 149710037SARM gem5 Developers{ 149810037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 149910037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 150010037SARM gem5 Developers return (!scr.ns || scr.aw); 150110037SARM gem5 Developers } 150210037SARM gem5 Developers return true; 150310037SARM gem5 Developers} 150410037SARM gem5 Developers 150510037SARM gem5 Developersbool 150610037SARM gem5 DevelopersFastInterrupt::fiqDisable(ThreadContext *tc) 150710037SARM gem5 Developers{ 150810037SARM gem5 Developers if (ArmSystem::haveVirtualization(tc)) { 150910037SARM gem5 Developers return true; 151010037SARM gem5 Developers } else if (ArmSystem::haveSecurity(tc)) { 151110037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 151210037SARM gem5 Developers return (!scr.ns || scr.fw); 151310037SARM gem5 Developers } 151410037SARM gem5 Developers return true; 151510037SARM gem5 Developers} 151610037SARM gem5 Developers 151710037SARM gem5 DevelopersVirtualFastInterrupt::VirtualFastInterrupt() 151810037SARM gem5 Developers{} 151910037SARM gem5 Developers 152010037SARM gem5 Developersvoid 152110417Sandreas.hansson@arm.comPCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 152210037SARM gem5 Developers{ 152310037SARM gem5 Developers ArmFaultVals<PCAlignmentFault>::invoke(tc, inst); 152410037SARM gem5 Developers assert(from64); 152510037SARM gem5 Developers // Set the FAR 152610037SARM gem5 Developers tc->setMiscReg(getFaultAddrReg64(), faultPC); 152710037SARM gem5 Developers} 152810037SARM gem5 Developers 152912568Sgiacomo.travaglini@arm.combool 153012568Sgiacomo.travaglini@arm.comPCAlignmentFault::routeToHyp(ThreadContext *tc) const 153112568Sgiacomo.travaglini@arm.com{ 153212568Sgiacomo.travaglini@arm.com bool toHyp = false; 153312568Sgiacomo.travaglini@arm.com 153412568Sgiacomo.travaglini@arm.com SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 153512568Sgiacomo.travaglini@arm.com HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 153612568Sgiacomo.travaglini@arm.com CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 153712568Sgiacomo.travaglini@arm.com 153812568Sgiacomo.travaglini@arm.com // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 153912568Sgiacomo.travaglini@arm.com toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); 154012568Sgiacomo.travaglini@arm.com return toHyp; 154112568Sgiacomo.travaglini@arm.com} 154212568Sgiacomo.travaglini@arm.com 154310037SARM gem5 DevelopersSPAlignmentFault::SPAlignmentFault() 154410037SARM gem5 Developers{} 154510037SARM gem5 Developers 154610037SARM gem5 DevelopersSystemError::SystemError() 154710037SARM gem5 Developers{} 154810037SARM gem5 Developers 154910037SARM gem5 Developersvoid 155010417Sandreas.hansson@arm.comSystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst) 155110037SARM gem5 Developers{ 155211150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 155310037SARM gem5 Developers ArmFault::invoke(tc, inst); 155410037SARM gem5 Developers} 155510037SARM gem5 Developers 155610037SARM gem5 Developersbool 155710037SARM gem5 DevelopersSystemError::routeToMonitor(ThreadContext *tc) const 155810037SARM gem5 Developers{ 155910037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 156010037SARM gem5 Developers assert(from64); 156110037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 156210037SARM gem5 Developers return scr.ea; 156310037SARM gem5 Developers} 156410037SARM gem5 Developers 156510037SARM gem5 Developersbool 156610037SARM gem5 DevelopersSystemError::routeToHyp(ThreadContext *tc) const 156710037SARM gem5 Developers{ 156810037SARM gem5 Developers bool toHyp; 156910037SARM gem5 Developers assert(from64); 157010037SARM gem5 Developers 157110037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 157210037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 157310037SARM gem5 Developers 157411581SDylan.Johnson@ARM.com toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) || 157511581SDylan.Johnson@ARM.com (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc)); 157610037SARM gem5 Developers return toHyp; 15777362Sgblack@eecs.umich.edu} 15787362Sgblack@eecs.umich.edu 157912299Sandreas.sandberg@arm.com 158012299Sandreas.sandberg@arm.comSoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss) 158112299Sandreas.sandberg@arm.com : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss) 158212299Sandreas.sandberg@arm.com{} 158312299Sandreas.sandberg@arm.com 158412299Sandreas.sandberg@arm.combool 158512299Sandreas.sandberg@arm.comSoftwareBreakpoint::routeToHyp(ThreadContext *tc) const 158612299Sandreas.sandberg@arm.com{ 158712299Sandreas.sandberg@arm.com const bool have_el2 = ArmSystem::haveVirtualization(tc); 158812299Sandreas.sandberg@arm.com 158912299Sandreas.sandberg@arm.com const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 159012299Sandreas.sandberg@arm.com const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); 159112299Sandreas.sandberg@arm.com 159212299Sandreas.sandberg@arm.com return have_el2 && !inSecureState(tc) && fromEL <= EL1 && 159312299Sandreas.sandberg@arm.com (hcr.tge || mdcr.tde); 159412299Sandreas.sandberg@arm.com} 159512299Sandreas.sandberg@arm.com 159612732Sandreas.sandberg@arm.comExceptionClass 159712732Sandreas.sandberg@arm.comSoftwareBreakpoint::ec(ThreadContext *tc) const 159812732Sandreas.sandberg@arm.com{ 159912732Sandreas.sandberg@arm.com return from64 ? EC_SOFTWARE_BREAKPOINT_64 : vals.ec; 160012732Sandreas.sandberg@arm.com} 160112732Sandreas.sandberg@arm.com 16027652Sminkyu.jeong@arm.comvoid 160310417Sandreas.hansson@arm.comArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 16048518Sgeoffrey.blake@arm.com DPRINTF(Faults, "Invoking ArmSev Fault\n"); 16058806Sgblack@eecs.umich.edu if (!FullSystem) 16068806Sgblack@eecs.umich.edu return; 16078806Sgblack@eecs.umich.edu 16088806Sgblack@eecs.umich.edu // Set sev_mailbox to 1, clear the pending interrupt from remote 16098806Sgblack@eecs.umich.edu // SEV execution and let pipeline continue as pcState is still 16108806Sgblack@eecs.umich.edu // valid. 16118806Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 161211150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0); 16138518Sgeoffrey.blake@arm.com} 16148518Sgeoffrey.blake@arm.com 161510037SARM gem5 Developers// Instantiate all the templates to make the linker happy 161610037SARM gem5 Developerstemplate class ArmFaultVals<Reset>; 161710037SARM gem5 Developerstemplate class ArmFaultVals<UndefinedInstruction>; 161810037SARM gem5 Developerstemplate class ArmFaultVals<SupervisorCall>; 161910037SARM gem5 Developerstemplate class ArmFaultVals<SecureMonitorCall>; 162010037SARM gem5 Developerstemplate class ArmFaultVals<HypervisorCall>; 162110037SARM gem5 Developerstemplate class ArmFaultVals<PrefetchAbort>; 162210037SARM gem5 Developerstemplate class ArmFaultVals<DataAbort>; 162310037SARM gem5 Developerstemplate class ArmFaultVals<VirtualDataAbort>; 162410037SARM gem5 Developerstemplate class ArmFaultVals<HypervisorTrap>; 162510037SARM gem5 Developerstemplate class ArmFaultVals<Interrupt>; 162610037SARM gem5 Developerstemplate class ArmFaultVals<VirtualInterrupt>; 162710037SARM gem5 Developerstemplate class ArmFaultVals<FastInterrupt>; 162810037SARM gem5 Developerstemplate class ArmFaultVals<VirtualFastInterrupt>; 162910037SARM gem5 Developerstemplate class ArmFaultVals<SupervisorTrap>; 163010037SARM gem5 Developerstemplate class ArmFaultVals<SecureMonitorTrap>; 163110037SARM gem5 Developerstemplate class ArmFaultVals<PCAlignmentFault>; 163210037SARM gem5 Developerstemplate class ArmFaultVals<SPAlignmentFault>; 163310037SARM gem5 Developerstemplate class ArmFaultVals<SystemError>; 163412299Sandreas.sandberg@arm.comtemplate class ArmFaultVals<SoftwareBreakpoint>; 163510037SARM gem5 Developerstemplate class ArmFaultVals<ArmSev>; 163610037SARM gem5 Developerstemplate class AbortFault<PrefetchAbort>; 163710037SARM gem5 Developerstemplate class AbortFault<DataAbort>; 163810037SARM gem5 Developerstemplate class AbortFault<VirtualDataAbort>; 163910037SARM gem5 Developers 164010037SARM gem5 Developers 164110037SARM gem5 DevelopersIllegalInstSetStateFault::IllegalInstSetStateFault() 164210037SARM gem5 Developers{} 164310037SARM gem5 Developers 164414091Sgabor.dozsa@arm.combool 164514091Sgabor.dozsa@arm.comgetFaultVAddr(Fault fault, Addr &va) 164614091Sgabor.dozsa@arm.com{ 164714091Sgabor.dozsa@arm.com auto arm_fault = dynamic_cast<ArmFault *>(fault.get()); 164814091Sgabor.dozsa@arm.com 164914091Sgabor.dozsa@arm.com if (arm_fault) { 165014091Sgabor.dozsa@arm.com return arm_fault->getFaultVAddr(va); 165114091Sgabor.dozsa@arm.com } else { 165214091Sgabor.dozsa@arm.com auto pgt_fault = dynamic_cast<GenericPageTableFault *>(fault.get()); 165314091Sgabor.dozsa@arm.com if (pgt_fault) { 165414091Sgabor.dozsa@arm.com va = pgt_fault->getFaultVAddr(); 165514091Sgabor.dozsa@arm.com return true; 165614091Sgabor.dozsa@arm.com } 165714091Sgabor.dozsa@arm.com 165814091Sgabor.dozsa@arm.com auto align_fault = dynamic_cast<GenericAlignmentFault *>(fault.get()); 165914091Sgabor.dozsa@arm.com if (align_fault) { 166014091Sgabor.dozsa@arm.com va = align_fault->getFaultVAddr(); 166114091Sgabor.dozsa@arm.com return true; 166214091Sgabor.dozsa@arm.com } 166314091Sgabor.dozsa@arm.com 166414091Sgabor.dozsa@arm.com // Return false since it's not an address triggered exception 166514091Sgabor.dozsa@arm.com return false; 166614091Sgabor.dozsa@arm.com } 166714091Sgabor.dozsa@arm.com} 16686019Shines@cs.fsu.edu 16696019Shines@cs.fsu.edu} // namespace ArmISA 1670