faults.cc revision 12509
16019Shines@cs.fsu.edu/* 212509Schuan.zhu@arm.com * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416735Sgblack@eecs.umich.edu * Authors: Ali Saidi 426735Sgblack@eecs.umich.edu * Gabe Black 4310037SARM gem5 Developers * Giacomo Gabrielli 4410037SARM gem5 Developers * Thomas Grocutt 456019Shines@cs.fsu.edu */ 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#include "arch/arm/faults.hh" 4811793Sbrandon.potter@amd.com 4911793Sbrandon.potter@amd.com#include "arch/arm/insts/static_inst.hh" 5010037SARM gem5 Developers#include "arch/arm/system.hh" 5110037SARM gem5 Developers#include "arch/arm/utility.hh" 5210037SARM gem5 Developers#include "base/compiler.hh" 538229Snate@binkert.org#include "base/trace.hh" 548229Snate@binkert.org#include "cpu/base.hh" 556019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 568232Snate@binkert.org#include "debug/Faults.hh" 578782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edunamespace ArmISA 606019Shines@cs.fsu.edu{ 616019Shines@cs.fsu.edu 6210037SARM gem5 Developersuint8_t ArmFault::shortDescFaultSources[] = { 6310037SARM gem5 Developers 0x01, // AlignmentFault 6410037SARM gem5 Developers 0x04, // InstructionCacheMaintenance 6510037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 6610037SARM gem5 Developers 0x0c, // SynchExtAbtOnTranslTableWalkL1 6710037SARM gem5 Developers 0x0e, // SynchExtAbtOnTranslTableWalkL2 6810037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID) 6910037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 7010037SARM gem5 Developers 0x1c, // SynchPtyErrOnTranslTableWalkL1 7110037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 7210037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID) 7310037SARM gem5 Developers 0xff, // TranslationL0 (INVALID) 7410037SARM gem5 Developers 0x05, // TranslationL1 7510037SARM gem5 Developers 0x07, // TranslationL2 7610037SARM gem5 Developers 0xff, // TranslationL3 (INVALID) 7710037SARM gem5 Developers 0xff, // AccessFlagL0 (INVALID) 7810037SARM gem5 Developers 0x03, // AccessFlagL1 7910037SARM gem5 Developers 0x06, // AccessFlagL2 8010037SARM gem5 Developers 0xff, // AccessFlagL3 (INVALID) 8110037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 8210037SARM gem5 Developers 0x09, // DomainL1 8310037SARM gem5 Developers 0x0b, // DomainL2 8410037SARM gem5 Developers 0xff, // DomainL3 (INVALID) 8510037SARM gem5 Developers 0xff, // PermissionL0 (INVALID) 8610037SARM gem5 Developers 0x0d, // PermissionL1 8710037SARM gem5 Developers 0x0f, // PermissionL2 8810037SARM gem5 Developers 0xff, // PermissionL3 (INVALID) 8910037SARM gem5 Developers 0x02, // DebugEvent 9010037SARM gem5 Developers 0x08, // SynchronousExternalAbort 9110037SARM gem5 Developers 0x10, // TLBConflictAbort 9210037SARM gem5 Developers 0x19, // SynchPtyErrOnMemoryAccess 9310037SARM gem5 Developers 0x16, // AsynchronousExternalAbort 9410037SARM gem5 Developers 0x18, // AsynchPtyErrOnMemoryAccess 9510037SARM gem5 Developers 0xff, // AddressSizeL0 (INVALID) 9610037SARM gem5 Developers 0xff, // AddressSizeL1 (INVALID) 9710037SARM gem5 Developers 0xff, // AddressSizeL2 (INVALID) 9810037SARM gem5 Developers 0xff, // AddressSizeL3 (INVALID) 9910037SARM gem5 Developers 0x40, // PrefetchTLBMiss 10010037SARM gem5 Developers 0x80 // PrefetchUncacheable 10110037SARM gem5 Developers}; 1026019Shines@cs.fsu.edu 10310037SARM gem5 Developersstatic_assert(sizeof(ArmFault::shortDescFaultSources) == 10410037SARM gem5 Developers ArmFault::NumFaultSources, 10510037SARM gem5 Developers "Invalid size of ArmFault::shortDescFaultSources[]"); 1066019Shines@cs.fsu.edu 10710037SARM gem5 Developersuint8_t ArmFault::longDescFaultSources[] = { 10810037SARM gem5 Developers 0x21, // AlignmentFault 10910037SARM gem5 Developers 0xff, // InstructionCacheMaintenance (INVALID) 11010037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 11110037SARM gem5 Developers 0x15, // SynchExtAbtOnTranslTableWalkL1 11210037SARM gem5 Developers 0x16, // SynchExtAbtOnTranslTableWalkL2 11310037SARM gem5 Developers 0x17, // SynchExtAbtOnTranslTableWalkL3 11410037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 11510037SARM gem5 Developers 0x1d, // SynchPtyErrOnTranslTableWalkL1 11610037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 11710037SARM gem5 Developers 0x1f, // SynchPtyErrOnTranslTableWalkL3 11810037SARM gem5 Developers 0xff, // TranslationL0 (INVALID) 11910037SARM gem5 Developers 0x05, // TranslationL1 12010037SARM gem5 Developers 0x06, // TranslationL2 12110037SARM gem5 Developers 0x07, // TranslationL3 12210037SARM gem5 Developers 0xff, // AccessFlagL0 (INVALID) 12310037SARM gem5 Developers 0x09, // AccessFlagL1 12410037SARM gem5 Developers 0x0a, // AccessFlagL2 12510037SARM gem5 Developers 0x0b, // AccessFlagL3 12610037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 12710037SARM gem5 Developers 0x3d, // DomainL1 12810037SARM gem5 Developers 0x3e, // DomainL2 12910037SARM gem5 Developers 0xff, // DomainL3 (RESERVED) 13010037SARM gem5 Developers 0xff, // PermissionL0 (INVALID) 13110037SARM gem5 Developers 0x0d, // PermissionL1 13210037SARM gem5 Developers 0x0e, // PermissionL2 13310037SARM gem5 Developers 0x0f, // PermissionL3 13410037SARM gem5 Developers 0x22, // DebugEvent 13510037SARM gem5 Developers 0x10, // SynchronousExternalAbort 13610037SARM gem5 Developers 0x30, // TLBConflictAbort 13710037SARM gem5 Developers 0x18, // SynchPtyErrOnMemoryAccess 13810037SARM gem5 Developers 0x11, // AsynchronousExternalAbort 13910037SARM gem5 Developers 0x19, // AsynchPtyErrOnMemoryAccess 14010037SARM gem5 Developers 0xff, // AddressSizeL0 (INVALID) 14110037SARM gem5 Developers 0xff, // AddressSizeL1 (INVALID) 14210037SARM gem5 Developers 0xff, // AddressSizeL2 (INVALID) 14310037SARM gem5 Developers 0xff, // AddressSizeL3 (INVALID) 14410037SARM gem5 Developers 0x40, // PrefetchTLBMiss 14510037SARM gem5 Developers 0x80 // PrefetchUncacheable 14610037SARM gem5 Developers}; 1476019Shines@cs.fsu.edu 14810037SARM gem5 Developersstatic_assert(sizeof(ArmFault::longDescFaultSources) == 14910037SARM gem5 Developers ArmFault::NumFaultSources, 15010037SARM gem5 Developers "Invalid size of ArmFault::longDescFaultSources[]"); 1516019Shines@cs.fsu.edu 15210037SARM gem5 Developersuint8_t ArmFault::aarch64FaultSources[] = { 15310037SARM gem5 Developers 0x21, // AlignmentFault 15410037SARM gem5 Developers 0xff, // InstructionCacheMaintenance (INVALID) 15510037SARM gem5 Developers 0x14, // SynchExtAbtOnTranslTableWalkL0 15610037SARM gem5 Developers 0x15, // SynchExtAbtOnTranslTableWalkL1 15710037SARM gem5 Developers 0x16, // SynchExtAbtOnTranslTableWalkL2 15810037SARM gem5 Developers 0x17, // SynchExtAbtOnTranslTableWalkL3 15910037SARM gem5 Developers 0x1c, // SynchPtyErrOnTranslTableWalkL0 16010037SARM gem5 Developers 0x1d, // SynchPtyErrOnTranslTableWalkL1 16110037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 16210037SARM gem5 Developers 0x1f, // SynchPtyErrOnTranslTableWalkL3 16310037SARM gem5 Developers 0x04, // TranslationL0 16410037SARM gem5 Developers 0x05, // TranslationL1 16510037SARM gem5 Developers 0x06, // TranslationL2 16610037SARM gem5 Developers 0x07, // TranslationL3 16710037SARM gem5 Developers 0x08, // AccessFlagL0 16810037SARM gem5 Developers 0x09, // AccessFlagL1 16910037SARM gem5 Developers 0x0a, // AccessFlagL2 17010037SARM gem5 Developers 0x0b, // AccessFlagL3 17110037SARM gem5 Developers // @todo: Section & Page Domain Fault in AArch64? 17210037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 17310037SARM gem5 Developers 0xff, // DomainL1 (INVALID) 17410037SARM gem5 Developers 0xff, // DomainL2 (INVALID) 17510037SARM gem5 Developers 0xff, // DomainL3 (INVALID) 17610037SARM gem5 Developers 0x0c, // PermissionL0 17710037SARM gem5 Developers 0x0d, // PermissionL1 17810037SARM gem5 Developers 0x0e, // PermissionL2 17910037SARM gem5 Developers 0x0f, // PermissionL3 18010037SARM gem5 Developers 0xff, // DebugEvent (INVALID) 18110037SARM gem5 Developers 0x10, // SynchronousExternalAbort 18210037SARM gem5 Developers 0x30, // TLBConflictAbort 18310037SARM gem5 Developers 0x18, // SynchPtyErrOnMemoryAccess 18410037SARM gem5 Developers 0xff, // AsynchronousExternalAbort (INVALID) 18510037SARM gem5 Developers 0xff, // AsynchPtyErrOnMemoryAccess (INVALID) 18610037SARM gem5 Developers 0x00, // AddressSizeL0 18710037SARM gem5 Developers 0x01, // AddressSizeL1 18810037SARM gem5 Developers 0x02, // AddressSizeL2 18910037SARM gem5 Developers 0x03, // AddressSizeL3 19010037SARM gem5 Developers 0x40, // PrefetchTLBMiss 19110037SARM gem5 Developers 0x80 // PrefetchUncacheable 19210037SARM gem5 Developers}; 1936019Shines@cs.fsu.edu 19410037SARM gem5 Developersstatic_assert(sizeof(ArmFault::aarch64FaultSources) == 19510037SARM gem5 Developers ArmFault::NumFaultSources, 19610037SARM gem5 Developers "Invalid size of ArmFault::aarch64FaultSources[]"); 1976019Shines@cs.fsu.edu 19810037SARM gem5 Developers// Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode, 19910037SARM gem5 Developers// {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap, 20010037SARM gem5 Developers// {A, F} disable, class, stat 20110037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals = { 20210037SARM gem5 Developers // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED 20310037SARM gem5 Developers // location in AArch64) 20410037SARM gem5 Developers "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 20510037SARM gem5 Developers 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 20610037SARM gem5 Developers}; 20710037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals = { 20810037SARM gem5 Developers "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 20910037SARM gem5 Developers 4, 2, 0, 0, true, false, false, EC_UNKNOWN, FaultStat() 21010037SARM gem5 Developers}; 21110037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals = { 21210037SARM gem5 Developers "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 21310037SARM gem5 Developers 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP, FaultStat() 21410037SARM gem5 Developers}; 21510037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals = { 21610037SARM gem5 Developers "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 21710037SARM gem5 Developers 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP, FaultStat() 21810037SARM gem5 Developers}; 21910037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals = { 22010037SARM gem5 Developers "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 22110037SARM gem5 Developers 4, 4, 4, 4, true, false, false, EC_HVC, FaultStat() 22210037SARM gem5 Developers}; 22310037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals = { 22410037SARM gem5 Developers "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 22510037SARM gem5 Developers 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP, FaultStat() 22610037SARM gem5 Developers}; 22710037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals = { 22810037SARM gem5 Developers "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 22910037SARM gem5 Developers 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP, FaultStat() 23010037SARM gem5 Developers}; 23110037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals = { 23210037SARM gem5 Developers "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 23310037SARM gem5 Developers 8, 8, 0, 0, true, true, false, EC_INVALID, FaultStat() 23410037SARM gem5 Developers}; 23510037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals = { 23610037SARM gem5 Developers // @todo: double check these values 23710037SARM gem5 Developers "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 23810037SARM gem5 Developers 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat() 23910037SARM gem5 Developers}; 24010037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = { 24110037SARM gem5 Developers "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 24210037SARM gem5 Developers 4, 4, 0, 0, false, true, false, EC_UNKNOWN, FaultStat() 24310037SARM gem5 Developers}; 24410037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals = { 24510037SARM gem5 Developers "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 24610037SARM gem5 Developers 4, 4, 0, 0, false, true, false, EC_INVALID, FaultStat() 24710037SARM gem5 Developers}; 24810037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = { 24910037SARM gem5 Developers "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 25010037SARM gem5 Developers 4, 4, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 25110037SARM gem5 Developers}; 25210037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals = { 25310037SARM gem5 Developers "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 25410037SARM gem5 Developers 4, 4, 0, 0, false, true, true, EC_INVALID, FaultStat() 25510037SARM gem5 Developers}; 25610037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals = { 25710037SARM gem5 Developers // Some dummy values (SupervisorTrap is AArch64-only) 25810037SARM gem5 Developers "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 25910037SARM gem5 Developers 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat() 26010037SARM gem5 Developers}; 26110037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals = { 26210037SARM gem5 Developers // Some dummy values (SecureMonitorTrap is AArch64-only) 26310037SARM gem5 Developers "Secure Monitor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_MON, 26410037SARM gem5 Developers 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat() 26510037SARM gem5 Developers}; 26610037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals = { 26710037SARM gem5 Developers // Some dummy values (PCAlignmentFault is AArch64-only) 26810037SARM gem5 Developers "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 26910037SARM gem5 Developers 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT, FaultStat() 27010037SARM gem5 Developers}; 27110037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals = { 27210037SARM gem5 Developers // Some dummy values (SPAlignmentFault is AArch64-only) 27310037SARM gem5 Developers "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 27410037SARM gem5 Developers 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT, FaultStat() 27510037SARM gem5 Developers}; 27610037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals = { 27710037SARM gem5 Developers // Some dummy values (SError is AArch64-only) 27810037SARM gem5 Developers "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 27910037SARM gem5 Developers 0, 0, 0, 0, false, true, true, EC_SERROR, FaultStat() 28010037SARM gem5 Developers}; 28112299Sandreas.sandberg@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals = { 28212299Sandreas.sandberg@arm.com // Some dummy values (SoftwareBreakpoint is AArch64-only) 28312299Sandreas.sandberg@arm.com "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 28412299Sandreas.sandberg@arm.com 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT, FaultStat() 28512299Sandreas.sandberg@arm.com}; 28610037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = { 28710037SARM gem5 Developers // Some dummy values 28810037SARM gem5 Developers "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 28910037SARM gem5 Developers 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 29010037SARM gem5 Developers}; 29110037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals = { 29210037SARM gem5 Developers // Some dummy values (SPAlignmentFault is AArch64-only) 29310037SARM gem5 Developers "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 29410037SARM gem5 Developers 0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST, FaultStat() 29510037SARM gem5 Developers}; 2966019Shines@cs.fsu.edu 29710037SARM gem5 DevelopersAddr 2987362Sgblack@eecs.umich.eduArmFault::getVector(ThreadContext *tc) 2996735Sgblack@eecs.umich.edu{ 30010037SARM gem5 Developers Addr base; 3016019Shines@cs.fsu.edu 30210037SARM gem5 Developers // ARM ARM issue C B1.8.1 30310037SARM gem5 Developers bool haveSecurity = ArmSystem::haveSecurity(tc); 3047400SAli.Saidi@ARM.com 3056735Sgblack@eecs.umich.edu // panic if SCTLR.VE because I have no idea what to do with vectored 3066735Sgblack@eecs.umich.edu // interrupts 30710037SARM gem5 Developers SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 3086735Sgblack@eecs.umich.edu assert(!sctlr.ve); 30910037SARM gem5 Developers // Check for invalid modes 31010037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 31110037SARM gem5 Developers assert(haveSecurity || cpsr.mode != MODE_MON); 31210037SARM gem5 Developers assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); 3137400SAli.Saidi@ARM.com 31410037SARM gem5 Developers switch (cpsr.mode) 31510037SARM gem5 Developers { 31610037SARM gem5 Developers case MODE_MON: 31710037SARM gem5 Developers base = tc->readMiscReg(MISCREG_MVBAR); 31810037SARM gem5 Developers break; 31910037SARM gem5 Developers case MODE_HYP: 32010037SARM gem5 Developers base = tc->readMiscReg(MISCREG_HVBAR); 32110037SARM gem5 Developers break; 32210037SARM gem5 Developers default: 32310037SARM gem5 Developers if (sctlr.v) { 32410037SARM gem5 Developers base = HighVecs; 32510037SARM gem5 Developers } else { 32610037SARM gem5 Developers base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0; 32710037SARM gem5 Developers } 32810037SARM gem5 Developers break; 32910037SARM gem5 Developers } 33010037SARM gem5 Developers return base + offset(tc); 3316019Shines@cs.fsu.edu} 3326019Shines@cs.fsu.edu 33310037SARM gem5 DevelopersAddr 33410037SARM gem5 DevelopersArmFault::getVector64(ThreadContext *tc) 33510037SARM gem5 Developers{ 33610037SARM gem5 Developers Addr vbar; 33710037SARM gem5 Developers switch (toEL) { 33810037SARM gem5 Developers case EL3: 33910037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 34010037SARM gem5 Developers vbar = tc->readMiscReg(MISCREG_VBAR_EL3); 34110037SARM gem5 Developers break; 34211574SCurtis.Dunham@arm.com case EL2: 34311574SCurtis.Dunham@arm.com assert(ArmSystem::haveVirtualization(tc)); 34411574SCurtis.Dunham@arm.com vbar = tc->readMiscReg(MISCREG_VBAR_EL2); 34511574SCurtis.Dunham@arm.com break; 34610037SARM gem5 Developers case EL1: 34710037SARM gem5 Developers vbar = tc->readMiscReg(MISCREG_VBAR_EL1); 34810037SARM gem5 Developers break; 34910037SARM gem5 Developers default: 35010037SARM gem5 Developers panic("Invalid target exception level"); 35110037SARM gem5 Developers break; 35210037SARM gem5 Developers } 35310037SARM gem5 Developers return vbar + offset64(); 35410037SARM gem5 Developers} 35510037SARM gem5 Developers 35610037SARM gem5 DevelopersMiscRegIndex 35710037SARM gem5 DevelopersArmFault::getSyndromeReg64() const 35810037SARM gem5 Developers{ 35910037SARM gem5 Developers switch (toEL) { 36010037SARM gem5 Developers case EL1: 36110037SARM gem5 Developers return MISCREG_ESR_EL1; 36210037SARM gem5 Developers case EL2: 36310037SARM gem5 Developers return MISCREG_ESR_EL2; 36410037SARM gem5 Developers case EL3: 36510037SARM gem5 Developers return MISCREG_ESR_EL3; 36610037SARM gem5 Developers default: 36710037SARM gem5 Developers panic("Invalid exception level"); 36810037SARM gem5 Developers break; 36910037SARM gem5 Developers } 37010037SARM gem5 Developers} 37110037SARM gem5 Developers 37210037SARM gem5 DevelopersMiscRegIndex 37310037SARM gem5 DevelopersArmFault::getFaultAddrReg64() const 37410037SARM gem5 Developers{ 37510037SARM gem5 Developers switch (toEL) { 37610037SARM gem5 Developers case EL1: 37710037SARM gem5 Developers return MISCREG_FAR_EL1; 37810037SARM gem5 Developers case EL2: 37910037SARM gem5 Developers return MISCREG_FAR_EL2; 38010037SARM gem5 Developers case EL3: 38110037SARM gem5 Developers return MISCREG_FAR_EL3; 38210037SARM gem5 Developers default: 38310037SARM gem5 Developers panic("Invalid exception level"); 38410037SARM gem5 Developers break; 38510037SARM gem5 Developers } 38610037SARM gem5 Developers} 38710037SARM gem5 Developers 38810037SARM gem5 Developersvoid 38910037SARM gem5 DevelopersArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 39010037SARM gem5 Developers{ 39110037SARM gem5 Developers uint32_t value; 39210037SARM gem5 Developers uint32_t exc_class = (uint32_t) ec(tc); 39310037SARM gem5 Developers uint32_t issVal = iss(); 39412402Sgiacomo.travaglini@arm.com 39510037SARM gem5 Developers assert(!from64 || ArmSystem::highestELIs64(tc)); 39610037SARM gem5 Developers 39710037SARM gem5 Developers value = exc_class << 26; 39810037SARM gem5 Developers 39910037SARM gem5 Developers // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24, 40010037SARM gem5 Developers // 0x25) for which the ISS information is not valid (ARMv7). 40110037SARM gem5 Developers // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not 40210037SARM gem5 Developers // valid it is treated as RES1. 40310037SARM gem5 Developers if (to64) { 40410037SARM gem5 Developers value |= 1 << 25; 40510037SARM gem5 Developers } else if ((bits(exc_class, 5, 3) != 4) || 40610037SARM gem5 Developers (bits(exc_class, 2) && bits(issVal, 24))) { 40710037SARM gem5 Developers if (!machInst.thumb || machInst.bigThumb) 40810037SARM gem5 Developers value |= 1 << 25; 40910037SARM gem5 Developers } 41010037SARM gem5 Developers // Condition code valid for EC[5:4] nonzero 41110037SARM gem5 Developers if (!from64 && ((bits(exc_class, 5, 4) == 0) && 41210037SARM gem5 Developers (bits(exc_class, 3, 0) != 0))) { 41310037SARM gem5 Developers if (!machInst.thumb) { 41410037SARM gem5 Developers uint32_t cond; 41510037SARM gem5 Developers ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode; 41610037SARM gem5 Developers // If its on unconditional instruction report with a cond code of 41710037SARM gem5 Developers // 0xE, ie the unconditional code 41810037SARM gem5 Developers cond = (condCode == COND_UC) ? COND_AL : condCode; 41910037SARM gem5 Developers value |= cond << 20; 42010037SARM gem5 Developers value |= 1 << 24; 42110037SARM gem5 Developers } 42210037SARM gem5 Developers value |= bits(issVal, 19, 0); 42310037SARM gem5 Developers } else { 42410037SARM gem5 Developers value |= issVal; 42510037SARM gem5 Developers } 42610037SARM gem5 Developers tc->setMiscReg(syndrome_reg, value); 42710037SARM gem5 Developers} 42810037SARM gem5 Developers 42910037SARM gem5 Developersvoid 43010417Sandreas.hansson@arm.comArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 4316019Shines@cs.fsu.edu{ 43210037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 43310037SARM gem5 Developers 43410037SARM gem5 Developers if (ArmSystem::highestELIs64(tc)) { // ARMv8 43510037SARM gem5 Developers // Determine source exception level and mode 43610037SARM gem5 Developers fromMode = (OperatingMode) (uint8_t) cpsr.mode; 43710037SARM gem5 Developers fromEL = opModeToEL(fromMode); 43810037SARM gem5 Developers if (opModeIs64(fromMode)) 43910037SARM gem5 Developers from64 = true; 44010037SARM gem5 Developers 44110037SARM gem5 Developers // Determine target exception level 44212402Sgiacomo.travaglini@arm.com if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) { 44310037SARM gem5 Developers toEL = EL3; 44412402Sgiacomo.travaglini@arm.com } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) { 44511578SDylan.Johnson@ARM.com toEL = EL2; 44612402Sgiacomo.travaglini@arm.com hypRouted = true; 44712402Sgiacomo.travaglini@arm.com } else { 44810037SARM gem5 Developers toEL = opModeToEL(nextMode()); 44912402Sgiacomo.travaglini@arm.com } 45012402Sgiacomo.travaglini@arm.com 45110037SARM gem5 Developers if (fromEL > toEL) 45210037SARM gem5 Developers toEL = fromEL; 45310037SARM gem5 Developers 45410037SARM gem5 Developers if (toEL == ArmSystem::highestEL(tc) || ELIs64(tc, toEL)) { 45510037SARM gem5 Developers // Invoke exception handler in AArch64 state 45610037SARM gem5 Developers to64 = true; 45710037SARM gem5 Developers invoke64(tc, inst); 45810037SARM gem5 Developers return; 45910037SARM gem5 Developers } 46010037SARM gem5 Developers } 46110037SARM gem5 Developers 46210037SARM gem5 Developers // ARMv7 (ARM ARM issue C B1.9) 46310037SARM gem5 Developers 46410037SARM gem5 Developers bool have_security = ArmSystem::haveSecurity(tc); 46510037SARM gem5 Developers bool have_virtualization = ArmSystem::haveVirtualization(tc); 46610037SARM gem5 Developers 4676735Sgblack@eecs.umich.edu FaultBase::invoke(tc); 4688782Sgblack@eecs.umich.edu if (!FullSystem) 4698782Sgblack@eecs.umich.edu return; 4706735Sgblack@eecs.umich.edu countStat()++; 4716019Shines@cs.fsu.edu 4726735Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 47310037SARM gem5 Developers SCR scr = tc->readMiscReg(MISCREG_SCR); 4748303SAli.Saidi@ARM.com CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR); 47510338SCurtis.Dunham@arm.com saved_cpsr.nz = tc->readCCReg(CCREG_NZ); 47610338SCurtis.Dunham@arm.com saved_cpsr.c = tc->readCCReg(CCREG_C); 47710338SCurtis.Dunham@arm.com saved_cpsr.v = tc->readCCReg(CCREG_V); 47810338SCurtis.Dunham@arm.com saved_cpsr.ge = tc->readCCReg(CCREG_GE); 4798303SAli.Saidi@ARM.com 4807720Sgblack@eecs.umich.edu Addr curPc M5_VAR_USED = tc->pcState().pc(); 4818205SAli.Saidi@ARM.com ITSTATE it = tc->pcState().itstate(); 4828205SAli.Saidi@ARM.com saved_cpsr.it2 = it.top6; 4838205SAli.Saidi@ARM.com saved_cpsr.it1 = it.bottom2; 4846735Sgblack@eecs.umich.edu 48510037SARM gem5 Developers // if we have a valid instruction then use it to annotate this fault with 48610037SARM gem5 Developers // extra information. This is used to generate the correct fault syndrome 48710037SARM gem5 Developers // information 48810037SARM gem5 Developers if (inst) { 48912398Sgiacomo.travaglini@arm.com ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get()); 49010037SARM gem5 Developers armInst->annotateFault(this); 49110037SARM gem5 Developers } 49210037SARM gem5 Developers 49312402Sgiacomo.travaglini@arm.com if (have_security && routeToMonitor(tc)) { 49410037SARM gem5 Developers cpsr.mode = MODE_MON; 49512402Sgiacomo.travaglini@arm.com } else if (have_virtualization && routeToHyp(tc)) { 49610037SARM gem5 Developers cpsr.mode = MODE_HYP; 49712402Sgiacomo.travaglini@arm.com hypRouted = true; 49812402Sgiacomo.travaglini@arm.com } else { 49910037SARM gem5 Developers cpsr.mode = nextMode(); 50012402Sgiacomo.travaglini@arm.com } 50110037SARM gem5 Developers 50210037SARM gem5 Developers // Ensure Secure state if initially in Monitor mode 50310037SARM gem5 Developers if (have_security && saved_cpsr.mode == MODE_MON) { 50410037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 50510037SARM gem5 Developers if (scr.ns) { 50610037SARM gem5 Developers scr.ns = 0; 50710037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_SCR, scr); 50810037SARM gem5 Developers } 50910037SARM gem5 Developers } 51010037SARM gem5 Developers 51110037SARM gem5 Developers // some bits are set differently if we have been routed to hyp mode 51210037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 51310037SARM gem5 Developers SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR); 51410037SARM gem5 Developers cpsr.t = hsctlr.te; 51510037SARM gem5 Developers cpsr.e = hsctlr.ee; 51610037SARM gem5 Developers if (!scr.ea) {cpsr.a = 1;} 51710037SARM gem5 Developers if (!scr.fiq) {cpsr.f = 1;} 51810037SARM gem5 Developers if (!scr.irq) {cpsr.i = 1;} 51910037SARM gem5 Developers } else if (cpsr.mode == MODE_MON) { 52010037SARM gem5 Developers // Special case handling when entering monitor mode 52110037SARM gem5 Developers cpsr.t = sctlr.te; 52210037SARM gem5 Developers cpsr.e = sctlr.ee; 52310037SARM gem5 Developers cpsr.a = 1; 52410037SARM gem5 Developers cpsr.f = 1; 52510037SARM gem5 Developers cpsr.i = 1; 52610037SARM gem5 Developers } else { 52710037SARM gem5 Developers cpsr.t = sctlr.te; 52810037SARM gem5 Developers cpsr.e = sctlr.ee; 52910037SARM gem5 Developers 53010037SARM gem5 Developers // The *Disable functions are virtual and different per fault 53110037SARM gem5 Developers cpsr.a = cpsr.a | abortDisable(tc); 53210037SARM gem5 Developers cpsr.f = cpsr.f | fiqDisable(tc); 53310037SARM gem5 Developers cpsr.i = 1; 53410037SARM gem5 Developers } 5356735Sgblack@eecs.umich.edu cpsr.it1 = cpsr.it2 = 0; 5366735Sgblack@eecs.umich.edu cpsr.j = 0; 5376735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CPSR, cpsr); 53810037SARM gem5 Developers 5398518Sgeoffrey.blake@arm.com // Make sure mailbox sets to one always 5408518Sgeoffrey.blake@arm.com tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 5416735Sgblack@eecs.umich.edu 54210037SARM gem5 Developers // Clear the exclusive monitor 54310037SARM gem5 Developers tc->setMiscReg(MISCREG_LOCKFLAG, 0); 54410037SARM gem5 Developers 54510037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 54610037SARM gem5 Developers tc->setMiscReg(MISCREG_ELR_HYP, curPc + 54710037SARM gem5 Developers (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true))); 54810037SARM gem5 Developers } else { 54910037SARM gem5 Developers tc->setIntReg(INTREG_LR, curPc + 55010037SARM gem5 Developers (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false))); 55110037SARM gem5 Developers } 55210037SARM gem5 Developers 55310037SARM gem5 Developers switch (cpsr.mode) { 5546735Sgblack@eecs.umich.edu case MODE_FIQ: 5556735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 5566735Sgblack@eecs.umich.edu break; 5576735Sgblack@eecs.umich.edu case MODE_IRQ: 5586735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 5596735Sgblack@eecs.umich.edu break; 5606735Sgblack@eecs.umich.edu case MODE_SVC: 5616735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 5626735Sgblack@eecs.umich.edu break; 56310037SARM gem5 Developers case MODE_MON: 56410037SARM gem5 Developers assert(have_security); 56510037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr); 5666735Sgblack@eecs.umich.edu break; 5676735Sgblack@eecs.umich.edu case MODE_ABORT: 5686735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 5696735Sgblack@eecs.umich.edu break; 57010037SARM gem5 Developers case MODE_UNDEFINED: 57110037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 57210037SARM gem5 Developers if (ec(tc) != EC_UNKNOWN) 57310037SARM gem5 Developers setSyndrome(tc, MISCREG_HSR); 57410037SARM gem5 Developers break; 57510037SARM gem5 Developers case MODE_HYP: 57610037SARM gem5 Developers assert(have_virtualization); 57710037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr); 57810037SARM gem5 Developers setSyndrome(tc, MISCREG_HSR); 57910037SARM gem5 Developers break; 5806735Sgblack@eecs.umich.edu default: 5816735Sgblack@eecs.umich.edu panic("unknown Mode\n"); 5827093Sgblack@eecs.umich.edu } 5837093Sgblack@eecs.umich.edu 5847720Sgblack@eecs.umich.edu Addr newPc = getVector(tc); 5857585SAli.Saidi@arm.com DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n", 5867720Sgblack@eecs.umich.edu name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc); 5877720Sgblack@eecs.umich.edu PCState pc(newPc); 5887720Sgblack@eecs.umich.edu pc.thumb(cpsr.t); 5897720Sgblack@eecs.umich.edu pc.nextThumb(pc.thumb()); 5907720Sgblack@eecs.umich.edu pc.jazelle(cpsr.j); 5917720Sgblack@eecs.umich.edu pc.nextJazelle(pc.jazelle()); 59210037SARM gem5 Developers pc.aarch64(!cpsr.width); 59310037SARM gem5 Developers pc.nextAArch64(!cpsr.width); 5947720Sgblack@eecs.umich.edu tc->pcState(pc); 5956019Shines@cs.fsu.edu} 5967189Sgblack@eecs.umich.edu 5977400SAli.Saidi@ARM.comvoid 59810417Sandreas.hansson@arm.comArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) 59910037SARM gem5 Developers{ 60010037SARM gem5 Developers // Determine actual misc. register indices for ELR_ELx and SPSR_ELx 60110037SARM gem5 Developers MiscRegIndex elr_idx, spsr_idx; 60210037SARM gem5 Developers switch (toEL) { 60310037SARM gem5 Developers case EL1: 60410037SARM gem5 Developers elr_idx = MISCREG_ELR_EL1; 60510037SARM gem5 Developers spsr_idx = MISCREG_SPSR_EL1; 60610037SARM gem5 Developers break; 60711574SCurtis.Dunham@arm.com case EL2: 60811574SCurtis.Dunham@arm.com assert(ArmSystem::haveVirtualization(tc)); 60911574SCurtis.Dunham@arm.com elr_idx = MISCREG_ELR_EL2; 61011574SCurtis.Dunham@arm.com spsr_idx = MISCREG_SPSR_EL2; 61111574SCurtis.Dunham@arm.com break; 61210037SARM gem5 Developers case EL3: 61310037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 61410037SARM gem5 Developers elr_idx = MISCREG_ELR_EL3; 61510037SARM gem5 Developers spsr_idx = MISCREG_SPSR_EL3; 61610037SARM gem5 Developers break; 61710037SARM gem5 Developers default: 61810037SARM gem5 Developers panic("Invalid target exception level"); 61910037SARM gem5 Developers break; 62010037SARM gem5 Developers } 62110037SARM gem5 Developers 62210037SARM gem5 Developers // Save process state into SPSR_ELx 62310037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 62410037SARM gem5 Developers CPSR spsr = cpsr; 62510338SCurtis.Dunham@arm.com spsr.nz = tc->readCCReg(CCREG_NZ); 62610338SCurtis.Dunham@arm.com spsr.c = tc->readCCReg(CCREG_C); 62710338SCurtis.Dunham@arm.com spsr.v = tc->readCCReg(CCREG_V); 62810037SARM gem5 Developers if (from64) { 62910037SARM gem5 Developers // Force some bitfields to 0 63010037SARM gem5 Developers spsr.q = 0; 63110037SARM gem5 Developers spsr.it1 = 0; 63210037SARM gem5 Developers spsr.j = 0; 63310037SARM gem5 Developers spsr.res0_23_22 = 0; 63410037SARM gem5 Developers spsr.ge = 0; 63510037SARM gem5 Developers spsr.it2 = 0; 63610037SARM gem5 Developers spsr.t = 0; 63710037SARM gem5 Developers } else { 63810338SCurtis.Dunham@arm.com spsr.ge = tc->readCCReg(CCREG_GE); 63910037SARM gem5 Developers ITSTATE it = tc->pcState().itstate(); 64010037SARM gem5 Developers spsr.it2 = it.top6; 64110037SARM gem5 Developers spsr.it1 = it.bottom2; 64210037SARM gem5 Developers // Force some bitfields to 0 64310037SARM gem5 Developers spsr.res0_23_22 = 0; 64410037SARM gem5 Developers spsr.ss = 0; 64510037SARM gem5 Developers } 64610037SARM gem5 Developers tc->setMiscReg(spsr_idx, spsr); 64710037SARM gem5 Developers 64810037SARM gem5 Developers // Save preferred return address into ELR_ELx 64910037SARM gem5 Developers Addr curr_pc = tc->pcState().pc(); 65010037SARM gem5 Developers Addr ret_addr = curr_pc; 65110037SARM gem5 Developers if (from64) 65210037SARM gem5 Developers ret_addr += armPcElrOffset(); 65310037SARM gem5 Developers else 65410037SARM gem5 Developers ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset(); 65510037SARM gem5 Developers tc->setMiscReg(elr_idx, ret_addr); 65610037SARM gem5 Developers 65710037SARM gem5 Developers // Update process state 65810037SARM gem5 Developers OperatingMode64 mode = 0; 65910037SARM gem5 Developers mode.spX = 1; 66010037SARM gem5 Developers mode.el = toEL; 66110037SARM gem5 Developers mode.width = 0; 66210037SARM gem5 Developers cpsr.mode = mode; 66310037SARM gem5 Developers cpsr.daif = 0xf; 66410037SARM gem5 Developers cpsr.il = 0; 66510037SARM gem5 Developers cpsr.ss = 0; 66610037SARM gem5 Developers tc->setMiscReg(MISCREG_CPSR, cpsr); 66710037SARM gem5 Developers 66810037SARM gem5 Developers // Set PC to start of exception handler 66910037SARM gem5 Developers Addr new_pc = purifyTaggedAddr(getVector64(tc), tc, toEL); 67010037SARM gem5 Developers DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x " 67110037SARM gem5 Developers "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc); 67210037SARM gem5 Developers PCState pc(new_pc); 67310037SARM gem5 Developers pc.aarch64(!cpsr.width); 67410037SARM gem5 Developers pc.nextAArch64(!cpsr.width); 67510037SARM gem5 Developers tc->pcState(pc); 67610037SARM gem5 Developers 67710037SARM gem5 Developers // If we have a valid instruction then use it to annotate this fault with 67810037SARM gem5 Developers // extra information. This is used to generate the correct fault syndrome 67910037SARM gem5 Developers // information 68010037SARM gem5 Developers if (inst) 68112398Sgiacomo.travaglini@arm.com static_cast<ArmStaticInst *>(inst.get())->annotateFault(this); 68210037SARM gem5 Developers // Save exception syndrome 68310037SARM gem5 Developers if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ)) 68410037SARM gem5 Developers setSyndrome(tc, getSyndromeReg64()); 68510037SARM gem5 Developers} 68610037SARM gem5 Developers 68710037SARM gem5 Developersvoid 68810417Sandreas.hansson@arm.comReset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 6897400SAli.Saidi@ARM.com{ 6908782Sgblack@eecs.umich.edu if (FullSystem) { 69111150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupts(tc->threadId()); 6928782Sgblack@eecs.umich.edu tc->clearArchRegs(); 6938782Sgblack@eecs.umich.edu } 69410037SARM gem5 Developers if (!ArmSystem::highestELIs64(tc)) { 69510037SARM gem5 Developers ArmFault::invoke(tc, inst); 69610037SARM gem5 Developers tc->setMiscReg(MISCREG_VMPIDR, 69710037SARM gem5 Developers getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc)); 69810037SARM gem5 Developers 69910037SARM gem5 Developers // Unless we have SMC code to get us there, boot in HYP! 70010037SARM gem5 Developers if (ArmSystem::haveVirtualization(tc) && 70110037SARM gem5 Developers !ArmSystem::haveSecurity(tc)) { 70210037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 70310037SARM gem5 Developers cpsr.mode = MODE_HYP; 70410037SARM gem5 Developers tc->setMiscReg(MISCREG_CPSR, cpsr); 70510037SARM gem5 Developers } 70610037SARM gem5 Developers } else { 70710037SARM gem5 Developers // Advance the PC to the IMPLEMENTATION DEFINED reset value 70810037SARM gem5 Developers PCState pc = ArmSystem::resetAddr64(tc); 70910037SARM gem5 Developers pc.aarch64(true); 71010037SARM gem5 Developers pc.nextAArch64(true); 71110037SARM gem5 Developers tc->pcState(pc); 71210037SARM gem5 Developers } 7137400SAli.Saidi@ARM.com} 7147400SAli.Saidi@ARM.com 7157189Sgblack@eecs.umich.eduvoid 71610417Sandreas.hansson@arm.comUndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7177189Sgblack@eecs.umich.edu{ 7188782Sgblack@eecs.umich.edu if (FullSystem) { 7198782Sgblack@eecs.umich.edu ArmFault::invoke(tc, inst); 7208806Sgblack@eecs.umich.edu return; 7218806Sgblack@eecs.umich.edu } 7228806Sgblack@eecs.umich.edu 7238806Sgblack@eecs.umich.edu // If the mnemonic isn't defined this has to be an unknown instruction. 7248806Sgblack@eecs.umich.edu assert(unknown || mnemonic != NULL); 7258806Sgblack@eecs.umich.edu if (disabled) { 7268806Sgblack@eecs.umich.edu panic("Attempted to execute disabled instruction " 7278806Sgblack@eecs.umich.edu "'%s' (inst 0x%08x)", mnemonic, machInst); 7288806Sgblack@eecs.umich.edu } else if (unknown) { 7298806Sgblack@eecs.umich.edu panic("Attempted to execute unknown instruction (inst 0x%08x)", 7308806Sgblack@eecs.umich.edu machInst); 7317189Sgblack@eecs.umich.edu } else { 7328806Sgblack@eecs.umich.edu panic("Attempted to execute unimplemented instruction " 7338806Sgblack@eecs.umich.edu "'%s' (inst 0x%08x)", mnemonic, machInst); 7347189Sgblack@eecs.umich.edu } 7357189Sgblack@eecs.umich.edu} 7367189Sgblack@eecs.umich.edu 73710037SARM gem5 Developersbool 73810037SARM gem5 DevelopersUndefinedInstruction::routeToHyp(ThreadContext *tc) const 73910037SARM gem5 Developers{ 74010037SARM gem5 Developers bool toHyp; 74110037SARM gem5 Developers 74210037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 74310037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 74410037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 74510037SARM gem5 Developers 74610037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 74710037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 74810037SARM gem5 Developers // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 74910037SARM gem5 Developers toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 75010037SARM gem5 Developers return toHyp; 75110037SARM gem5 Developers} 75210037SARM gem5 Developers 75310037SARM gem5 Developersuint32_t 75410037SARM gem5 DevelopersUndefinedInstruction::iss() const 75510037SARM gem5 Developers{ 75612402Sgiacomo.travaglini@arm.com 75712402Sgiacomo.travaglini@arm.com // If UndefinedInstruction is routed to hypervisor, iss field is 0. 75812402Sgiacomo.travaglini@arm.com if (hypRouted) { 75912402Sgiacomo.travaglini@arm.com return 0; 76012402Sgiacomo.travaglini@arm.com } 76112402Sgiacomo.travaglini@arm.com 76210037SARM gem5 Developers if (overrideEc == EC_INVALID) 76310037SARM gem5 Developers return issRaw; 76410037SARM gem5 Developers 76510037SARM gem5 Developers uint32_t new_iss = 0; 76610037SARM gem5 Developers uint32_t op0, op1, op2, CRn, CRm, Rt, dir; 76710037SARM gem5 Developers 76810037SARM gem5 Developers dir = bits(machInst, 21, 21); 76910037SARM gem5 Developers op0 = bits(machInst, 20, 19); 77010037SARM gem5 Developers op1 = bits(machInst, 18, 16); 77110037SARM gem5 Developers CRn = bits(machInst, 15, 12); 77210037SARM gem5 Developers CRm = bits(machInst, 11, 8); 77310037SARM gem5 Developers op2 = bits(machInst, 7, 5); 77410037SARM gem5 Developers Rt = bits(machInst, 4, 0); 77510037SARM gem5 Developers 77610037SARM gem5 Developers new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 | 77710037SARM gem5 Developers Rt << 5 | CRm << 1 | dir; 77810037SARM gem5 Developers 77910037SARM gem5 Developers return new_iss; 78010037SARM gem5 Developers} 78110037SARM gem5 Developers 7827197Sgblack@eecs.umich.eduvoid 78310417Sandreas.hansson@arm.comSupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7847197Sgblack@eecs.umich.edu{ 7858782Sgblack@eecs.umich.edu if (FullSystem) { 7868782Sgblack@eecs.umich.edu ArmFault::invoke(tc, inst); 7878806Sgblack@eecs.umich.edu return; 7888806Sgblack@eecs.umich.edu } 7897197Sgblack@eecs.umich.edu 7908806Sgblack@eecs.umich.edu // As of now, there isn't a 32 bit thumb version of this instruction. 7918806Sgblack@eecs.umich.edu assert(!machInst.bigThumb); 7928806Sgblack@eecs.umich.edu uint32_t callNum; 79310037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 79410037SARM gem5 Developers OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode; 79510037SARM gem5 Developers if (opModeIs64(mode)) 79610037SARM gem5 Developers callNum = tc->readIntReg(INTREG_X8); 79710037SARM gem5 Developers else 79810037SARM gem5 Developers callNum = tc->readIntReg(INTREG_R7); 79911877Sbrandon.potter@amd.com Fault fault; 80011877Sbrandon.potter@amd.com tc->syscall(callNum, &fault); 8018806Sgblack@eecs.umich.edu 8028806Sgblack@eecs.umich.edu // Advance the PC since that won't happen automatically. 8038806Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 8048806Sgblack@eecs.umich.edu assert(inst); 8058806Sgblack@eecs.umich.edu inst->advancePC(pc); 8068806Sgblack@eecs.umich.edu tc->pcState(pc); 8077197Sgblack@eecs.umich.edu} 8087197Sgblack@eecs.umich.edu 80910037SARM gem5 Developersbool 81010037SARM gem5 DevelopersSupervisorCall::routeToHyp(ThreadContext *tc) const 81110037SARM gem5 Developers{ 81210037SARM gem5 Developers bool toHyp; 81310037SARM gem5 Developers 81410037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 81510037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 81610037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 81710037SARM gem5 Developers 81810037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 81910037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 82010037SARM gem5 Developers // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 82110037SARM gem5 Developers toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 82210037SARM gem5 Developers return toHyp; 82310037SARM gem5 Developers} 82410037SARM gem5 Developers 82510037SARM gem5 DevelopersExceptionClass 82610037SARM gem5 DevelopersSupervisorCall::ec(ThreadContext *tc) const 82710037SARM gem5 Developers{ 82810037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : 82910037SARM gem5 Developers (from64 ? EC_SVC_64 : vals.ec); 83010037SARM gem5 Developers} 83110037SARM gem5 Developers 83210037SARM gem5 Developersuint32_t 83310037SARM gem5 DevelopersSupervisorCall::iss() const 83410037SARM gem5 Developers{ 83510037SARM gem5 Developers // Even if we have a 24 bit imm from an arm32 instruction then we only use 83610037SARM gem5 Developers // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC). 83710037SARM gem5 Developers return issRaw & 0xFFFF; 83810037SARM gem5 Developers} 83910037SARM gem5 Developers 84010037SARM gem5 Developersuint32_t 84110037SARM gem5 DevelopersSecureMonitorCall::iss() const 84210037SARM gem5 Developers{ 84310037SARM gem5 Developers if (from64) 84410037SARM gem5 Developers return bits(machInst, 20, 5); 84510037SARM gem5 Developers return 0; 84610037SARM gem5 Developers} 84710037SARM gem5 Developers 84810037SARM gem5 DevelopersExceptionClass 84910037SARM gem5 DevelopersUndefinedInstruction::ec(ThreadContext *tc) const 85010037SARM gem5 Developers{ 85112402Sgiacomo.travaglini@arm.com // If UndefinedInstruction is routed to hypervisor, 85212402Sgiacomo.travaglini@arm.com // HSR.EC field is 0. 85312402Sgiacomo.travaglini@arm.com if (hypRouted) 85412402Sgiacomo.travaglini@arm.com return EC_UNKNOWN; 85512402Sgiacomo.travaglini@arm.com else 85612402Sgiacomo.travaglini@arm.com return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 85710037SARM gem5 Developers} 85810037SARM gem5 Developers 85910037SARM gem5 Developers 86010037SARM gem5 DevelopersHypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) : 86110037SARM gem5 Developers ArmFaultVals<HypervisorCall>(_machInst, _imm) 86210037SARM gem5 Developers{} 86310037SARM gem5 Developers 86410037SARM gem5 DevelopersExceptionClass 86511576SDylan.Johnson@ARM.comHypervisorCall::ec(ThreadContext *tc) const 86611576SDylan.Johnson@ARM.com{ 86711576SDylan.Johnson@ARM.com return from64 ? EC_HVC_64 : vals.ec; 86811576SDylan.Johnson@ARM.com} 86911576SDylan.Johnson@ARM.com 87011576SDylan.Johnson@ARM.comExceptionClass 87110037SARM gem5 DevelopersHypervisorTrap::ec(ThreadContext *tc) const 87210037SARM gem5 Developers{ 87310037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 87410037SARM gem5 Developers} 87510037SARM gem5 Developers 87610037SARM gem5 Developerstemplate<class T> 87710037SARM gem5 DevelopersFaultOffset 87810037SARM gem5 DevelopersArmFaultVals<T>::offset(ThreadContext *tc) 87910037SARM gem5 Developers{ 88010037SARM gem5 Developers bool isHypTrap = false; 88110037SARM gem5 Developers 88210037SARM gem5 Developers // Normally we just use the exception vector from the table at the top if 88310037SARM gem5 Developers // this file, however if this exception has caused a transition to hype 88410037SARM gem5 Developers // mode, and its an exception type that would only do this if it has been 88510037SARM gem5 Developers // trapped then we use the hyp trap vector instead of the normal vector 88610037SARM gem5 Developers if (vals.hypTrappable) { 88710037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 88810037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 88910037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 89010037SARM gem5 Developers isHypTrap = spsr.mode != MODE_HYP; 89110037SARM gem5 Developers } 89210037SARM gem5 Developers } 89310037SARM gem5 Developers return isHypTrap ? 0x14 : vals.offset; 89410037SARM gem5 Developers} 89510037SARM gem5 Developers 89610037SARM gem5 Developers// void 89710037SARM gem5 Developers// SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx) 89810037SARM gem5 Developers// { 89910037SARM gem5 Developers// ESR esr = 0; 90010037SARM gem5 Developers// esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32; 90110037SARM gem5 Developers// esr.il = !machInst.thumb; 90210037SARM gem5 Developers// if (machInst.aarch64) 90310037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 20, 5); 90410037SARM gem5 Developers// else if (machInst.thumb) 90510037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 7, 0); 90610037SARM gem5 Developers// else 90710037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 15, 0); 90810037SARM gem5 Developers// tc->setMiscReg(esr_idx, esr); 90910037SARM gem5 Developers// } 91010037SARM gem5 Developers 91110037SARM gem5 Developersvoid 91210417Sandreas.hansson@arm.comSecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 91310037SARM gem5 Developers{ 91410037SARM gem5 Developers if (FullSystem) { 91510037SARM gem5 Developers ArmFault::invoke(tc, inst); 91610037SARM gem5 Developers return; 91710037SARM gem5 Developers } 91810037SARM gem5 Developers} 91910037SARM gem5 Developers 92010037SARM gem5 DevelopersExceptionClass 92110037SARM gem5 DevelopersSecureMonitorCall::ec(ThreadContext *tc) const 92210037SARM gem5 Developers{ 92310037SARM gem5 Developers return (from64 ? EC_SMC_64 : vals.ec); 92410037SARM gem5 Developers} 92510037SARM gem5 Developers 92612509Schuan.zhu@arm.combool 92712509Schuan.zhu@arm.comSupervisorTrap::routeToHyp(ThreadContext *tc) const 92812509Schuan.zhu@arm.com{ 92912509Schuan.zhu@arm.com bool toHyp = false; 93012509Schuan.zhu@arm.com 93112509Schuan.zhu@arm.com SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 93212509Schuan.zhu@arm.com HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 93312509Schuan.zhu@arm.com CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 93412509Schuan.zhu@arm.com 93512509Schuan.zhu@arm.com // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 93612509Schuan.zhu@arm.com toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); 93712509Schuan.zhu@arm.com return toHyp; 93812509Schuan.zhu@arm.com} 93912509Schuan.zhu@arm.com 94012509Schuan.zhu@arm.comuint32_t 94112509Schuan.zhu@arm.comSupervisorTrap::iss() const 94212509Schuan.zhu@arm.com{ 94312509Schuan.zhu@arm.com // If SupervisorTrap is routed to hypervisor, iss field is 0. 94412509Schuan.zhu@arm.com if (hypRouted) { 94512509Schuan.zhu@arm.com return 0; 94612509Schuan.zhu@arm.com } 94712509Schuan.zhu@arm.com return issRaw; 94812509Schuan.zhu@arm.com} 94912509Schuan.zhu@arm.com 95010037SARM gem5 DevelopersExceptionClass 95110037SARM gem5 DevelopersSupervisorTrap::ec(ThreadContext *tc) const 95210037SARM gem5 Developers{ 95312509Schuan.zhu@arm.com if (hypRouted) 95412509Schuan.zhu@arm.com return EC_UNKNOWN; 95512509Schuan.zhu@arm.com else 95612509Schuan.zhu@arm.com return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 95710037SARM gem5 Developers} 95810037SARM gem5 Developers 95910037SARM gem5 DevelopersExceptionClass 96010037SARM gem5 DevelopersSecureMonitorTrap::ec(ThreadContext *tc) const 96110037SARM gem5 Developers{ 96210037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : 96310037SARM gem5 Developers (from64 ? EC_SMC_64 : vals.ec); 96410037SARM gem5 Developers} 96510037SARM gem5 Developers 9667362Sgblack@eecs.umich.edutemplate<class T> 9677362Sgblack@eecs.umich.eduvoid 96810417Sandreas.hansson@arm.comAbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst) 9697362Sgblack@eecs.umich.edu{ 97010037SARM gem5 Developers if (tranMethod == ArmFault::UnknownTran) { 97110037SARM gem5 Developers tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran 97210037SARM gem5 Developers : ArmFault::VmsaTran; 97310037SARM gem5 Developers 97410037SARM gem5 Developers if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) { 97510037SARM gem5 Developers // See ARM ARM B3-1416 97610037SARM gem5 Developers bool override_LPAE = false; 97710037SARM gem5 Developers TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S); 97810037SARM gem5 Developers TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS); 97910037SARM gem5 Developers if (ttbcr_s.eae) { 98010037SARM gem5 Developers override_LPAE = true; 98110037SARM gem5 Developers } else { 98210037SARM gem5 Developers // Unimplemented code option, not seen in testing. May need 98310037SARM gem5 Developers // extension according to the manual exceprt above. 98410037SARM gem5 Developers DPRINTF(Faults, "Warning: Incomplete translation method " 98510037SARM gem5 Developers "override detected.\n"); 98610037SARM gem5 Developers } 98710037SARM gem5 Developers if (override_LPAE) 98810037SARM gem5 Developers tranMethod = ArmFault::LpaeTran; 98910037SARM gem5 Developers } 99010037SARM gem5 Developers } 99110037SARM gem5 Developers 99210037SARM gem5 Developers if (source == ArmFault::AsynchronousExternalAbort) { 99311150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 99410037SARM gem5 Developers } 99510037SARM gem5 Developers // Get effective fault source encoding 99610037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 99710037SARM gem5 Developers FSR fsr = getFsr(tc); 99810037SARM gem5 Developers 99910037SARM gem5 Developers // source must be determined BEFORE invoking generic routines which will 100010037SARM gem5 Developers // try to set hsr etc. and are based upon source! 10018205SAli.Saidi@ARM.com ArmFaultVals<T>::invoke(tc, inst); 100210037SARM gem5 Developers 100311496Sandreas.sandberg@arm.com if (!this->to64) { // AArch32 100410037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 100510037SARM gem5 Developers tc->setMiscReg(T::HFarIndex, faultAddr); 100610037SARM gem5 Developers } else if (stage2) { 100710037SARM gem5 Developers tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf); 100810037SARM gem5 Developers tc->setMiscReg(T::HFarIndex, OVAddr); 100910037SARM gem5 Developers } else { 101010037SARM gem5 Developers tc->setMiscReg(T::FsrIndex, fsr); 101110037SARM gem5 Developers tc->setMiscReg(T::FarIndex, faultAddr); 101210037SARM gem5 Developers } 101310037SARM gem5 Developers DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\ 101410037SARM gem5 Developers "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod); 101510037SARM gem5 Developers } else { // AArch64 101610037SARM gem5 Developers // Set the FAR register. Nothing else to do if we are in AArch64 state 101710037SARM gem5 Developers // because the syndrome register has already been set inside invoke64() 101811585SDylan.Johnson@ARM.com if (stage2) { 101911585SDylan.Johnson@ARM.com // stage 2 fault, set HPFAR_EL2 to the faulting IPA 102011585SDylan.Johnson@ARM.com // and FAR_EL2 to the Original VA 102111585SDylan.Johnson@ARM.com tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr); 102211585SDylan.Johnson@ARM.com tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4); 102311585SDylan.Johnson@ARM.com 102411585SDylan.Johnson@ARM.com DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n", 102511585SDylan.Johnson@ARM.com OVAddr, faultAddr); 102611585SDylan.Johnson@ARM.com } else { 102711585SDylan.Johnson@ARM.com tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr); 102811585SDylan.Johnson@ARM.com } 102910037SARM gem5 Developers } 103010037SARM gem5 Developers} 103110037SARM gem5 Developers 103210037SARM gem5 Developerstemplate<class T> 103310037SARM gem5 DevelopersFSR 103410037SARM gem5 DevelopersAbortFault<T>::getFsr(ThreadContext *tc) 103510037SARM gem5 Developers{ 10367362Sgblack@eecs.umich.edu FSR fsr = 0; 10378314Sgeoffrey.blake@arm.com 103810037SARM gem5 Developers if (((CPSR) tc->readMiscRegNoEffect(MISCREG_CPSR)).width) { 103910037SARM gem5 Developers // AArch32 104010037SARM gem5 Developers assert(tranMethod != ArmFault::UnknownTran); 104110037SARM gem5 Developers if (tranMethod == ArmFault::LpaeTran) { 104210037SARM gem5 Developers srcEncoded = ArmFault::longDescFaultSources[source]; 104310037SARM gem5 Developers fsr.status = srcEncoded; 104410037SARM gem5 Developers fsr.lpae = 1; 104510037SARM gem5 Developers } else { 104610037SARM gem5 Developers srcEncoded = ArmFault::shortDescFaultSources[source]; 104710037SARM gem5 Developers fsr.fsLow = bits(srcEncoded, 3, 0); 104810037SARM gem5 Developers fsr.fsHigh = bits(srcEncoded, 4); 104910037SARM gem5 Developers fsr.domain = static_cast<uint8_t>(domain); 105010037SARM gem5 Developers } 105110037SARM gem5 Developers fsr.wnr = (write ? 1 : 0); 105210037SARM gem5 Developers fsr.ext = 0; 105310037SARM gem5 Developers } else { 105410037SARM gem5 Developers // AArch64 105510037SARM gem5 Developers srcEncoded = ArmFault::aarch64FaultSources[source]; 105610037SARM gem5 Developers } 105710037SARM gem5 Developers if (srcEncoded == ArmFault::FaultSourceInvalid) { 105810037SARM gem5 Developers panic("Invalid fault source\n"); 105910037SARM gem5 Developers } 106010037SARM gem5 Developers return fsr; 106110037SARM gem5 Developers} 106210037SARM gem5 Developers 106310037SARM gem5 Developerstemplate<class T> 106410037SARM gem5 Developersbool 106510037SARM gem5 DevelopersAbortFault<T>::abortDisable(ThreadContext *tc) 106610037SARM gem5 Developers{ 106710037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 106810037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 106910037SARM gem5 Developers return (!scr.ns || scr.aw); 107010037SARM gem5 Developers } 107110037SARM gem5 Developers return true; 107210037SARM gem5 Developers} 107310037SARM gem5 Developers 107410037SARM gem5 Developerstemplate<class T> 107510037SARM gem5 Developersvoid 107610037SARM gem5 DevelopersAbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val) 107710037SARM gem5 Developers{ 107810037SARM gem5 Developers switch (id) 107910037SARM gem5 Developers { 108010037SARM gem5 Developers case ArmFault::S1PTW: 108110037SARM gem5 Developers s1ptw = val; 108210037SARM gem5 Developers break; 108310037SARM gem5 Developers case ArmFault::OVA: 108410037SARM gem5 Developers OVAddr = val; 108510037SARM gem5 Developers break; 108610037SARM gem5 Developers 108710037SARM gem5 Developers // Just ignore unknown ID's 108810037SARM gem5 Developers default: 108910037SARM gem5 Developers break; 109010037SARM gem5 Developers } 109110037SARM gem5 Developers} 109210037SARM gem5 Developers 109310037SARM gem5 Developerstemplate<class T> 109410037SARM gem5 Developersuint32_t 109510037SARM gem5 DevelopersAbortFault<T>::iss() const 109610037SARM gem5 Developers{ 109710037SARM gem5 Developers uint32_t val; 109810037SARM gem5 Developers 109910037SARM gem5 Developers val = srcEncoded & 0x3F; 110010037SARM gem5 Developers val |= write << 6; 110110037SARM gem5 Developers val |= s1ptw << 7; 110210037SARM gem5 Developers return (val); 110310037SARM gem5 Developers} 110410037SARM gem5 Developers 110510037SARM gem5 Developerstemplate<class T> 110610037SARM gem5 Developersbool 110710037SARM gem5 DevelopersAbortFault<T>::isMMUFault() const 110810037SARM gem5 Developers{ 110910037SARM gem5 Developers // NOTE: Not relying on LL information being aligned to lowest bits here 111010037SARM gem5 Developers return 111110037SARM gem5 Developers (source == ArmFault::AlignmentFault) || 111210037SARM gem5 Developers ((source >= ArmFault::TranslationLL) && 111310037SARM gem5 Developers (source < ArmFault::TranslationLL + 4)) || 111410037SARM gem5 Developers ((source >= ArmFault::AccessFlagLL) && 111510037SARM gem5 Developers (source < ArmFault::AccessFlagLL + 4)) || 111610037SARM gem5 Developers ((source >= ArmFault::DomainLL) && 111710037SARM gem5 Developers (source < ArmFault::DomainLL + 4)) || 111810037SARM gem5 Developers ((source >= ArmFault::PermissionLL) && 111910037SARM gem5 Developers (source < ArmFault::PermissionLL + 4)); 112010037SARM gem5 Developers} 112110037SARM gem5 Developers 112210037SARM gem5 DevelopersExceptionClass 112310037SARM gem5 DevelopersPrefetchAbort::ec(ThreadContext *tc) const 112410037SARM gem5 Developers{ 112510037SARM gem5 Developers if (to64) { 112610037SARM gem5 Developers // AArch64 112710037SARM gem5 Developers if (toEL == fromEL) 112810037SARM gem5 Developers return EC_PREFETCH_ABORT_CURR_EL; 112910037SARM gem5 Developers else 113010037SARM gem5 Developers return EC_PREFETCH_ABORT_LOWER_EL; 113110037SARM gem5 Developers } else { 113210037SARM gem5 Developers // AArch32 113310037SARM gem5 Developers // Abort faults have different EC codes depending on whether 113410037SARM gem5 Developers // the fault originated within HYP mode, or not. So override 113510037SARM gem5 Developers // the method and add the extra adjustment of the EC value. 113610037SARM gem5 Developers 113710037SARM gem5 Developers ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec; 113810037SARM gem5 Developers 113910037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 114010037SARM gem5 Developers if (spsr.mode == MODE_HYP) { 114110037SARM gem5 Developers ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 114210037SARM gem5 Developers } 114310037SARM gem5 Developers return ec; 114410037SARM gem5 Developers } 114510037SARM gem5 Developers} 114610037SARM gem5 Developers 114710037SARM gem5 Developersbool 114810037SARM gem5 DevelopersPrefetchAbort::routeToMonitor(ThreadContext *tc) const 114910037SARM gem5 Developers{ 115010037SARM gem5 Developers SCR scr = 0; 115110037SARM gem5 Developers if (from64) 115210037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 115310037SARM gem5 Developers else 115410037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 115510037SARM gem5 Developers 115610037SARM gem5 Developers return scr.ea && !isMMUFault(); 115710037SARM gem5 Developers} 115810037SARM gem5 Developers 115910037SARM gem5 Developersbool 116010037SARM gem5 DevelopersPrefetchAbort::routeToHyp(ThreadContext *tc) const 116110037SARM gem5 Developers{ 116210037SARM gem5 Developers bool toHyp; 116310037SARM gem5 Developers 116410037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 116510037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 116610037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 116710037SARM gem5 Developers HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 116810037SARM gem5 Developers 116910037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 117010037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 117110037SARM gem5 Developers // otherwise, check whether to take to Hyp mode through Hyp Trap vector 117210037SARM gem5 Developers toHyp |= (stage2 || 117310037SARM gem5 Developers ( (source == DebugEvent) && hdcr.tde && (cpsr.mode != MODE_HYP)) || 117410037SARM gem5 Developers ( (source == SynchronousExternalAbort) && hcr.tge && (cpsr.mode == MODE_USER)) 117511581SDylan.Johnson@ARM.com ) && !inSecureState(tc); 117610037SARM gem5 Developers return toHyp; 117710037SARM gem5 Developers} 117810037SARM gem5 Developers 117910037SARM gem5 DevelopersExceptionClass 118010037SARM gem5 DevelopersDataAbort::ec(ThreadContext *tc) const 118110037SARM gem5 Developers{ 118210037SARM gem5 Developers if (to64) { 118310037SARM gem5 Developers // AArch64 118410037SARM gem5 Developers if (source == ArmFault::AsynchronousExternalAbort) { 118510367SAndrew.Bardsley@arm.com panic("Asynchronous External Abort should be handled with " 118610367SAndrew.Bardsley@arm.com "SystemErrors (SErrors)!"); 118710037SARM gem5 Developers } 118810037SARM gem5 Developers if (toEL == fromEL) 118910037SARM gem5 Developers return EC_DATA_ABORT_CURR_EL; 119010037SARM gem5 Developers else 119110037SARM gem5 Developers return EC_DATA_ABORT_LOWER_EL; 119210037SARM gem5 Developers } else { 119310037SARM gem5 Developers // AArch32 119410037SARM gem5 Developers // Abort faults have different EC codes depending on whether 119510037SARM gem5 Developers // the fault originated within HYP mode, or not. So override 119610037SARM gem5 Developers // the method and add the extra adjustment of the EC value. 119710037SARM gem5 Developers 119810037SARM gem5 Developers ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec; 119910037SARM gem5 Developers 120010037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 120110037SARM gem5 Developers if (spsr.mode == MODE_HYP) { 120210037SARM gem5 Developers ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 120310037SARM gem5 Developers } 120410037SARM gem5 Developers return ec; 120510037SARM gem5 Developers } 120610037SARM gem5 Developers} 120710037SARM gem5 Developers 120810037SARM gem5 Developersbool 120910037SARM gem5 DevelopersDataAbort::routeToMonitor(ThreadContext *tc) const 121010037SARM gem5 Developers{ 121110037SARM gem5 Developers SCR scr = 0; 121210037SARM gem5 Developers if (from64) 121310037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 121410037SARM gem5 Developers else 121510037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 121610037SARM gem5 Developers 121710037SARM gem5 Developers return scr.ea && !isMMUFault(); 121810037SARM gem5 Developers} 121910037SARM gem5 Developers 122010037SARM gem5 Developersbool 122110037SARM gem5 DevelopersDataAbort::routeToHyp(ThreadContext *tc) const 122210037SARM gem5 Developers{ 122310037SARM gem5 Developers bool toHyp; 122410037SARM gem5 Developers 122510037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 122610037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 122710037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 122810037SARM gem5 Developers HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 122910037SARM gem5 Developers 123010037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 123110037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 123210037SARM gem5 Developers // otherwise, check whether to take to Hyp mode through Hyp Trap vector 123310037SARM gem5 Developers toHyp |= (stage2 || 123410037SARM gem5 Developers ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) || 123510037SARM gem5 Developers ((source == DebugEvent) && hdcr.tde) ) 123610037SARM gem5 Developers ) || 123710037SARM gem5 Developers ( (cpsr.mode == MODE_USER) && hcr.tge && 123810037SARM gem5 Developers ((source == AlignmentFault) || 123910037SARM gem5 Developers (source == SynchronousExternalAbort)) 124010037SARM gem5 Developers ) 124111581SDylan.Johnson@ARM.com ) && !inSecureState(tc); 124210037SARM gem5 Developers return toHyp; 124310037SARM gem5 Developers} 124410037SARM gem5 Developers 124510037SARM gem5 Developersuint32_t 124610037SARM gem5 DevelopersDataAbort::iss() const 124710037SARM gem5 Developers{ 124810037SARM gem5 Developers uint32_t val; 124910037SARM gem5 Developers 125010037SARM gem5 Developers // Add on the data abort specific fields to the generic abort ISS value 125110037SARM gem5 Developers val = AbortFault<DataAbort>::iss(); 125210037SARM gem5 Developers // ISS is valid if not caused by a stage 1 page table walk, and when taken 125310037SARM gem5 Developers // to AArch64 only when directed to EL2 125410037SARM gem5 Developers if (!s1ptw && (!to64 || toEL == EL2)) { 125510037SARM gem5 Developers val |= isv << 24; 125610037SARM gem5 Developers if (isv) { 125710037SARM gem5 Developers val |= sas << 22; 125810037SARM gem5 Developers val |= sse << 21; 125910037SARM gem5 Developers val |= srt << 16; 126010037SARM gem5 Developers // AArch64 only. These assignments are safe on AArch32 as well 126110037SARM gem5 Developers // because these vars are initialized to false 126210037SARM gem5 Developers val |= sf << 15; 126310037SARM gem5 Developers val |= ar << 14; 126410037SARM gem5 Developers } 126510037SARM gem5 Developers } 126610037SARM gem5 Developers return (val); 126710037SARM gem5 Developers} 126810037SARM gem5 Developers 126910037SARM gem5 Developersvoid 127010037SARM gem5 DevelopersDataAbort::annotate(AnnotationIDs id, uint64_t val) 127110037SARM gem5 Developers{ 127210037SARM gem5 Developers AbortFault<DataAbort>::annotate(id, val); 127310037SARM gem5 Developers switch (id) 127410037SARM gem5 Developers { 127510037SARM gem5 Developers case SAS: 127610037SARM gem5 Developers isv = true; 127710037SARM gem5 Developers sas = val; 127810037SARM gem5 Developers break; 127910037SARM gem5 Developers case SSE: 128010037SARM gem5 Developers isv = true; 128110037SARM gem5 Developers sse = val; 128210037SARM gem5 Developers break; 128310037SARM gem5 Developers case SRT: 128410037SARM gem5 Developers isv = true; 128510037SARM gem5 Developers srt = val; 128610037SARM gem5 Developers break; 128710037SARM gem5 Developers case SF: 128810037SARM gem5 Developers isv = true; 128910037SARM gem5 Developers sf = val; 129010037SARM gem5 Developers break; 129110037SARM gem5 Developers case AR: 129210037SARM gem5 Developers isv = true; 129310037SARM gem5 Developers ar = val; 129410037SARM gem5 Developers break; 129510037SARM gem5 Developers // Just ignore unknown ID's 129610037SARM gem5 Developers default: 129710037SARM gem5 Developers break; 129810037SARM gem5 Developers } 129910037SARM gem5 Developers} 130010037SARM gem5 Developers 130110037SARM gem5 Developersvoid 130210417Sandreas.hansson@arm.comVirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst) 130310037SARM gem5 Developers{ 130410037SARM gem5 Developers AbortFault<VirtualDataAbort>::invoke(tc, inst); 130510037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 130610037SARM gem5 Developers hcr.va = 0; 130710037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_HCR, hcr); 130810037SARM gem5 Developers} 130910037SARM gem5 Developers 131010037SARM gem5 Developersbool 131110037SARM gem5 DevelopersInterrupt::routeToMonitor(ThreadContext *tc) const 131210037SARM gem5 Developers{ 131310037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 131410037SARM gem5 Developers SCR scr = 0; 131510037SARM gem5 Developers if (from64) 131610037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 131710037SARM gem5 Developers else 131810037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 131910037SARM gem5 Developers return scr.irq; 132010037SARM gem5 Developers} 132110037SARM gem5 Developers 132210037SARM gem5 Developersbool 132310037SARM gem5 DevelopersInterrupt::routeToHyp(ThreadContext *tc) const 132410037SARM gem5 Developers{ 132510037SARM gem5 Developers bool toHyp; 132610037SARM gem5 Developers 132710037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 132810037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 132910037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 133010037SARM gem5 Developers // Determine whether IRQs are routed to Hyp mode. 133111581SDylan.Johnson@ARM.com toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) || 133210037SARM gem5 Developers (cpsr.mode == MODE_HYP); 133310037SARM gem5 Developers return toHyp; 133410037SARM gem5 Developers} 133510037SARM gem5 Developers 133610037SARM gem5 Developersbool 133710037SARM gem5 DevelopersInterrupt::abortDisable(ThreadContext *tc) 133810037SARM gem5 Developers{ 133910037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 134010037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 134110037SARM gem5 Developers return (!scr.ns || scr.aw); 134210037SARM gem5 Developers } 134310037SARM gem5 Developers return true; 134410037SARM gem5 Developers} 134510037SARM gem5 Developers 134610037SARM gem5 DevelopersVirtualInterrupt::VirtualInterrupt() 134710037SARM gem5 Developers{} 134810037SARM gem5 Developers 134910037SARM gem5 Developersbool 135010037SARM gem5 DevelopersFastInterrupt::routeToMonitor(ThreadContext *tc) const 135110037SARM gem5 Developers{ 135210037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 135310037SARM gem5 Developers SCR scr = 0; 135410037SARM gem5 Developers if (from64) 135510037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 135610037SARM gem5 Developers else 135710037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 135810037SARM gem5 Developers return scr.fiq; 135910037SARM gem5 Developers} 136010037SARM gem5 Developers 136110037SARM gem5 Developersbool 136210037SARM gem5 DevelopersFastInterrupt::routeToHyp(ThreadContext *tc) const 136310037SARM gem5 Developers{ 136410037SARM gem5 Developers bool toHyp; 136510037SARM gem5 Developers 136610037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 136710037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 136810037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 136910037SARM gem5 Developers // Determine whether IRQs are routed to Hyp mode. 137011581SDylan.Johnson@ARM.com toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) || 137110037SARM gem5 Developers (cpsr.mode == MODE_HYP); 137210037SARM gem5 Developers return toHyp; 137310037SARM gem5 Developers} 137410037SARM gem5 Developers 137510037SARM gem5 Developersbool 137610037SARM gem5 DevelopersFastInterrupt::abortDisable(ThreadContext *tc) 137710037SARM gem5 Developers{ 137810037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 137910037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 138010037SARM gem5 Developers return (!scr.ns || scr.aw); 138110037SARM gem5 Developers } 138210037SARM gem5 Developers return true; 138310037SARM gem5 Developers} 138410037SARM gem5 Developers 138510037SARM gem5 Developersbool 138610037SARM gem5 DevelopersFastInterrupt::fiqDisable(ThreadContext *tc) 138710037SARM gem5 Developers{ 138810037SARM gem5 Developers if (ArmSystem::haveVirtualization(tc)) { 138910037SARM gem5 Developers return true; 139010037SARM gem5 Developers } else if (ArmSystem::haveSecurity(tc)) { 139110037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 139210037SARM gem5 Developers return (!scr.ns || scr.fw); 139310037SARM gem5 Developers } 139410037SARM gem5 Developers return true; 139510037SARM gem5 Developers} 139610037SARM gem5 Developers 139710037SARM gem5 DevelopersVirtualFastInterrupt::VirtualFastInterrupt() 139810037SARM gem5 Developers{} 139910037SARM gem5 Developers 140010037SARM gem5 Developersvoid 140110417Sandreas.hansson@arm.comPCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 140210037SARM gem5 Developers{ 140310037SARM gem5 Developers ArmFaultVals<PCAlignmentFault>::invoke(tc, inst); 140410037SARM gem5 Developers assert(from64); 140510037SARM gem5 Developers // Set the FAR 140610037SARM gem5 Developers tc->setMiscReg(getFaultAddrReg64(), faultPC); 140710037SARM gem5 Developers} 140810037SARM gem5 Developers 140910037SARM gem5 DevelopersSPAlignmentFault::SPAlignmentFault() 141010037SARM gem5 Developers{} 141110037SARM gem5 Developers 141210037SARM gem5 DevelopersSystemError::SystemError() 141310037SARM gem5 Developers{} 141410037SARM gem5 Developers 141510037SARM gem5 Developersvoid 141610417Sandreas.hansson@arm.comSystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst) 141710037SARM gem5 Developers{ 141811150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 141910037SARM gem5 Developers ArmFault::invoke(tc, inst); 142010037SARM gem5 Developers} 142110037SARM gem5 Developers 142210037SARM gem5 Developersbool 142310037SARM gem5 DevelopersSystemError::routeToMonitor(ThreadContext *tc) const 142410037SARM gem5 Developers{ 142510037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 142610037SARM gem5 Developers assert(from64); 142710037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 142810037SARM gem5 Developers return scr.ea; 142910037SARM gem5 Developers} 143010037SARM gem5 Developers 143110037SARM gem5 Developersbool 143210037SARM gem5 DevelopersSystemError::routeToHyp(ThreadContext *tc) const 143310037SARM gem5 Developers{ 143410037SARM gem5 Developers bool toHyp; 143510037SARM gem5 Developers assert(from64); 143610037SARM gem5 Developers 143710037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 143810037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 143910037SARM gem5 Developers 144011581SDylan.Johnson@ARM.com toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) || 144111581SDylan.Johnson@ARM.com (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc)); 144210037SARM gem5 Developers return toHyp; 14437362Sgblack@eecs.umich.edu} 14447362Sgblack@eecs.umich.edu 144512299Sandreas.sandberg@arm.com 144612299Sandreas.sandberg@arm.comSoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss) 144712299Sandreas.sandberg@arm.com : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss) 144812299Sandreas.sandberg@arm.com{} 144912299Sandreas.sandberg@arm.com 145012299Sandreas.sandberg@arm.combool 145112299Sandreas.sandberg@arm.comSoftwareBreakpoint::routeToHyp(ThreadContext *tc) const 145212299Sandreas.sandberg@arm.com{ 145312299Sandreas.sandberg@arm.com assert(from64); 145412299Sandreas.sandberg@arm.com 145512299Sandreas.sandberg@arm.com const bool have_el2 = ArmSystem::haveVirtualization(tc); 145612299Sandreas.sandberg@arm.com 145712299Sandreas.sandberg@arm.com const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 145812299Sandreas.sandberg@arm.com const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); 145912299Sandreas.sandberg@arm.com 146012299Sandreas.sandberg@arm.com return have_el2 && !inSecureState(tc) && fromEL <= EL1 && 146112299Sandreas.sandberg@arm.com (hcr.tge || mdcr.tde); 146212299Sandreas.sandberg@arm.com} 146312299Sandreas.sandberg@arm.com 14647652Sminkyu.jeong@arm.comvoid 146510417Sandreas.hansson@arm.comArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 14668518Sgeoffrey.blake@arm.com DPRINTF(Faults, "Invoking ArmSev Fault\n"); 14678806Sgblack@eecs.umich.edu if (!FullSystem) 14688806Sgblack@eecs.umich.edu return; 14698806Sgblack@eecs.umich.edu 14708806Sgblack@eecs.umich.edu // Set sev_mailbox to 1, clear the pending interrupt from remote 14718806Sgblack@eecs.umich.edu // SEV execution and let pipeline continue as pcState is still 14728806Sgblack@eecs.umich.edu // valid. 14738806Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 147411150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0); 14758518Sgeoffrey.blake@arm.com} 14768518Sgeoffrey.blake@arm.com 147710037SARM gem5 Developers// Instantiate all the templates to make the linker happy 147810037SARM gem5 Developerstemplate class ArmFaultVals<Reset>; 147910037SARM gem5 Developerstemplate class ArmFaultVals<UndefinedInstruction>; 148010037SARM gem5 Developerstemplate class ArmFaultVals<SupervisorCall>; 148110037SARM gem5 Developerstemplate class ArmFaultVals<SecureMonitorCall>; 148210037SARM gem5 Developerstemplate class ArmFaultVals<HypervisorCall>; 148310037SARM gem5 Developerstemplate class ArmFaultVals<PrefetchAbort>; 148410037SARM gem5 Developerstemplate class ArmFaultVals<DataAbort>; 148510037SARM gem5 Developerstemplate class ArmFaultVals<VirtualDataAbort>; 148610037SARM gem5 Developerstemplate class ArmFaultVals<HypervisorTrap>; 148710037SARM gem5 Developerstemplate class ArmFaultVals<Interrupt>; 148810037SARM gem5 Developerstemplate class ArmFaultVals<VirtualInterrupt>; 148910037SARM gem5 Developerstemplate class ArmFaultVals<FastInterrupt>; 149010037SARM gem5 Developerstemplate class ArmFaultVals<VirtualFastInterrupt>; 149110037SARM gem5 Developerstemplate class ArmFaultVals<SupervisorTrap>; 149210037SARM gem5 Developerstemplate class ArmFaultVals<SecureMonitorTrap>; 149310037SARM gem5 Developerstemplate class ArmFaultVals<PCAlignmentFault>; 149410037SARM gem5 Developerstemplate class ArmFaultVals<SPAlignmentFault>; 149510037SARM gem5 Developerstemplate class ArmFaultVals<SystemError>; 149612299Sandreas.sandberg@arm.comtemplate class ArmFaultVals<SoftwareBreakpoint>; 149710037SARM gem5 Developerstemplate class ArmFaultVals<ArmSev>; 149810037SARM gem5 Developerstemplate class AbortFault<PrefetchAbort>; 149910037SARM gem5 Developerstemplate class AbortFault<DataAbort>; 150010037SARM gem5 Developerstemplate class AbortFault<VirtualDataAbort>; 150110037SARM gem5 Developers 150210037SARM gem5 Developers 150310037SARM gem5 DevelopersIllegalInstSetStateFault::IllegalInstSetStateFault() 150410037SARM gem5 Developers{} 150510037SARM gem5 Developers 15066019Shines@cs.fsu.edu 15076019Shines@cs.fsu.edu} // namespace ArmISA 1508