ArmSystem.py revision 13396:23277eaae855
12810SN/A# Copyright (c) 2009, 2012-2013, 2015-2018 ARM Limited 210771Sstephan.diestelhorst@arm.com# All rights reserved. 310028SGiacomo.Gabrielli@arm.com# 410028SGiacomo.Gabrielli@arm.com# The license below extends only to copyright in the software and shall 510028SGiacomo.Gabrielli@arm.com# not be construed as granting a license to any other intellectual 610028SGiacomo.Gabrielli@arm.com# property including but not limited to intellectual property relating 710028SGiacomo.Gabrielli@arm.com# to a hardware implementation of the functionality of the software 810028SGiacomo.Gabrielli@arm.com# licensed hereunder. You may use the software subject to the license 910028SGiacomo.Gabrielli@arm.com# terms below provided that you ensure that this notice is replicated 1010028SGiacomo.Gabrielli@arm.com# unmodified and in its entirety in all distributions of the software, 1110028SGiacomo.Gabrielli@arm.com# modified or unmodified, in source code or in binary form. 1210028SGiacomo.Gabrielli@arm.com# 1310028SGiacomo.Gabrielli@arm.com# Redistribution and use in source and binary forms, with or without 142810SN/A# modification, are permitted provided that the following conditions are 152810SN/A# met: redistributions of source code must retain the above copyright 162810SN/A# notice, this list of conditions and the following disclaimer; 172810SN/A# redistributions in binary form must reproduce the above copyright 182810SN/A# notice, this list of conditions and the following disclaimer in the 192810SN/A# documentation and/or other materials provided with the distribution; 202810SN/A# neither the name of the copyright holders nor the names of its 212810SN/A# contributors may be used to endorse or promote products derived from 222810SN/A# this software without specific prior written permission. 232810SN/A# 242810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 252810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 262810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 272810SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 282810SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 292810SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 302810SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 312810SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 322810SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 332810SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 342810SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 352810SN/A# 362810SN/A# Authors: Ali Saidi 372810SN/A# Glenn Bergmans 382810SN/A 392810SN/Afrom m5.params import * 402810SN/Afrom m5.SimObject import * 412810SN/Afrom m5.util.fdthelper import * 422810SN/A 432810SN/Afrom System import System 442810SN/Afrom ArmSemihosting import ArmSemihosting 453861SN/A 462810SN/Aclass ArmMachineType(Enum): 472810SN/A map = { 4810623Smitch.hayenga@arm.com 'RealViewPBX' : 1901, 4910623Smitch.hayenga@arm.com 'VExpress_EMM' : 2272, 502810SN/A 'VExpress_EMM64' : 2272, 5112727Snikos.nikoleris@arm.com 'DTOnly' : -1, 5211168Sandreas.hansson@arm.com } 5313424Sodanrc@yahoo.com.br 5411168Sandreas.hansson@arm.comclass ArmSystem(System): 5512727Snikos.nikoleris@arm.com type = 'ArmSystem' 5610623Smitch.hayenga@arm.com cxx_header = "arch/arm/system.hh" 5712727Snikos.nikoleris@arm.com multi_proc = Param.Bool(True, "Multiprocessor system?") 5812727Snikos.nikoleris@arm.com boot_loader = VectorParam.String([], 5912727Snikos.nikoleris@arm.com "File that contains the boot loader code. Zero or more files may be " 602810SN/A "specified. The first boot loader that matches the kernel's " 6110623Smitch.hayenga@arm.com "architecture will be used.") 622810SN/A gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface") 632810SN/A flags_addr = Param.Addr(0, "Address of the flags register for MP booting") 6410623Smitch.hayenga@arm.com have_security = Param.Bool(False, 6510623Smitch.hayenga@arm.com "True if Security Extensions are implemented") 6610623Smitch.hayenga@arm.com have_virtualization = Param.Bool(False, 6710623Smitch.hayenga@arm.com "True if Virtualization Extensions are implemented") 685875Ssteve.reinhardt@amd.com have_crypto = Param.Bool(False, 6910623Smitch.hayenga@arm.com "True if Crypto Extensions is implemented") 7010623Smitch.hayenga@arm.com have_lpae = Param.Bool(True, "True if LPAE is implemented") 715875Ssteve.reinhardt@amd.com reset_addr = Param.Addr(0x0, 7210623Smitch.hayenga@arm.com "Reset address (ARMv8)") 7310623Smitch.hayenga@arm.com auto_reset_addr = Param.Bool(False, 7410623Smitch.hayenga@arm.com "Determine reset address from kernel entry point if no boot loader") 7510623Smitch.hayenga@arm.com highest_el_is_64 = Param.Bool(False, 7610623Smitch.hayenga@arm.com "True if the register width of the highest implemented exception level " 772810SN/A "is 64 bits (ARMv8)") 7813426Sodanrc@yahoo.com.br phys_addr_range_64 = Param.UInt8(40, 7913426Sodanrc@yahoo.com.br "Supported physical address range in bits when using AArch64 (ARMv8)") 8013426Sodanrc@yahoo.com.br have_large_asid_64 = Param.Bool(False, 8113426Sodanrc@yahoo.com.br "True if ASID is 16 bits in AArch64 (ARMv8)") 8213426Sodanrc@yahoo.com.br 8310623Smitch.hayenga@arm.com semihosting = Param.ArmSemihosting(NULL, 845875Ssteve.reinhardt@amd.com "Enable support for the Arm semihosting by settings this parameter") 8510623Smitch.hayenga@arm.com 8610028SGiacomo.Gabrielli@arm.com m5ops_base = Param.Addr(0, 872810SN/A "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 " 885875Ssteve.reinhardt@amd.com "to disable.") 895875Ssteve.reinhardt@amd.com 902810SN/A def generateDeviceTree(self, state): 9110771Sstephan.diestelhorst@arm.com # Generate a device tree root node for the system by creating the root 9210771Sstephan.diestelhorst@arm.com # node and adding the generated subnodes of all children. 9310771Sstephan.diestelhorst@arm.com # When a child needs to add multiple nodes, this is done by also 9413425Sodanrc@yahoo.com.br # creating a node called '/' which will then be merged with the 9513425Sodanrc@yahoo.com.br # root instead of appended. 9613425Sodanrc@yahoo.com.br 9713425Sodanrc@yahoo.com.br def generateMemNode(mem_range): 9813425Sodanrc@yahoo.com.br node = FdtNode("memory@%x" % long(mem_range.start)) 9913425Sodanrc@yahoo.com.br node.append(FdtPropertyStrings("device_type", ["memory"])) 10013425Sodanrc@yahoo.com.br node.append(FdtPropertyWords("reg", 10113425Sodanrc@yahoo.com.br state.addrCells(mem_range.start) + 10213424Sodanrc@yahoo.com.br state.sizeCells(mem_range.size()) )) 10313425Sodanrc@yahoo.com.br return node 10413425Sodanrc@yahoo.com.br 10513425Sodanrc@yahoo.com.br root = FdtNode('/') 10613425Sodanrc@yahoo.com.br root.append(state.addrCellsProperty()) 10710771Sstephan.diestelhorst@arm.com root.append(state.sizeCellsProperty()) 10813425Sodanrc@yahoo.com.br 10913425Sodanrc@yahoo.com.br # Add memory nodes 11013425Sodanrc@yahoo.com.br for mem_range in self.mem_ranges: 11113425Sodanrc@yahoo.com.br root.append(generateMemNode(mem_range)) 11213425Sodanrc@yahoo.com.br 11313425Sodanrc@yahoo.com.br for node in self.recurseDeviceTree(state): 11413425Sodanrc@yahoo.com.br # Merge root nodes instead of adding them (for children 11513425Sodanrc@yahoo.com.br # that need to add multiple root level nodes) 11610771Sstephan.diestelhorst@arm.com if node.get_name() == root.get_name(): 11713425Sodanrc@yahoo.com.br root.merge(node) 11813425Sodanrc@yahoo.com.br else: 11913425Sodanrc@yahoo.com.br root.append(node) 12013425Sodanrc@yahoo.com.br 12113425Sodanrc@yahoo.com.br return root 12213425Sodanrc@yahoo.com.br 12313425Sodanrc@yahoo.com.brclass GenericArmSystem(ArmSystem): 12413425Sodanrc@yahoo.com.br type = 'GenericArmSystem' 12510771Sstephan.diestelhorst@arm.com cxx_header = "arch/arm/system.hh" 12610771Sstephan.diestelhorst@arm.com machine_type = Param.ArmMachineType('DTOnly', 12710771Sstephan.diestelhorst@arm.com "Machine id from http://www.arm.linux.org.uk/developer/machines/") 12810771Sstephan.diestelhorst@arm.com atags_addr = Param.Addr("Address where default atags structure should " \ 12910771Sstephan.diestelhorst@arm.com "be written") 13013425Sodanrc@yahoo.com.br dtb_filename = Param.String("", 13110771Sstephan.diestelhorst@arm.com "File that contains the Device Tree Blob. Don't use DTB if empty.") 13213425Sodanrc@yahoo.com.br early_kernel_symbols = Param.Bool(False, 13313425Sodanrc@yahoo.com.br "enable early kernel symbol tables before MMU") 13413425Sodanrc@yahoo.com.br enable_context_switch_stats_dump = Param.Bool(False, "enable stats/task info dumping at context switch boundaries") 13513425Sodanrc@yahoo.com.br 13613425Sodanrc@yahoo.com.br panic_on_panic = Param.Bool(False, "Trigger a gem5 panic if the " \ 13713425Sodanrc@yahoo.com.br "guest kernel panics") 13813425Sodanrc@yahoo.com.br panic_on_oops = Param.Bool(False, "Trigger a gem5 panic if the " \ 13910771Sstephan.diestelhorst@arm.com "guest kernel oopses") 14013425Sodanrc@yahoo.com.br 1412810SN/Aclass LinuxArmSystem(GenericArmSystem): 14213423Sodanrc@yahoo.com.br type = 'LinuxArmSystem' 14313425Sodanrc@yahoo.com.br cxx_header = "arch/arm/linux/system.hh" 14413425Sodanrc@yahoo.com.br 14513423Sodanrc@yahoo.com.br @cxxMethod 14613425Sodanrc@yahoo.com.br def dumpDmesg(self): 14713425Sodanrc@yahoo.com.br """Dump dmesg from the simulated kernel to standard out""" 14813423Sodanrc@yahoo.com.br pass 14913425Sodanrc@yahoo.com.br 15013423Sodanrc@yahoo.com.br # Have Linux systems for ARM auto-calc their load_addr_mask for proper 15113425Sodanrc@yahoo.com.br # kernel relocation. 15213425Sodanrc@yahoo.com.br load_addr_mask = 0x0 15313425Sodanrc@yahoo.com.br 15413425Sodanrc@yahoo.com.brclass FreebsdArmSystem(GenericArmSystem): 15513425Sodanrc@yahoo.com.br type = 'FreebsdArmSystem' 15613425Sodanrc@yahoo.com.br cxx_header = "arch/arm/freebsd/system.hh" 15713425Sodanrc@yahoo.com.br