ArmSystem.py revision 13759
112525Sandreas.sandberg@arm.com# Copyright (c) 2009, 2012-2013, 2015-2018 ARM Limited 26757SAli.Saidi@ARM.com# All rights reserved. 36757SAli.Saidi@ARM.com# 47585SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57585SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67585SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77585SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87585SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97585SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107585SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117585SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127585SAli.Saidi@arm.com# 136757SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without 146757SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are 156757SAli.Saidi@ARM.com# met: redistributions of source code must retain the above copyright 166757SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer; 176757SAli.Saidi@ARM.com# redistributions in binary form must reproduce the above copyright 186757SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer in the 196757SAli.Saidi@ARM.com# documentation and/or other materials provided with the distribution; 206757SAli.Saidi@ARM.com# neither the name of the copyright holders nor the names of its 216757SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from 226757SAli.Saidi@ARM.com# this software without specific prior written permission. 236757SAli.Saidi@ARM.com# 246757SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 256757SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 266757SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 276757SAli.Saidi@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 286757SAli.Saidi@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 296757SAli.Saidi@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 306757SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 316757SAli.Saidi@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 326757SAli.Saidi@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 336757SAli.Saidi@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 346757SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 356757SAli.Saidi@ARM.com# 366757SAli.Saidi@ARM.com# Authors: Ali Saidi 3712469Sglenn.bergmans@arm.com# Glenn Bergmans 386757SAli.Saidi@ARM.com 396757SAli.Saidi@ARM.comfrom m5.params import * 4013608Sgiacomo.travaglini@arm.comfrom m5.options import * 4111988Sandreas.sandberg@arm.comfrom m5.SimObject import * 4212469Sglenn.bergmans@arm.comfrom m5.util.fdthelper import * 436757SAli.Saidi@ARM.com 4413665Sandreas.sandberg@arm.comfrom m5.objects.System import System 4513665Sandreas.sandberg@arm.comfrom m5.objects.ArmSemihosting import ArmSemihosting 466757SAli.Saidi@ARM.com 477585SAli.Saidi@arm.comclass ArmMachineType(Enum): 4811238Sandreas.sandberg@arm.com map = { 4911238Sandreas.sandberg@arm.com 'RealViewPBX' : 1901, 5011238Sandreas.sandberg@arm.com 'VExpress_EMM' : 2272, 5111238Sandreas.sandberg@arm.com 'VExpress_EMM64' : 2272, 5211238Sandreas.sandberg@arm.com 'DTOnly' : -1, 5311238Sandreas.sandberg@arm.com } 547585SAli.Saidi@arm.com 5513759Sgiacomo.gabrielli@arm.comclass SveVectorLength(UInt8): min = 1; max = 16 5613759Sgiacomo.gabrielli@arm.com 576757SAli.Saidi@ARM.comclass ArmSystem(System): 586757SAli.Saidi@ARM.com type = 'ArmSystem' 599338SAndreas.Sandberg@arm.com cxx_header = "arch/arm/system.hh" 609050Schander.sudanthi@arm.com multi_proc = Param.Bool(True, "Multiprocessor system?") 6111234Sandreas.sandberg@arm.com boot_loader = VectorParam.String([], 6211234Sandreas.sandberg@arm.com "File that contains the boot loader code. Zero or more files may be " 6311234Sandreas.sandberg@arm.com "specified. The first boot loader that matches the kernel's " 6411234Sandreas.sandberg@arm.com "architecture will be used.") 658286SAli.Saidi@ARM.com gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface") 668286SAli.Saidi@ARM.com flags_addr = Param.Addr(0, "Address of the flags register for MP booting") 6710037SARM gem5 Developers have_security = Param.Bool(False, 6810037SARM gem5 Developers "True if Security Extensions are implemented") 6910037SARM gem5 Developers have_virtualization = Param.Bool(False, 7010037SARM gem5 Developers "True if Virtualization Extensions are implemented") 7113173Sgiacomo.travaglini@arm.com have_crypto = Param.Bool(False, 7213173Sgiacomo.travaglini@arm.com "True if Crypto Extensions is implemented") 7311506Sandreas.sandberg@arm.com have_lpae = Param.Bool(True, "True if LPAE is implemented") 7413396Sgiacomo.travaglini@arm.com reset_addr = Param.Addr(0x0, 7513396Sgiacomo.travaglini@arm.com "Reset address (ARMv8)") 7613396Sgiacomo.travaglini@arm.com auto_reset_addr = Param.Bool(False, 7713396Sgiacomo.travaglini@arm.com "Determine reset address from kernel entry point if no boot loader") 7810037SARM gem5 Developers highest_el_is_64 = Param.Bool(False, 7910037SARM gem5 Developers "True if the register width of the highest implemented exception level " 8010037SARM gem5 Developers "is 64 bits (ARMv8)") 8110037SARM gem5 Developers phys_addr_range_64 = Param.UInt8(40, 8210037SARM gem5 Developers "Supported physical address range in bits when using AArch64 (ARMv8)") 8310037SARM gem5 Developers have_large_asid_64 = Param.Bool(False, 8410037SARM gem5 Developers "True if ASID is 16 bits in AArch64 (ARMv8)") 8513759Sgiacomo.gabrielli@arm.com have_sve = Param.Bool(True, 8613759Sgiacomo.gabrielli@arm.com "True if SVE is implemented (ARMv8)") 8713759Sgiacomo.gabrielli@arm.com sve_vl = Param.SveVectorLength(1, 8813759Sgiacomo.gabrielli@arm.com "SVE vector length in quadwords (128-bit)") 896757SAli.Saidi@ARM.com 9012531Sandreas.sandberg@arm.com semihosting = Param.ArmSemihosting(NULL, 9112531Sandreas.sandberg@arm.com "Enable support for the Arm semihosting by settings this parameter") 9212531Sandreas.sandberg@arm.com 9312005Sandreas.sandberg@arm.com m5ops_base = Param.Addr(0, 9412005Sandreas.sandberg@arm.com "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 " 9512005Sandreas.sandberg@arm.com "to disable.") 9612005Sandreas.sandberg@arm.com 9712469Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 9812469Sglenn.bergmans@arm.com # Generate a device tree root node for the system by creating the root 9912469Sglenn.bergmans@arm.com # node and adding the generated subnodes of all children. 10012469Sglenn.bergmans@arm.com # When a child needs to add multiple nodes, this is done by also 10112469Sglenn.bergmans@arm.com # creating a node called '/' which will then be merged with the 10212469Sglenn.bergmans@arm.com # root instead of appended. 10312469Sglenn.bergmans@arm.com 10412471Sglenn.bergmans@arm.com def generateMemNode(mem_range): 10512471Sglenn.bergmans@arm.com node = FdtNode("memory@%x" % long(mem_range.start)) 10612471Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("device_type", ["memory"])) 10712471Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", 10812471Sglenn.bergmans@arm.com state.addrCells(mem_range.start) + 10912471Sglenn.bergmans@arm.com state.sizeCells(mem_range.size()) )) 11012471Sglenn.bergmans@arm.com return node 11112471Sglenn.bergmans@arm.com 11212469Sglenn.bergmans@arm.com root = FdtNode('/') 11312469Sglenn.bergmans@arm.com root.append(state.addrCellsProperty()) 11412469Sglenn.bergmans@arm.com root.append(state.sizeCellsProperty()) 11512469Sglenn.bergmans@arm.com 11612471Sglenn.bergmans@arm.com # Add memory nodes 11712471Sglenn.bergmans@arm.com for mem_range in self.mem_ranges: 11812471Sglenn.bergmans@arm.com root.append(generateMemNode(mem_range)) 11912471Sglenn.bergmans@arm.com 12012469Sglenn.bergmans@arm.com for node in self.recurseDeviceTree(state): 12112469Sglenn.bergmans@arm.com # Merge root nodes instead of adding them (for children 12212469Sglenn.bergmans@arm.com # that need to add multiple root level nodes) 12312469Sglenn.bergmans@arm.com if node.get_name() == root.get_name(): 12412469Sglenn.bergmans@arm.com root.merge(node) 12512469Sglenn.bergmans@arm.com else: 12612469Sglenn.bergmans@arm.com root.append(node) 12712469Sglenn.bergmans@arm.com 12812469Sglenn.bergmans@arm.com return root 12912469Sglenn.bergmans@arm.com 13010810Sbr@bsdpad.comclass GenericArmSystem(ArmSystem): 13110810Sbr@bsdpad.com type = 'GenericArmSystem' 13210810Sbr@bsdpad.com cxx_header = "arch/arm/system.hh" 13312153Sandreas.sandberg@arm.com machine_type = Param.ArmMachineType('DTOnly', 1347585SAli.Saidi@arm.com "Machine id from http://www.arm.linux.org.uk/developer/machines/") 13510037SARM gem5 Developers atags_addr = Param.Addr("Address where default atags structure should " \ 13610037SARM gem5 Developers "be written") 1379261Sdam.sunwoo@arm.com dtb_filename = Param.String("", 1389261Sdam.sunwoo@arm.com "File that contains the Device Tree Blob. Don't use DTB if empty.") 1399261Sdam.sunwoo@arm.com early_kernel_symbols = Param.Bool(False, 1409261Sdam.sunwoo@arm.com "enable early kernel symbol tables before MMU") 1419332Sdam.sunwoo@arm.com enable_context_switch_stats_dump = Param.Bool(False, "enable stats/task info dumping at context switch boundaries") 1429649SAndreas.Sandberg@ARM.com 1439649SAndreas.Sandberg@ARM.com panic_on_panic = Param.Bool(False, "Trigger a gem5 panic if the " \ 1449649SAndreas.Sandberg@ARM.com "guest kernel panics") 1459649SAndreas.Sandberg@ARM.com panic_on_oops = Param.Bool(False, "Trigger a gem5 panic if the " \ 1469649SAndreas.Sandberg@ARM.com "guest kernel oopses") 14710810Sbr@bsdpad.com 14813608Sgiacomo.travaglini@arm.com def generateDtb(self, outdir, filename): 14913608Sgiacomo.travaglini@arm.com """ 15013608Sgiacomo.travaglini@arm.com Autogenerate DTB. Arguments are the folder where the DTB 15113608Sgiacomo.travaglini@arm.com will be stored, and the name of the DTB file. 15213608Sgiacomo.travaglini@arm.com """ 15313608Sgiacomo.travaglini@arm.com state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1) 15413608Sgiacomo.travaglini@arm.com rootNode = self.generateDeviceTree(state) 15513608Sgiacomo.travaglini@arm.com 15613608Sgiacomo.travaglini@arm.com fdt = Fdt() 15713608Sgiacomo.travaglini@arm.com fdt.add_rootnode(rootNode) 15813608Sgiacomo.travaglini@arm.com dtb_filename = os.path.join(outdir, filename) 15913608Sgiacomo.travaglini@arm.com self.dtb_filename = fdt.writeDtbFile(dtb_filename) 16013608Sgiacomo.travaglini@arm.com 16110810Sbr@bsdpad.comclass LinuxArmSystem(GenericArmSystem): 16210810Sbr@bsdpad.com type = 'LinuxArmSystem' 16310810Sbr@bsdpad.com cxx_header = "arch/arm/linux/system.hh" 16410810Sbr@bsdpad.com 16511988Sandreas.sandberg@arm.com @cxxMethod 16611988Sandreas.sandberg@arm.com def dumpDmesg(self): 16711988Sandreas.sandberg@arm.com """Dump dmesg from the simulated kernel to standard out""" 16811988Sandreas.sandberg@arm.com pass 16911538Sandreas.sandberg@arm.com 17012272SGeoffrey.Blake@arm.com # Have Linux systems for ARM auto-calc their load_addr_mask for proper 17112272SGeoffrey.Blake@arm.com # kernel relocation. 17212272SGeoffrey.Blake@arm.com load_addr_mask = 0x0 17312272SGeoffrey.Blake@arm.com 17410810Sbr@bsdpad.comclass FreebsdArmSystem(GenericArmSystem): 17510810Sbr@bsdpad.com type = 'FreebsdArmSystem' 17610810Sbr@bsdpad.com cxx_header = "arch/arm/freebsd/system.hh" 177