ArmSystem.py revision 12471
112272SGeoffrey.Blake@arm.com# Copyright (c) 2009, 2012-2013, 2015-2017 ARM Limited
26757SAli.Saidi@ARM.com# All rights reserved.
36757SAli.Saidi@ARM.com#
47585SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall
57585SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual
67585SAli.Saidi@arm.com# property including but not limited to intellectual property relating
77585SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software
87585SAli.Saidi@arm.com# licensed hereunder.  You may use the software subject to the license
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117585SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form.
127585SAli.Saidi@arm.com#
136757SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without
146757SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are
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166757SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer;
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226757SAli.Saidi@ARM.com# this software without specific prior written permission.
236757SAli.Saidi@ARM.com#
246757SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
256757SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
266757SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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346757SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
356757SAli.Saidi@ARM.com#
366757SAli.Saidi@ARM.com# Authors: Ali Saidi
3712469Sglenn.bergmans@arm.com#          Glenn Bergmans
386757SAli.Saidi@ARM.com
396757SAli.Saidi@ARM.comfrom m5.params import *
4011988Sandreas.sandberg@arm.comfrom m5.SimObject import *
4112469Sglenn.bergmans@arm.comfrom m5.util.fdthelper import *
426757SAli.Saidi@ARM.com
436757SAli.Saidi@ARM.comfrom System import System
446757SAli.Saidi@ARM.com
457585SAli.Saidi@arm.comclass ArmMachineType(Enum):
4611238Sandreas.sandberg@arm.com    map = {
4711238Sandreas.sandberg@arm.com        'RealViewEB' : 827,
4811238Sandreas.sandberg@arm.com        'RealViewPBX' : 1901,
4911238Sandreas.sandberg@arm.com        'VExpress_EMM' : 2272,
5011238Sandreas.sandberg@arm.com        'VExpress_EMM64' : 2272,
5111238Sandreas.sandberg@arm.com        'DTOnly' : -1,
5211238Sandreas.sandberg@arm.com    }
537585SAli.Saidi@arm.com
546757SAli.Saidi@ARM.comclass ArmSystem(System):
556757SAli.Saidi@ARM.com    type = 'ArmSystem'
569338SAndreas.Sandberg@arm.com    cxx_header = "arch/arm/system.hh"
579050Schander.sudanthi@arm.com    multi_proc = Param.Bool(True, "Multiprocessor system?")
5811234Sandreas.sandberg@arm.com    boot_loader = VectorParam.String([],
5911234Sandreas.sandberg@arm.com        "File that contains the boot loader code. Zero or more files may be "
6011234Sandreas.sandberg@arm.com        "specified. The first boot loader that matches the kernel's "
6111234Sandreas.sandberg@arm.com        "architecture will be used.")
628286SAli.Saidi@ARM.com    gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
638286SAli.Saidi@ARM.com    flags_addr = Param.Addr(0, "Address of the flags register for MP booting")
6410037SARM gem5 Developers    have_security = Param.Bool(False,
6510037SARM gem5 Developers        "True if Security Extensions are implemented")
6610037SARM gem5 Developers    have_virtualization = Param.Bool(False,
6710037SARM gem5 Developers        "True if Virtualization Extensions are implemented")
6811506Sandreas.sandberg@arm.com    have_lpae = Param.Bool(True, "True if LPAE is implemented")
6910037SARM gem5 Developers    highest_el_is_64 = Param.Bool(False,
7010037SARM gem5 Developers        "True if the register width of the highest implemented exception level "
7110037SARM gem5 Developers        "is 64 bits (ARMv8)")
7210317Smitch.hayenga@arm.com    reset_addr_64 = Param.Addr(0x0,
7310037SARM gem5 Developers        "Reset address if the highest implemented exception level is 64 bits "
7410037SARM gem5 Developers        "(ARMv8)")
7510037SARM gem5 Developers    phys_addr_range_64 = Param.UInt8(40,
7610037SARM gem5 Developers        "Supported physical address range in bits when using AArch64 (ARMv8)")
7710037SARM gem5 Developers    have_large_asid_64 = Param.Bool(False,
7810037SARM gem5 Developers        "True if ASID is 16 bits in AArch64 (ARMv8)")
796757SAli.Saidi@ARM.com
8012005Sandreas.sandberg@arm.com    m5ops_base = Param.Addr(0,
8112005Sandreas.sandberg@arm.com        "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 "
8212005Sandreas.sandberg@arm.com        "to disable.")
8312005Sandreas.sandberg@arm.com
8412469Sglenn.bergmans@arm.com    def generateDeviceTree(self, state):
8512469Sglenn.bergmans@arm.com        # Generate a device tree root node for the system by creating the root
8612469Sglenn.bergmans@arm.com        # node and adding the generated subnodes of all children.
8712469Sglenn.bergmans@arm.com        # When a child needs to add multiple nodes, this is done by also
8812469Sglenn.bergmans@arm.com        # creating a node called '/' which will then be merged with the
8912469Sglenn.bergmans@arm.com        # root instead of appended.
9012469Sglenn.bergmans@arm.com
9112471Sglenn.bergmans@arm.com        def generateMemNode(mem_range):
9212471Sglenn.bergmans@arm.com            node = FdtNode("memory@%x" % long(mem_range.start))
9312471Sglenn.bergmans@arm.com            node.append(FdtPropertyStrings("device_type", ["memory"]))
9412471Sglenn.bergmans@arm.com            node.append(FdtPropertyWords("reg",
9512471Sglenn.bergmans@arm.com                state.addrCells(mem_range.start) +
9612471Sglenn.bergmans@arm.com                state.sizeCells(mem_range.size()) ))
9712471Sglenn.bergmans@arm.com            return node
9812471Sglenn.bergmans@arm.com
9912469Sglenn.bergmans@arm.com        root = FdtNode('/')
10012469Sglenn.bergmans@arm.com        root.append(state.addrCellsProperty())
10112469Sglenn.bergmans@arm.com        root.append(state.sizeCellsProperty())
10212469Sglenn.bergmans@arm.com
10312471Sglenn.bergmans@arm.com        # Add memory nodes
10412471Sglenn.bergmans@arm.com        for mem_range in self.mem_ranges:
10512471Sglenn.bergmans@arm.com            root.append(generateMemNode(mem_range))
10612471Sglenn.bergmans@arm.com
10712469Sglenn.bergmans@arm.com        for node in self.recurseDeviceTree(state):
10812469Sglenn.bergmans@arm.com            # Merge root nodes instead of adding them (for children
10912469Sglenn.bergmans@arm.com            # that need to add multiple root level nodes)
11012469Sglenn.bergmans@arm.com            if node.get_name() == root.get_name():
11112469Sglenn.bergmans@arm.com                root.merge(node)
11212469Sglenn.bergmans@arm.com            else:
11312469Sglenn.bergmans@arm.com                root.append(node)
11412469Sglenn.bergmans@arm.com
11512469Sglenn.bergmans@arm.com        return root
11612469Sglenn.bergmans@arm.com
11710810Sbr@bsdpad.comclass GenericArmSystem(ArmSystem):
11810810Sbr@bsdpad.com    type = 'GenericArmSystem'
11910810Sbr@bsdpad.com    cxx_header = "arch/arm/system.hh"
12012153Sandreas.sandberg@arm.com    machine_type = Param.ArmMachineType('DTOnly',
1217585SAli.Saidi@arm.com        "Machine id from http://www.arm.linux.org.uk/developer/machines/")
12210037SARM gem5 Developers    atags_addr = Param.Addr("Address where default atags structure should " \
12310037SARM gem5 Developers                                "be written")
1249261Sdam.sunwoo@arm.com    dtb_filename = Param.String("",
1259261Sdam.sunwoo@arm.com        "File that contains the Device Tree Blob. Don't use DTB if empty.")
1269261Sdam.sunwoo@arm.com    early_kernel_symbols = Param.Bool(False,
1279261Sdam.sunwoo@arm.com        "enable early kernel symbol tables before MMU")
1289332Sdam.sunwoo@arm.com    enable_context_switch_stats_dump = Param.Bool(False, "enable stats/task info dumping at context switch boundaries")
1299649SAndreas.Sandberg@ARM.com
1309649SAndreas.Sandberg@ARM.com    panic_on_panic = Param.Bool(False, "Trigger a gem5 panic if the " \
1319649SAndreas.Sandberg@ARM.com                                    "guest kernel panics")
1329649SAndreas.Sandberg@ARM.com    panic_on_oops = Param.Bool(False, "Trigger a gem5 panic if the " \
1339649SAndreas.Sandberg@ARM.com                                   "guest kernel oopses")
13410810Sbr@bsdpad.com
13510810Sbr@bsdpad.comclass LinuxArmSystem(GenericArmSystem):
13610810Sbr@bsdpad.com    type = 'LinuxArmSystem'
13710810Sbr@bsdpad.com    cxx_header = "arch/arm/linux/system.hh"
13810810Sbr@bsdpad.com
13911988Sandreas.sandberg@arm.com    @cxxMethod
14011988Sandreas.sandberg@arm.com    def dumpDmesg(self):
14111988Sandreas.sandberg@arm.com        """Dump dmesg from the simulated kernel to standard out"""
14211988Sandreas.sandberg@arm.com        pass
14311538Sandreas.sandberg@arm.com
14412272SGeoffrey.Blake@arm.com    # Have Linux systems for ARM auto-calc their load_addr_mask for proper
14512272SGeoffrey.Blake@arm.com    # kernel relocation.
14612272SGeoffrey.Blake@arm.com    load_addr_mask = 0x0
14712272SGeoffrey.Blake@arm.com
14810810Sbr@bsdpad.comclass FreebsdArmSystem(GenericArmSystem):
14910810Sbr@bsdpad.com    type = 'FreebsdArmSystem'
15010810Sbr@bsdpad.com    cxx_header = "arch/arm/freebsd/system.hh"
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