utility.hh revision 8300
111527Sdavid.guillen@arm.com/* 211527Sdavid.guillen@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 311527Sdavid.guillen@arm.com * All rights reserved. 411527Sdavid.guillen@arm.com * 511527Sdavid.guillen@arm.com * Redistribution and use in source and binary forms, with or without 611527Sdavid.guillen@arm.com * modification, are permitted provided that the following conditions are 711527Sdavid.guillen@arm.com * met: redistributions of source code must retain the above copyright 811527Sdavid.guillen@arm.com * notice, this list of conditions and the following disclaimer; 911527Sdavid.guillen@arm.com * redistributions in binary form must reproduce the above copyright 1011527Sdavid.guillen@arm.com * notice, this list of conditions and the following disclaimer in the 1111527Sdavid.guillen@arm.com * documentation and/or other materials provided with the distribution; 1211527Sdavid.guillen@arm.com * neither the name of the copyright holders nor the names of its 1311527Sdavid.guillen@arm.com * contributors may be used to endorse or promote products derived from 1411527Sdavid.guillen@arm.com * this software without specific prior written permission. 1511527Sdavid.guillen@arm.com * 1611527Sdavid.guillen@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711527Sdavid.guillen@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811527Sdavid.guillen@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911527Sdavid.guillen@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011527Sdavid.guillen@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111527Sdavid.guillen@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211527Sdavid.guillen@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311527Sdavid.guillen@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411527Sdavid.guillen@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511527Sdavid.guillen@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611527Sdavid.guillen@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711527Sdavid.guillen@arm.com * 2811527Sdavid.guillen@arm.com * Authors: Nathan Binkert 2911527Sdavid.guillen@arm.com * Steve Reinhardt 3011527Sdavid.guillen@arm.com */ 3111527Sdavid.guillen@arm.com 3211527Sdavid.guillen@arm.com#ifndef __ARCH_ALPHA_UTILITY_HH__ 3311527Sdavid.guillen@arm.com#define __ARCH_ALPHA_UTILITY_HH__ 3411527Sdavid.guillen@arm.com 3511527Sdavid.guillen@arm.com#include "arch/alpha/isa_traits.hh" 3611527Sdavid.guillen@arm.com#include "arch/alpha/registers.hh" 3711527Sdavid.guillen@arm.com#include "arch/alpha/types.hh" 3811527Sdavid.guillen@arm.com#include "base/misc.hh" 3911527Sdavid.guillen@arm.com#include "config/full_system.hh" 4011527Sdavid.guillen@arm.com#include "cpu/static_inst.hh" 4111527Sdavid.guillen@arm.com#include "cpu/thread_context.hh" 4211527Sdavid.guillen@arm.com#include "arch/alpha/ev5.hh" 4311527Sdavid.guillen@arm.com 4411527Sdavid.guillen@arm.comnamespace AlphaISA { 4511527Sdavid.guillen@arm.com 4611527Sdavid.guillen@arm.cominline PCState 4711527Sdavid.guillen@arm.combuildRetPC(const PCState &curPC, const PCState &callPC) 4811527Sdavid.guillen@arm.com{ 4911527Sdavid.guillen@arm.com PCState retPC = callPC; 5011527Sdavid.guillen@arm.com retPC.advance(); 5111527Sdavid.guillen@arm.com return retPC; 5211527Sdavid.guillen@arm.com} 5311527Sdavid.guillen@arm.com 5411527Sdavid.guillen@arm.comuint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 5511527Sdavid.guillen@arm.com 56inline bool 57inUserMode(ThreadContext *tc) 58{ 59 return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; 60} 61 62/** 63 * Function to insure ISA semantics about 0 registers. 64 * @param tc The thread context. 65 */ 66template <class TC> 67void zeroRegisters(TC *tc); 68 69// Alpha IPR register accessors 70inline bool PcPAL(Addr addr) { return addr & 0x3; } 71inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } 72 73//////////////////////////////////////////////////////////////////////// 74// 75// Translation stuff 76// 77 78inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 79 80// User Virtual 81inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 82 83// Kernel Direct Mapped 84inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 85inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 86 87// Kernel Virtual 88inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 89 90inline Addr 91TruncPage(Addr addr) 92{ return addr & ~(PageBytes - 1); } 93 94inline Addr 95RoundPage(Addr addr) 96{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 97 98void initIPRs(ThreadContext *tc, int cpuId); 99#if FULL_SYSTEM 100void initCPU(ThreadContext *tc, int cpuId); 101#endif 102 103void copyRegs(ThreadContext *src, ThreadContext *dest); 104 105void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 106 107void skipFunction(ThreadContext *tc); 108 109inline void 110advancePC(PCState &pc, const StaticInstPtr inst) 111{ 112 pc.advance(); 113} 114 115inline uint64_t 116getExecutingAsid(ThreadContext *tc) 117{ 118 return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 119} 120 121} // namespace AlphaISA 122 123#endif // __ARCH_ALPHA_UTILITY_HH__ 124