utility.hh revision 8300
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 */ 31 32#ifndef __ARCH_ALPHA_UTILITY_HH__ 33#define __ARCH_ALPHA_UTILITY_HH__ 34 35#include "arch/alpha/isa_traits.hh" 36#include "arch/alpha/registers.hh" 37#include "arch/alpha/types.hh" 38#include "base/misc.hh" 39#include "config/full_system.hh" 40#include "cpu/static_inst.hh" 41#include "cpu/thread_context.hh" 42#include "arch/alpha/ev5.hh" 43 44namespace AlphaISA { 45 46inline PCState 47buildRetPC(const PCState &curPC, const PCState &callPC) 48{ 49 PCState retPC = callPC; 50 retPC.advance(); 51 return retPC; 52} 53 54uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 55 56inline bool 57inUserMode(ThreadContext *tc) 58{ 59 return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; 60} 61 62/** 63 * Function to insure ISA semantics about 0 registers. 64 * @param tc The thread context. 65 */ 66template <class TC> 67void zeroRegisters(TC *tc); 68 69// Alpha IPR register accessors 70inline bool PcPAL(Addr addr) { return addr & 0x3; } 71inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } 72 73//////////////////////////////////////////////////////////////////////// 74// 75// Translation stuff 76// 77 78inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 79 80// User Virtual 81inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 82 83// Kernel Direct Mapped 84inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 85inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 86 87// Kernel Virtual 88inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 89 90inline Addr 91TruncPage(Addr addr) 92{ return addr & ~(PageBytes - 1); } 93 94inline Addr 95RoundPage(Addr addr) 96{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 97 98void initIPRs(ThreadContext *tc, int cpuId); 99#if FULL_SYSTEM 100void initCPU(ThreadContext *tc, int cpuId); 101#endif 102 103void copyRegs(ThreadContext *src, ThreadContext *dest); 104 105void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 106 107void skipFunction(ThreadContext *tc); 108 109inline void 110advancePC(PCState &pc, const StaticInstPtr inst) 111{ 112 pc.advance(); 113} 114 115inline uint64_t 116getExecutingAsid(ThreadContext *tc) 117{ 118 return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 119} 120 121} // namespace AlphaISA 122 123#endif // __ARCH_ALPHA_UTILITY_HH__ 124