tlb.hh revision 4967 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 *          Steve Reinhardt
30 */
31
32#ifndef __ALPHA_MEMORY_HH__
33#define __ALPHA_MEMORY_HH__
34
35#include <map>
36
37#include "arch/alpha/ev5.hh"
38#include "arch/alpha/isa_traits.hh"
39#include "arch/alpha/pagetable.hh"
40#include "arch/alpha/utility.hh"
41#include "arch/alpha/vtophys.hh"
42#include "base/statistics.hh"
43#include "mem/request.hh"
44#include "sim/faults.hh"
45#include "sim/sim_object.hh"
46
47class ThreadContext;
48
49namespace AlphaISA
50{
51    class PTE;
52
53    class TLB : public SimObject
54    {
55      protected:
56        typedef std::multimap<Addr, int> PageTable;
57        PageTable lookupTable;	// Quick lookup into page table
58
59        PTE *table;	// the Page Table
60        int size;			// TLB Size
61        int nlu;			// not last used entry (for replacement)
62
63        void nextnlu() { if (++nlu >= size) nlu = 0; }
64        PTE *lookup(Addr vpn, uint8_t asn);
65
66      public:
67        TLB(const std::string &name, int size);
68        virtual ~TLB();
69
70        int getsize() const { return size; }
71
72        PTE &index(bool advance = true);
73        void insert(Addr vaddr, PTE &pte);
74
75        void flushAll();
76        void flushProcesses();
77        void flushAddr(Addr addr, uint8_t asn);
78
79        // static helper functions... really EV5 VM traits
80        static bool validVirtualAddress(Addr vaddr) {
81            // unimplemented bits must be all 0 or all 1
82            Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
83            return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
84        }
85
86        static Fault checkCacheability(RequestPtr &req);
87
88        // Checkpointing
89        virtual void serialize(std::ostream &os);
90        virtual void unserialize(Checkpoint *cp, const std::string &section);
91
92        // Most recently used page table entries
93        PTE *PTECache[3];
94        inline void flushCache() { memset(PTECache, 0, 3 * sizeof(PTE*)); }
95        inline PTE* updateCache(PTE *pte) {
96            PTECache[2] = PTECache[1];
97            PTECache[1] = PTECache[0];
98            PTECache[0] = pte;
99            return pte;
100        }
101    };
102
103    class ITB : public TLB
104    {
105      protected:
106        mutable Stats::Scalar<> hits;
107        mutable Stats::Scalar<> misses;
108        mutable Stats::Scalar<> acv;
109        mutable Stats::Formula accesses;
110
111      public:
112        ITB(const std::string &name, int size);
113        virtual void regStats();
114
115        Fault translate(RequestPtr &req, ThreadContext *tc);
116    };
117
118    class DTB : public TLB
119    {
120      protected:
121        mutable Stats::Scalar<> read_hits;
122        mutable Stats::Scalar<> read_misses;
123        mutable Stats::Scalar<> read_acv;
124        mutable Stats::Scalar<> read_accesses;
125        mutable Stats::Scalar<> write_hits;
126        mutable Stats::Scalar<> write_misses;
127        mutable Stats::Scalar<> write_acv;
128        mutable Stats::Scalar<> write_accesses;
129        Stats::Formula hits;
130        Stats::Formula misses;
131        Stats::Formula acv;
132        Stats::Formula accesses;
133
134      public:
135        DTB(const std::string &name, int size);
136        virtual void regStats();
137
138        Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
139    };
140}
141
142#endif // __ALPHA_MEMORY_HH__
143