tlb.hh revision 2984:797622d7b311 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 *          Steve Reinhardt
30 */
31
32#ifndef __ALPHA_MEMORY_HH__
33#define __ALPHA_MEMORY_HH__
34
35#include <map>
36
37#include "arch/alpha/ev5.hh"
38#include "arch/alpha/isa_traits.hh"
39#include "arch/alpha/utility.hh"
40#include "arch/alpha/vtophys.hh"
41#include "base/statistics.hh"
42#include "mem/request.hh"
43#include "sim/faults.hh"
44#include "sim/sim_object.hh"
45
46class ThreadContext;
47
48class AlphaTLB : public SimObject
49{
50  protected:
51    typedef std::multimap<Addr, int> PageTable;
52    PageTable lookupTable;	// Quick lookup into page table
53
54    AlphaISA::PTE *table;	// the Page Table
55    int size;			// TLB Size
56    int nlu;			// not last used entry (for replacement)
57
58    void nextnlu() { if (++nlu >= size) nlu = 0; }
59    AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
60
61  public:
62    AlphaTLB(const std::string &name, int size);
63    virtual ~AlphaTLB();
64
65    int getsize() const { return size; }
66
67    AlphaISA::PTE &index(bool advance = true);
68    void insert(Addr vaddr, AlphaISA::PTE &pte);
69
70    void flushAll();
71    void flushProcesses();
72    void flushAddr(Addr addr, uint8_t asn);
73
74    // static helper functions... really EV5 VM traits
75    static bool validVirtualAddress(Addr vaddr) {
76        // unimplemented bits must be all 0 or all 1
77        Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
78        return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
79    }
80
81    static Fault checkCacheability(RequestPtr &req);
82
83    // Checkpointing
84    virtual void serialize(std::ostream &os);
85    virtual void unserialize(Checkpoint *cp, const std::string &section);
86};
87
88class AlphaITB : public AlphaTLB
89{
90  protected:
91    mutable Stats::Scalar<> hits;
92    mutable Stats::Scalar<> misses;
93    mutable Stats::Scalar<> acv;
94    mutable Stats::Formula accesses;
95
96  public:
97    AlphaITB(const std::string &name, int size);
98    virtual void regStats();
99
100    Fault translate(RequestPtr &req, ThreadContext *tc) const;
101};
102
103class AlphaDTB : public AlphaTLB
104{
105  protected:
106    mutable Stats::Scalar<> read_hits;
107    mutable Stats::Scalar<> read_misses;
108    mutable Stats::Scalar<> read_acv;
109    mutable Stats::Scalar<> read_accesses;
110    mutable Stats::Scalar<> write_hits;
111    mutable Stats::Scalar<> write_misses;
112    mutable Stats::Scalar<> write_acv;
113    mutable Stats::Scalar<> write_accesses;
114    Stats::Formula hits;
115    Stats::Formula misses;
116    Stats::Formula acv;
117    Stats::Formula accesses;
118
119  public:
120    AlphaDTB(const std::string &name, int size);
121    virtual void regStats();
122
123    Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
124};
125
126#endif // __ALPHA_MEMORY_HH__
127