tlb.hh revision 10474:799c8ee4ecba
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 */ 31 32#ifndef __ARCH_ALPHA_TLB_HH__ 33#define __ARCH_ALPHA_TLB_HH__ 34 35#include <map> 36 37#include "arch/alpha/ev5.hh" 38#include "arch/alpha/isa_traits.hh" 39#include "arch/alpha/pagetable.hh" 40#include "arch/alpha/utility.hh" 41#include "arch/alpha/vtophys.hh" 42#include "base/statistics.hh" 43#include "mem/request.hh" 44#include "params/AlphaTLB.hh" 45#include "sim/tlb.hh" 46 47class ThreadContext; 48 49namespace AlphaISA { 50 51struct TlbEntry; 52 53class TLB : public BaseTLB 54{ 55 protected: 56 mutable Stats::Scalar fetch_hits; 57 mutable Stats::Scalar fetch_misses; 58 mutable Stats::Scalar fetch_acv; 59 mutable Stats::Formula fetch_accesses; 60 mutable Stats::Scalar read_hits; 61 mutable Stats::Scalar read_misses; 62 mutable Stats::Scalar read_acv; 63 mutable Stats::Scalar read_accesses; 64 mutable Stats::Scalar write_hits; 65 mutable Stats::Scalar write_misses; 66 mutable Stats::Scalar write_acv; 67 mutable Stats::Scalar write_accesses; 68 Stats::Formula data_hits; 69 Stats::Formula data_misses; 70 Stats::Formula data_acv; 71 Stats::Formula data_accesses; 72 73 74 typedef std::multimap<Addr, int> PageTable; 75 PageTable lookupTable; // Quick lookup into page table 76 77 TlbEntry *table; // the Page Table 78 int size; // TLB Size 79 int nlu; // not last used entry (for replacement) 80 81 void nextnlu() { if (++nlu >= size) nlu = 0; } 82 TlbEntry *lookup(Addr vpn, uint8_t asn); 83 84 public: 85 typedef AlphaTLBParams Params; 86 TLB(const Params *p); 87 virtual ~TLB(); 88 89 void takeOverFrom(BaseTLB *otlb) {} 90 91 virtual void regStats(); 92 93 int getsize() const { return size; } 94 95 TlbEntry &index(bool advance = true); 96 void insert(Addr vaddr, TlbEntry &entry); 97 98 void flushAll(); 99 void flushProcesses(); 100 void flushAddr(Addr addr, uint8_t asn); 101 102 void 103 demapPage(Addr vaddr, uint64_t asn) 104 { 105 assert(asn < (1 << 8)); 106 flushAddr(vaddr, asn); 107 } 108 109 // static helper functions... really EV5 VM traits 110 static bool 111 validVirtualAddress(Addr vaddr) 112 { 113 // unimplemented bits must be all 0 or all 1 114 Addr unimplBits = vaddr & VAddrUnImplMask; 115 return unimplBits == 0 || unimplBits == VAddrUnImplMask; 116 } 117 118 static Fault checkCacheability(RequestPtr &req, bool itb = false); 119 120 // Checkpointing 121 virtual void serialize(std::ostream &os); 122 virtual void unserialize(Checkpoint *cp, const std::string §ion); 123 124 // Most recently used page table entries 125 TlbEntry *EntryCache[3]; 126 inline void 127 flushCache() 128 { 129 memset(EntryCache, 0, 3 * sizeof(TlbEntry*)); 130 } 131 132 inline TlbEntry * 133 updateCache(TlbEntry *entry) { 134 EntryCache[2] = EntryCache[1]; 135 EntryCache[1] = EntryCache[0]; 136 EntryCache[0] = entry; 137 return entry; 138 } 139 140 protected: 141 Fault translateData(RequestPtr req, ThreadContext *tc, bool write); 142 Fault translateInst(RequestPtr req, ThreadContext *tc); 143 144 public: 145 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 146 void translateTiming(RequestPtr req, ThreadContext *tc, 147 Translation *translation, Mode mode); 148 /** 149 * translateFunctional stub function for future CheckerCPU support 150 */ 151 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); 152 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 153}; 154 155} // namespace AlphaISA 156 157#endif // __ARCH_ALPHA_TLB_HH__ 158