tlb.hh revision 1147
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2001-2004 The Regents of The University of Michigan 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 1510259SAndrew.Bardsley@arm.com * 1610259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710259SAndrew.Bardsley@arm.com */ 2810259SAndrew.Bardsley@arm.com 2910259SAndrew.Bardsley@arm.com#ifndef __ALPHA_MEMORY_HH__ 3010259SAndrew.Bardsley@arm.com#define __ALPHA_MEMORY_HH__ 3110259SAndrew.Bardsley@arm.com 3210259SAndrew.Bardsley@arm.com#include <map> 3310259SAndrew.Bardsley@arm.com 3410259SAndrew.Bardsley@arm.com#include "arch/alpha/isa_traits.hh" 3510259SAndrew.Bardsley@arm.com#include "base/statistics.hh" 3610259SAndrew.Bardsley@arm.com#include "mem/mem_req.hh" 3710259SAndrew.Bardsley@arm.com#include "sim/sim_object.hh" 3810259SAndrew.Bardsley@arm.com 3910259SAndrew.Bardsley@arm.comclass ExecContext; 4010259SAndrew.Bardsley@arm.com 4110259SAndrew.Bardsley@arm.comclass AlphaTLB : public SimObject 4210259SAndrew.Bardsley@arm.com{ 4310259SAndrew.Bardsley@arm.com protected: 4410259SAndrew.Bardsley@arm.com typedef std::multimap<Addr, int> PageTable; 4510259SAndrew.Bardsley@arm.com PageTable lookupTable; // Quick lookup into page table 4610259SAndrew.Bardsley@arm.com 4710259SAndrew.Bardsley@arm.com AlphaISA::PTE *table; // the Page Table 4810259SAndrew.Bardsley@arm.com int size; // TLB Size 4910259SAndrew.Bardsley@arm.com int nlu; // not last used entry (for replacement) 5010259SAndrew.Bardsley@arm.com 5110259SAndrew.Bardsley@arm.com void nextnlu() { if (++nlu >= size) nlu = 0; } 5210259SAndrew.Bardsley@arm.com AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const; 5310259SAndrew.Bardsley@arm.com 5410259SAndrew.Bardsley@arm.com public: 5510259SAndrew.Bardsley@arm.com AlphaTLB(const std::string &name, int size); 5610259SAndrew.Bardsley@arm.com virtual ~AlphaTLB(); 5710259SAndrew.Bardsley@arm.com 5810259SAndrew.Bardsley@arm.com int getsize() const { return size; } 5910259SAndrew.Bardsley@arm.com 6010259SAndrew.Bardsley@arm.com AlphaISA::PTE &index(bool advance = true); 6110259SAndrew.Bardsley@arm.com void insert(Addr vaddr, AlphaISA::PTE &pte); 6210259SAndrew.Bardsley@arm.com 6310259SAndrew.Bardsley@arm.com void flushAll(); 6410259SAndrew.Bardsley@arm.com void flushProcesses(); 6510259SAndrew.Bardsley@arm.com void flushAddr(Addr addr, uint8_t asn); 6610259SAndrew.Bardsley@arm.com 6710259SAndrew.Bardsley@arm.com // static helper functions... really EV5 VM traits 6810259SAndrew.Bardsley@arm.com static bool validVirtualAddress(Addr vaddr) { 6910259SAndrew.Bardsley@arm.com // unimplemented bits must be all 0 or all 1 7010259SAndrew.Bardsley@arm.com Addr unimplBits = vaddr & EV5::VAddrUnImplMask; 7110259SAndrew.Bardsley@arm.com return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask); 7210259SAndrew.Bardsley@arm.com } 7310259SAndrew.Bardsley@arm.com 7410259SAndrew.Bardsley@arm.com static void checkCacheability(MemReqPtr &req); 7510259SAndrew.Bardsley@arm.com 7610259SAndrew.Bardsley@arm.com // Checkpointing 7710259SAndrew.Bardsley@arm.com virtual void serialize(std::ostream &os); 7810259SAndrew.Bardsley@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 7910259SAndrew.Bardsley@arm.com}; 8010259SAndrew.Bardsley@arm.com 8110259SAndrew.Bardsley@arm.comclass AlphaITB : public AlphaTLB 8210259SAndrew.Bardsley@arm.com{ 8310259SAndrew.Bardsley@arm.com protected: 8410259SAndrew.Bardsley@arm.com mutable Stats::Scalar<> hits; 8510259SAndrew.Bardsley@arm.com mutable Stats::Scalar<> misses; 8610259SAndrew.Bardsley@arm.com mutable Stats::Scalar<> acv; 8710259SAndrew.Bardsley@arm.com mutable Stats::Formula accesses; 8810259SAndrew.Bardsley@arm.com 8910259SAndrew.Bardsley@arm.com protected: 9010259SAndrew.Bardsley@arm.com void fault(Addr pc, ExecContext *xc) const; 9110259SAndrew.Bardsley@arm.com 9210259SAndrew.Bardsley@arm.com public: 9310259SAndrew.Bardsley@arm.com AlphaITB(const std::string &name, int size); 9410259SAndrew.Bardsley@arm.com virtual void regStats(); 9510259SAndrew.Bardsley@arm.com 9610259SAndrew.Bardsley@arm.com Fault translate(MemReqPtr &req) const; 9710259SAndrew.Bardsley@arm.com}; 9810259SAndrew.Bardsley@arm.com 9910259SAndrew.Bardsley@arm.comclass AlphaDTB : public AlphaTLB 10010259SAndrew.Bardsley@arm.com{ 10110259SAndrew.Bardsley@arm.com protected: 10210259SAndrew.Bardsley@arm.com mutable Stats::Scalar<> read_hits; 10310259SAndrew.Bardsley@arm.com mutable Stats::Scalar<> read_misses; 10410259SAndrew.Bardsley@arm.com mutable Stats::Scalar<> read_acv; 10510259SAndrew.Bardsley@arm.com mutable Stats::Scalar<> read_accesses; 10610259SAndrew.Bardsley@arm.com mutable Stats::Scalar<> write_hits; 10710259SAndrew.Bardsley@arm.com mutable Stats::Scalar<> write_misses; 10810259SAndrew.Bardsley@arm.com mutable Stats::Scalar<> write_acv; 10910259SAndrew.Bardsley@arm.com mutable Stats::Scalar<> write_accesses; 11010259SAndrew.Bardsley@arm.com Stats::Formula hits; 11110259SAndrew.Bardsley@arm.com Stats::Formula misses; 11210259SAndrew.Bardsley@arm.com Stats::Formula acv; 11310259SAndrew.Bardsley@arm.com Stats::Formula accesses; 11410259SAndrew.Bardsley@arm.com 11510259SAndrew.Bardsley@arm.com protected: 11610259SAndrew.Bardsley@arm.com void fault(MemReqPtr &req, uint64_t flags) const; 11710259SAndrew.Bardsley@arm.com 11810259SAndrew.Bardsley@arm.com public: 11910259SAndrew.Bardsley@arm.com AlphaDTB(const std::string &name, int size); 12010259SAndrew.Bardsley@arm.com virtual void regStats(); 12110259SAndrew.Bardsley@arm.com 12210259SAndrew.Bardsley@arm.com Fault translate(MemReqPtr &req, bool write) const; 12310259SAndrew.Bardsley@arm.com}; 12410259SAndrew.Bardsley@arm.com 12510259SAndrew.Bardsley@arm.com#endif // __ALPHA_MEMORY_HH__ 12610259SAndrew.Bardsley@arm.com