process.cc revision 11800
12207SN/A/* 22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 32207SN/A * All rights reserved. 42207SN/A * 52207SN/A * Redistribution and use in source and binary forms, with or without 62207SN/A * modification, are permitted provided that the following conditions are 72207SN/A * met: redistributions of source code must retain the above copyright 82207SN/A * notice, this list of conditions and the following disclaimer; 92207SN/A * redistributions in binary form must reproduce the above copyright 102207SN/A * notice, this list of conditions and the following disclaimer in the 112207SN/A * documentation and/or other materials provided with the distribution; 122207SN/A * neither the name of the copyright holders nor the names of its 132207SN/A * contributors may be used to endorse or promote products derived from 142207SN/A * this software without specific prior written permission. 152207SN/A * 162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Ali Saidi 302207SN/A */ 312207SN/A 3211793Sbrandon.potter@amd.com#include "arch/alpha/process.hh" 3311793Sbrandon.potter@amd.com 342972Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 358229Snate@binkert.org#include "base/loader/elf_object.hh" 362454SN/A#include "base/loader/object_file.hh" 372454SN/A#include "base/misc.hh" 382680Sktlim@umich.edu#include "cpu/thread_context.hh" 398232Snate@binkert.org#include "debug/Loader.hh" 405759Shsul@eecs.umich.edu#include "mem/page_table.hh" 417678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 425759Shsul@eecs.umich.edu#include "sim/process_impl.hh" 4311800Sbrandon.potter@amd.com#include "sim/syscall_return.hh" 442474SN/A#include "sim/system.hh" 452207SN/A 462474SN/Ausing namespace AlphaISA; 472474SN/Ausing namespace std; 482474SN/A 495569Snate@binkert.orgAlphaLiveProcess::AlphaLiveProcess(LiveProcessParams *params, 505569Snate@binkert.org ObjectFile *objFile) 515154Sgblack@eecs.umich.edu : LiveProcess(params, objFile) 522474SN/A{ 532474SN/A brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 5410318Sandreas.hansson@arm.com brk_point = roundUp(brk_point, PageBytes); 552474SN/A 562474SN/A // Set up stack. On Alpha, stack goes below text section. This 572474SN/A // code should get moved to some architecture-specific spot. 582474SN/A stack_base = objFile->textBase() - (409600+4096); 592474SN/A 602474SN/A // Set up region for mmaps. Tru64 seems to start just above 0 and 612474SN/A // grow up from there. 6211386Ssteve.reinhardt@amd.com mmap_end = 0x10000; 632474SN/A 642474SN/A // Set pointer for next thread stack. Reserve 8M for main stack. 652474SN/A next_thread_stack_base = stack_base - (8 * 1024 * 1024); 662474SN/A 672474SN/A} 682474SN/A 692474SN/Avoid 705759Shsul@eecs.umich.eduAlphaLiveProcess::argsInit(int intSize, int pageSize) 715759Shsul@eecs.umich.edu{ 7211389Sbrandon.potter@amd.com // Patch the ld_bias for dynamic executables. 7311389Sbrandon.potter@amd.com updateBias(); 7411389Sbrandon.potter@amd.com 755759Shsul@eecs.umich.edu objFile->loadSections(initVirtMem); 765759Shsul@eecs.umich.edu 775771Shsul@eecs.umich.edu typedef AuxVector<uint64_t> auxv_t; 785759Shsul@eecs.umich.edu std::vector<auxv_t> auxv; 795759Shsul@eecs.umich.edu 805759Shsul@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 8111321Ssteve.reinhardt@amd.com if (elfObject) 825759Shsul@eecs.umich.edu { 8311320Ssteve.reinhardt@amd.com // modern glibc uses a bunch of auxiliary vectors to set up 845759Shsul@eecs.umich.edu // TLS as well as do a bunch of other stuff 855759Shsul@eecs.umich.edu // these vectors go on the bottom of the stack, below argc/argv/envp 865759Shsul@eecs.umich.edu // pointers but above actual arg strings 875759Shsul@eecs.umich.edu // I don't have all the ones glibc looks at here, but so far it doesn't 885759Shsul@eecs.umich.edu // seem to be a problem. 895759Shsul@eecs.umich.edu // check out _dl_aux_init() in glibc/elf/dl-support.c for details 905759Shsul@eecs.umich.edu // --Lisa 9110318Sandreas.hansson@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes)); 925759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 935759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 945759Shsul@eecs.umich.edu DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable()); 955759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 9611389Sbrandon.potter@amd.com // This is the base address of the ELF interpreter; it should be 9711389Sbrandon.potter@amd.com // zero for static executables or contain the base address for 9811389Sbrandon.potter@amd.com // dynamic executables. 9911389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 1005759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 1015759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 1025759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 1035759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 1045759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 1055759Shsul@eecs.umich.edu 1065759Shsul@eecs.umich.edu } 1075759Shsul@eecs.umich.edu 1085759Shsul@eecs.umich.edu // Calculate how much space we need for arg & env & auxv arrays. 1095759Shsul@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 1105759Shsul@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 1115759Shsul@eecs.umich.edu int auxv_array_size = intSize * 2 * (auxv.size() + 1); 1125759Shsul@eecs.umich.edu 1135759Shsul@eecs.umich.edu int arg_data_size = 0; 1146227Snate@binkert.org for (vector<string>::size_type i = 0; i < argv.size(); ++i) { 1155759Shsul@eecs.umich.edu arg_data_size += argv[i].size() + 1; 1165759Shsul@eecs.umich.edu } 1175759Shsul@eecs.umich.edu int env_data_size = 0; 1186227Snate@binkert.org for (vector<string>::size_type i = 0; i < envp.size(); ++i) { 1195759Shsul@eecs.umich.edu env_data_size += envp[i].size() + 1; 1205759Shsul@eecs.umich.edu } 1215759Shsul@eecs.umich.edu 1225759Shsul@eecs.umich.edu int space_needed = 12311320Ssteve.reinhardt@amd.com argv_array_size + 12411320Ssteve.reinhardt@amd.com envp_array_size + 1255759Shsul@eecs.umich.edu auxv_array_size + 12611320Ssteve.reinhardt@amd.com arg_data_size + 1275759Shsul@eecs.umich.edu env_data_size; 1285759Shsul@eecs.umich.edu 1295759Shsul@eecs.umich.edu if (space_needed < 32*1024) 1305759Shsul@eecs.umich.edu space_needed = 32*1024; 1315759Shsul@eecs.umich.edu 1325759Shsul@eecs.umich.edu // set bottom of stack 1335759Shsul@eecs.umich.edu stack_min = stack_base - space_needed; 1345759Shsul@eecs.umich.edu // align it 1355759Shsul@eecs.umich.edu stack_min = roundDown(stack_min, pageSize); 1365759Shsul@eecs.umich.edu stack_size = stack_base - stack_min; 1375759Shsul@eecs.umich.edu // map memory 1388601Ssteve.reinhardt@amd.com allocateMem(stack_min, roundUp(stack_size, pageSize)); 1395759Shsul@eecs.umich.edu 1405759Shsul@eecs.umich.edu // map out initial stack contents 1415759Shsul@eecs.umich.edu Addr argv_array_base = stack_min + intSize; // room for argc 1425759Shsul@eecs.umich.edu Addr envp_array_base = argv_array_base + argv_array_size; 1435759Shsul@eecs.umich.edu Addr auxv_array_base = envp_array_base + envp_array_size; 1445759Shsul@eecs.umich.edu Addr arg_data_base = auxv_array_base + auxv_array_size; 1455759Shsul@eecs.umich.edu Addr env_data_base = arg_data_base + arg_data_size; 1465759Shsul@eecs.umich.edu 1475759Shsul@eecs.umich.edu // write contents to stack 1485759Shsul@eecs.umich.edu uint64_t argc = argv.size(); 1495759Shsul@eecs.umich.edu if (intSize == 8) 1505759Shsul@eecs.umich.edu argc = htog((uint64_t)argc); 1515759Shsul@eecs.umich.edu else if (intSize == 4) 1525759Shsul@eecs.umich.edu argc = htog((uint32_t)argc); 1535759Shsul@eecs.umich.edu else 1545759Shsul@eecs.umich.edu panic("Unknown int size"); 1555759Shsul@eecs.umich.edu 1568852Sandreas.hansson@arm.com initVirtMem.writeBlob(stack_min, (uint8_t*)&argc, intSize); 1575759Shsul@eecs.umich.edu 1585759Shsul@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 1595759Shsul@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 1605759Shsul@eecs.umich.edu 1615759Shsul@eecs.umich.edu //Copy the aux stuff 1626227Snate@binkert.org for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) { 1638852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 1645759Shsul@eecs.umich.edu (uint8_t*)&(auxv[x].a_type), intSize); 1658852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 1665759Shsul@eecs.umich.edu (uint8_t*)&(auxv[x].a_val), intSize); 1675759Shsul@eecs.umich.edu } 1685759Shsul@eecs.umich.edu 1695759Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1705759Shsul@eecs.umich.edu 1715958Sgblack@eecs.umich.edu setSyscallArg(tc, 0, argc); 1725958Sgblack@eecs.umich.edu setSyscallArg(tc, 1, argv_array_base); 1735759Shsul@eecs.umich.edu tc->setIntReg(StackPointerReg, stack_min); 1745759Shsul@eecs.umich.edu 17511389Sbrandon.potter@amd.com tc->pcState(getStartPC()); 1765759Shsul@eecs.umich.edu} 1775759Shsul@eecs.umich.edu 1785759Shsul@eecs.umich.eduvoid 1797532Ssteve.reinhardt@amd.comAlphaLiveProcess::setupASNReg() 1802474SN/A{ 1816820SLisa.Hsu@amd.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 1826820SLisa.Hsu@amd.com tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57); 1837532Ssteve.reinhardt@amd.com} 1846820SLisa.Hsu@amd.com 1855183Ssaidi@eecs.umich.edu 1867532Ssteve.reinhardt@amd.comvoid 18710905Sandreas.sandberg@arm.comAlphaLiveProcess::loadState(CheckpointIn &cp) 1887532Ssteve.reinhardt@amd.com{ 1897532Ssteve.reinhardt@amd.com LiveProcess::loadState(cp); 1907532Ssteve.reinhardt@amd.com // need to set up ASN after unserialization since M5_pid value may 1917532Ssteve.reinhardt@amd.com // come from checkpoint 1927532Ssteve.reinhardt@amd.com setupASNReg(); 1937532Ssteve.reinhardt@amd.com} 1947532Ssteve.reinhardt@amd.com 1957532Ssteve.reinhardt@amd.com 1967532Ssteve.reinhardt@amd.comvoid 1977532Ssteve.reinhardt@amd.comAlphaLiveProcess::initState() 1987532Ssteve.reinhardt@amd.com{ 1997532Ssteve.reinhardt@amd.com // need to set up ASN before further initialization since init 2007532Ssteve.reinhardt@amd.com // will involve writing to virtual memory addresses 2017532Ssteve.reinhardt@amd.com setupASNReg(); 2027532Ssteve.reinhardt@amd.com 2037532Ssteve.reinhardt@amd.com LiveProcess::initState(); 2045759Shsul@eecs.umich.edu 20510318Sandreas.hansson@arm.com argsInit(MachineBytes, PageBytes); 2062474SN/A 2077532Ssteve.reinhardt@amd.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 2085713Shsul@eecs.umich.edu tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); 2095713Shsul@eecs.umich.edu //Operate in user mode 2107701Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3); 2117701Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3); 2124997Sgblack@eecs.umich.edu //No super page mapping 2135713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(IPR_MCSR, 0); 2142474SN/A} 2152474SN/A 2165958Sgblack@eecs.umich.eduAlphaISA::IntReg 2176701Sgblack@eecs.umich.eduAlphaLiveProcess::getSyscallArg(ThreadContext *tc, int &i) 2185958Sgblack@eecs.umich.edu{ 2195958Sgblack@eecs.umich.edu assert(i < 6); 2206701Sgblack@eecs.umich.edu return tc->readIntReg(FirstArgumentReg + i++); 2215958Sgblack@eecs.umich.edu} 2225958Sgblack@eecs.umich.edu 2235958Sgblack@eecs.umich.eduvoid 2245958Sgblack@eecs.umich.eduAlphaLiveProcess::setSyscallArg(ThreadContext *tc, 2255958Sgblack@eecs.umich.edu int i, AlphaISA::IntReg val) 2265958Sgblack@eecs.umich.edu{ 2275958Sgblack@eecs.umich.edu assert(i < 6); 2285958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, val); 2295958Sgblack@eecs.umich.edu} 2305958Sgblack@eecs.umich.edu 2315958Sgblack@eecs.umich.eduvoid 23210223Ssteve.reinhardt@amd.comAlphaLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 2335958Sgblack@eecs.umich.edu{ 2345958Sgblack@eecs.umich.edu // check for error condition. Alpha syscall convention is to 2355958Sgblack@eecs.umich.edu // indicate success/failure in reg a3 (r19) and put the 2365958Sgblack@eecs.umich.edu // return value itself in the standard return value reg (v0). 23710223Ssteve.reinhardt@amd.com if (sysret.successful()) { 2385958Sgblack@eecs.umich.edu // no error 2395958Sgblack@eecs.umich.edu tc->setIntReg(SyscallSuccessReg, 0); 24010223Ssteve.reinhardt@amd.com tc->setIntReg(ReturnValueReg, sysret.returnValue()); 2415958Sgblack@eecs.umich.edu } else { 2425958Sgblack@eecs.umich.edu // got an error, return details 2435958Sgblack@eecs.umich.edu tc->setIntReg(SyscallSuccessReg, (IntReg)-1); 24410223Ssteve.reinhardt@amd.com tc->setIntReg(ReturnValueReg, sysret.errnoValue()); 2455958Sgblack@eecs.umich.edu } 2465958Sgblack@eecs.umich.edu} 247