process.cc revision 11800
16166Ssteve.reinhardt@amd.com/* 26166Ssteve.reinhardt@amd.com * Copyright (c) 2003-2004 The Regents of The University of Michigan 36166Ssteve.reinhardt@amd.com * All rights reserved. 46166Ssteve.reinhardt@amd.com * 56166Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 66166Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 76166Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 86166Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 96166Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 106166Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 116166Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 126166Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 136166Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 146166Ssteve.reinhardt@amd.com * this software without specific prior written permission. 156166Ssteve.reinhardt@amd.com * 166166Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176166Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186166Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196166Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206166Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216166Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226166Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236166Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246166Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256166Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266166Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276166Ssteve.reinhardt@amd.com * 286166Ssteve.reinhardt@amd.com * Authors: Gabe Black 296166Ssteve.reinhardt@amd.com * Ali Saidi 306166Ssteve.reinhardt@amd.com */ 316654Snate@binkert.org 329113SBrad.Beckmann@amd.com#include "arch/alpha/process.hh" 336166Ssteve.reinhardt@amd.com 346166Ssteve.reinhardt@amd.com#include "arch/alpha/isa_traits.hh" 356166Ssteve.reinhardt@amd.com#include "base/loader/elf_object.hh" 366166Ssteve.reinhardt@amd.com#include "base/loader/object_file.hh" 376289Snate@binkert.org#include "base/misc.hh" 386870Sdrh5@cs.wisc.edu#include "cpu/thread_context.hh" 396289Snate@binkert.org#include "debug/Loader.hh" 406166Ssteve.reinhardt@amd.com#include "mem/page_table.hh" 4110720Sandreas.hansson@arm.com#include "sim/byteswap.hh" 429793Sakash.bagdia@arm.com#include "sim/process_impl.hh" 439793Sakash.bagdia@arm.com#include "sim/syscall_return.hh" 449793Sakash.bagdia@arm.com#include "sim/system.hh" 459793Sakash.bagdia@arm.com 469793Sakash.bagdia@arm.comusing namespace AlphaISA; 479793Sakash.bagdia@arm.comusing namespace std; 486166Ssteve.reinhardt@amd.com 496166Ssteve.reinhardt@amd.comAlphaLiveProcess::AlphaLiveProcess(LiveProcessParams *params, 508876Sandreas.hansson@arm.com ObjectFile *objFile) 518876Sandreas.hansson@arm.com : LiveProcess(params, objFile) 527876Sgblack@eecs.umich.edu{ 539793Sakash.bagdia@arm.com brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 549793Sakash.bagdia@arm.com brk_point = roundUp(brk_point, PageBytes); 556166Ssteve.reinhardt@amd.com 566166Ssteve.reinhardt@amd.com // Set up stack. On Alpha, stack goes below text section. This 578839Sandreas.hansson@arm.com // code should get moved to some architecture-specific spot. 586166Ssteve.reinhardt@amd.com stack_base = objFile->textBase() - (409600+4096); 598732Sandreas.hansson@arm.com 608839Sandreas.hansson@arm.com // Set up region for mmaps. Tru64 seems to start just above 0 and 616166Ssteve.reinhardt@amd.com // grow up from there. 626166Ssteve.reinhardt@amd.com mmap_end = 0x10000; 636166Ssteve.reinhardt@amd.com 646166Ssteve.reinhardt@amd.com // Set pointer for next thread stack. Reserve 8M for main stack. 656166Ssteve.reinhardt@amd.com next_thread_stack_base = stack_base - (8 * 1024 * 1024); 668801Sgblack@eecs.umich.edu 676166Ssteve.reinhardt@amd.com} 68 69void 70AlphaLiveProcess::argsInit(int intSize, int pageSize) 71{ 72 // Patch the ld_bias for dynamic executables. 73 updateBias(); 74 75 objFile->loadSections(initVirtMem); 76 77 typedef AuxVector<uint64_t> auxv_t; 78 std::vector<auxv_t> auxv; 79 80 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 81 if (elfObject) 82 { 83 // modern glibc uses a bunch of auxiliary vectors to set up 84 // TLS as well as do a bunch of other stuff 85 // these vectors go on the bottom of the stack, below argc/argv/envp 86 // pointers but above actual arg strings 87 // I don't have all the ones glibc looks at here, but so far it doesn't 88 // seem to be a problem. 89 // check out _dl_aux_init() in glibc/elf/dl-support.c for details 90 // --Lisa 91 auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes)); 92 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 93 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 94 DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable()); 95 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 96 // This is the base address of the ELF interpreter; it should be 97 // zero for static executables or contain the base address for 98 // dynamic executables. 99 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 100 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 101 auxv.push_back(auxv_t(M5_AT_UID, uid())); 102 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 103 auxv.push_back(auxv_t(M5_AT_GID, gid())); 104 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 105 106 } 107 108 // Calculate how much space we need for arg & env & auxv arrays. 109 int argv_array_size = intSize * (argv.size() + 1); 110 int envp_array_size = intSize * (envp.size() + 1); 111 int auxv_array_size = intSize * 2 * (auxv.size() + 1); 112 113 int arg_data_size = 0; 114 for (vector<string>::size_type i = 0; i < argv.size(); ++i) { 115 arg_data_size += argv[i].size() + 1; 116 } 117 int env_data_size = 0; 118 for (vector<string>::size_type i = 0; i < envp.size(); ++i) { 119 env_data_size += envp[i].size() + 1; 120 } 121 122 int space_needed = 123 argv_array_size + 124 envp_array_size + 125 auxv_array_size + 126 arg_data_size + 127 env_data_size; 128 129 if (space_needed < 32*1024) 130 space_needed = 32*1024; 131 132 // set bottom of stack 133 stack_min = stack_base - space_needed; 134 // align it 135 stack_min = roundDown(stack_min, pageSize); 136 stack_size = stack_base - stack_min; 137 // map memory 138 allocateMem(stack_min, roundUp(stack_size, pageSize)); 139 140 // map out initial stack contents 141 Addr argv_array_base = stack_min + intSize; // room for argc 142 Addr envp_array_base = argv_array_base + argv_array_size; 143 Addr auxv_array_base = envp_array_base + envp_array_size; 144 Addr arg_data_base = auxv_array_base + auxv_array_size; 145 Addr env_data_base = arg_data_base + arg_data_size; 146 147 // write contents to stack 148 uint64_t argc = argv.size(); 149 if (intSize == 8) 150 argc = htog((uint64_t)argc); 151 else if (intSize == 4) 152 argc = htog((uint32_t)argc); 153 else 154 panic("Unknown int size"); 155 156 initVirtMem.writeBlob(stack_min, (uint8_t*)&argc, intSize); 157 158 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 159 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 160 161 //Copy the aux stuff 162 for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) { 163 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 164 (uint8_t*)&(auxv[x].a_type), intSize); 165 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 166 (uint8_t*)&(auxv[x].a_val), intSize); 167 } 168 169 ThreadContext *tc = system->getThreadContext(contextIds[0]); 170 171 setSyscallArg(tc, 0, argc); 172 setSyscallArg(tc, 1, argv_array_base); 173 tc->setIntReg(StackPointerReg, stack_min); 174 175 tc->pcState(getStartPC()); 176} 177 178void 179AlphaLiveProcess::setupASNReg() 180{ 181 ThreadContext *tc = system->getThreadContext(contextIds[0]); 182 tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57); 183} 184 185 186void 187AlphaLiveProcess::loadState(CheckpointIn &cp) 188{ 189 LiveProcess::loadState(cp); 190 // need to set up ASN after unserialization since M5_pid value may 191 // come from checkpoint 192 setupASNReg(); 193} 194 195 196void 197AlphaLiveProcess::initState() 198{ 199 // need to set up ASN before further initialization since init 200 // will involve writing to virtual memory addresses 201 setupASNReg(); 202 203 LiveProcess::initState(); 204 205 argsInit(MachineBytes, PageBytes); 206 207 ThreadContext *tc = system->getThreadContext(contextIds[0]); 208 tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); 209 //Operate in user mode 210 tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3); 211 tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3); 212 //No super page mapping 213 tc->setMiscRegNoEffect(IPR_MCSR, 0); 214} 215 216AlphaISA::IntReg 217AlphaLiveProcess::getSyscallArg(ThreadContext *tc, int &i) 218{ 219 assert(i < 6); 220 return tc->readIntReg(FirstArgumentReg + i++); 221} 222 223void 224AlphaLiveProcess::setSyscallArg(ThreadContext *tc, 225 int i, AlphaISA::IntReg val) 226{ 227 assert(i < 6); 228 tc->setIntReg(FirstArgumentReg + i, val); 229} 230 231void 232AlphaLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 233{ 234 // check for error condition. Alpha syscall convention is to 235 // indicate success/failure in reg a3 (r19) and put the 236 // return value itself in the standard return value reg (v0). 237 if (sysret.successful()) { 238 // no error 239 tc->setIntReg(SyscallSuccessReg, 0); 240 tc->setIntReg(ReturnValueReg, sysret.returnValue()); 241 } else { 242 // got an error, return details 243 tc->setIntReg(SyscallSuccessReg, (IntReg)-1); 244 tc->setIntReg(ReturnValueReg, sysret.errnoValue()); 245 } 246} 247