locked_mem.hh revision 12218:8c5db15dc8e7
110037SARM gem5 Developers/* 210037SARM gem5 Developers * Copyright (c) 2012 ARM Limited 310183SCurtis.Dunham@arm.com * All rights reserved 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1410037SARM gem5 Developers * Copyright (c) 2006 The Regents of The University of Michigan 1510037SARM gem5 Developers * All rights reserved. 1610037SARM gem5 Developers * 1710037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 1810037SARM gem5 Developers * modification, are permitted provided that the following conditions are 1910037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 2010037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 2110037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 2210037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 2310037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 2410037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 2510037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 2610037SARM gem5 Developers * this software without specific prior written permission. 2710037SARM gem5 Developers * 2810037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2910037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3010037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3110037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3210037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3310037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3410037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3610037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3710037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3910037SARM gem5 Developers * 4010037SARM gem5 Developers * Authors: Steve Reinhardt 4110184SCurtis.Dunham@arm.com */ 4210037SARM gem5 Developers 4310037SARM gem5 Developers#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__ 4410037SARM gem5 Developers#define __ARCH_ALPHA_LOCKED_MEM_HH__ 4510037SARM gem5 Developers 4610037SARM gem5 Developers/** 4710037SARM gem5 Developers * @file 4810037SARM gem5 Developers * 4910037SARM gem5 Developers * ISA-specific helper functions for locked memory accesses. 5010037SARM gem5 Developers * 5110037SARM gem5 Developers * Note that these functions are not embedded in the ISA description 5210184SCurtis.Dunham@arm.com * because they operate on the *physical* address rather than the 5310037SARM gem5 Developers * virtual address. In the current M5 design, the physical address is 5410037SARM gem5 Developers * not accessible from the ISA description, only from the CPU model. 5510037SARM gem5 Developers * Thus the CPU is responsible for calling back to the ISA (here) 5610037SARM gem5 Developers * after the address translation has been performed to allow the ISA 5710037SARM gem5 Developers * to do these manipulations based on the physical address. 5810037SARM gem5 Developers */ 5910037SARM gem5 Developers 6010037SARM gem5 Developers#include "arch/alpha/registers.hh" 6110037SARM gem5 Developers#include "base/misc.hh" 6210184SCurtis.Dunham@arm.com#include "mem/packet.hh" 6310037SARM gem5 Developers#include "mem/request.hh" 6410037SARM gem5 Developers 6510037SARM gem5 Developersnamespace AlphaISA { 6610037SARM gem5 Developers 6710037SARM gem5 Developerstemplate <class XC> 6810037SARM gem5 Developersinline void 6910037SARM gem5 DevelopershandleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) 7010037SARM gem5 Developers{ 7110037SARM gem5 Developers // If we see a snoop come into the CPU and we currently have an LLSC 7210037SARM gem5 Developers // operation pending we need to clear the lock flag if it is to the same 7310037SARM gem5 Developers // cache line. 7410037SARM gem5 Developers 7510184SCurtis.Dunham@arm.com if (!xc->readMiscReg(MISCREG_LOCKFLAG)) 7610037SARM gem5 Developers return; 7710037SARM gem5 Developers 7810037SARM gem5 Developers Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 7910037SARM gem5 Developers Addr snoop_addr = pkt->getAddr() & cacheBlockMask; 8010037SARM gem5 Developers 8110037SARM gem5 Developers if (locked_addr == snoop_addr) 8210037SARM gem5 Developers xc->setMiscReg(MISCREG_LOCKFLAG, false); 8310037SARM gem5 Developers} 8410037SARM gem5 Developers 8510037SARM gem5 Developers 8610037SARM gem5 Developerstemplate <class XC> 8710037SARM gem5 Developersinline void 8810037SARM gem5 DevelopershandleLockedRead(XC *xc, Request *req) 8910037SARM gem5 Developers{ 9010037SARM gem5 Developers xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); 9110037SARM gem5 Developers xc->setMiscReg(MISCREG_LOCKFLAG, true); 9210037SARM gem5 Developers} 9310037SARM gem5 Developers 9410037SARM gem5 Developerstemplate <class XC> 9512616Sgabeblack@google.cominline void 9610037SARM gem5 DevelopershandleLockedSnoopHit(XC *xc) 9710037SARM gem5 Developers{ 9810037SARM gem5 Developers} 9910037SARM gem5 Developers 10010184SCurtis.Dunham@arm.comtemplate <class XC> 10110037SARM gem5 Developersinline bool 10210037SARM gem5 DevelopershandleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask) 10310037SARM gem5 Developers{ 10410037SARM gem5 Developers if (req->isUncacheable()) { 10510037SARM gem5 Developers // Funky Turbolaser mailbox access...don't update 10610037SARM gem5 Developers // result register (see stq_c in decoder.isa) 10710037SARM gem5 Developers req->setExtraData(2); 10810037SARM gem5 Developers } else { 10910037SARM gem5 Developers // standard store conditional 11010037SARM gem5 Developers bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); 11110037SARM gem5 Developers Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR); 112 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 113 // Lock flag not set or addr mismatch in CPU; 114 // don't even bother sending to memory system 115 req->setExtraData(0); 116 xc->setMiscReg(MISCREG_LOCKFLAG, false); 117 // the rest of this code is not architectural; 118 // it's just a debugging aid to help detect 119 // livelock by warning on long sequences of failed 120 // store conditionals 121 int stCondFailures = xc->readStCondFailures(); 122 stCondFailures++; 123 xc->setStCondFailures(stCondFailures); 124 if (stCondFailures % 100000 == 0) { 125 warn("context %d: %d consecutive " 126 "store conditional failures\n", 127 xc->contextId(), stCondFailures); 128 } 129 130 // store conditional failed already, so don't issue it to mem 131 return false; 132 } 133 } 134 135 return true; 136} 137 138template <class XC> 139inline void 140globalClearExclusive(XC *xc) 141{ 142 xc->getCpuPtr()->wakeup(xc->threadId()); 143} 144 145} // namespace AlphaISA 146 147#endif // __ARCH_ALPHA_LOCKED_MEM_HH__ 148