locked_mem.hh revision 4120
13170Sstever@eecs.umich.edu/* 23170Sstever@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 33170Sstever@eecs.umich.edu * All rights reserved. 43170Sstever@eecs.umich.edu * 53170Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63170Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 73170Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83170Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93170Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103170Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113170Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123170Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133170Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143170Sstever@eecs.umich.edu * this software without specific prior written permission. 153170Sstever@eecs.umich.edu * 163170Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173170Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183170Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193170Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203170Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213170Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223170Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233170Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243170Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253170Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263170Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273170Sstever@eecs.umich.edu * 283170Sstever@eecs.umich.edu * Authors: Steve Reinhardt 293170Sstever@eecs.umich.edu */ 303170Sstever@eecs.umich.edu 313170Sstever@eecs.umich.edu#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__ 323170Sstever@eecs.umich.edu#define __ARCH_ALPHA_LOCKED_MEM_HH__ 333170Sstever@eecs.umich.edu 343170Sstever@eecs.umich.edu/** 353170Sstever@eecs.umich.edu * @file 363170Sstever@eecs.umich.edu * 373170Sstever@eecs.umich.edu * ISA-specific helper functions for locked memory accesses. 384027Sstever@eecs.umich.edu * 394027Sstever@eecs.umich.edu * Note that these functions are not embedded in the ISA description 404027Sstever@eecs.umich.edu * because they operate on the *physical* address rather than the 414027Sstever@eecs.umich.edu * virtual address. In the current M5 design, the physical address is 424027Sstever@eecs.umich.edu * not accessible from the ISA description, only from the CPU model. 434027Sstever@eecs.umich.edu * Thus the CPU is responsible for calling back to the ISA (here) 444027Sstever@eecs.umich.edu * after the address translation has been performed to allow the ISA 454027Sstever@eecs.umich.edu * to do these manipulations based on the physical address. 463170Sstever@eecs.umich.edu */ 473170Sstever@eecs.umich.edu 483586Sgblack@eecs.umich.edu#include "arch/alpha/miscregfile.hh" 493170Sstever@eecs.umich.edu#include "base/misc.hh" 503170Sstever@eecs.umich.edu#include "mem/request.hh" 513170Sstever@eecs.umich.edu 523170Sstever@eecs.umich.edu 533170Sstever@eecs.umich.edunamespace AlphaISA 543170Sstever@eecs.umich.edu{ 553170Sstever@eecs.umich.edutemplate <class XC> 563170Sstever@eecs.umich.eduinline void 573170Sstever@eecs.umich.eduhandleLockedRead(XC *xc, Request *req) 583170Sstever@eecs.umich.edu{ 593586Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); 603586Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_LOCKFLAG, true); 613170Sstever@eecs.umich.edu} 623170Sstever@eecs.umich.edu 633170Sstever@eecs.umich.edu 643170Sstever@eecs.umich.edutemplate <class XC> 653170Sstever@eecs.umich.eduinline bool 663170Sstever@eecs.umich.eduhandleLockedWrite(XC *xc, Request *req) 673170Sstever@eecs.umich.edu{ 683170Sstever@eecs.umich.edu if (req->isUncacheable()) { 693170Sstever@eecs.umich.edu // Funky Turbolaser mailbox access...don't update 703170Sstever@eecs.umich.edu // result register (see stq_c in decoder.isa) 714040Ssaidi@eecs.umich.edu req->setExtraData(2); 723170Sstever@eecs.umich.edu } else { 733170Sstever@eecs.umich.edu // standard store conditional 743586Sgblack@eecs.umich.edu bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); 753586Sgblack@eecs.umich.edu Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR); 763170Sstever@eecs.umich.edu if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 773170Sstever@eecs.umich.edu // Lock flag not set or addr mismatch in CPU; 783170Sstever@eecs.umich.edu // don't even bother sending to memory system 794040Ssaidi@eecs.umich.edu req->setExtraData(0); 803586Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_LOCKFLAG, false); 813170Sstever@eecs.umich.edu // the rest of this code is not architectural; 823170Sstever@eecs.umich.edu // it's just a debugging aid to help detect 833170Sstever@eecs.umich.edu // livelock by warning on long sequences of failed 843170Sstever@eecs.umich.edu // store conditionals 853170Sstever@eecs.umich.edu int stCondFailures = xc->readStCondFailures(); 863170Sstever@eecs.umich.edu stCondFailures++; 873170Sstever@eecs.umich.edu xc->setStCondFailures(stCondFailures); 883170Sstever@eecs.umich.edu if (stCondFailures % 100000 == 0) { 893170Sstever@eecs.umich.edu warn("cpu %d: %d consecutive " 903170Sstever@eecs.umich.edu "store conditional failures\n", 913170Sstever@eecs.umich.edu xc->readCpuId(), stCondFailures); 923170Sstever@eecs.umich.edu } 933170Sstever@eecs.umich.edu 943170Sstever@eecs.umich.edu // store conditional failed already, so don't issue it to mem 953170Sstever@eecs.umich.edu return false; 963170Sstever@eecs.umich.edu } 973170Sstever@eecs.umich.edu } 983170Sstever@eecs.umich.edu 993170Sstever@eecs.umich.edu return true; 1003170Sstever@eecs.umich.edu} 1013170Sstever@eecs.umich.edu 1023170Sstever@eecs.umich.edu 1033170Sstever@eecs.umich.edu} // namespace AlphaISA 1043170Sstever@eecs.umich.edu 1053170Sstever@eecs.umich.edu#endif 106