locked_mem.hh revision 12749
13170Sstever@eecs.umich.edu/* 29383SAli.Saidi@ARM.com * Copyright (c) 2012 ARM Limited 39383SAli.Saidi@ARM.com * All rights reserved 49383SAli.Saidi@ARM.com * 59383SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 69383SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 79383SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 89383SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 99383SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 109383SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 119383SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 129383SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 139383SAli.Saidi@ARM.com * 143170Sstever@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 153170Sstever@eecs.umich.edu * All rights reserved. 163170Sstever@eecs.umich.edu * 173170Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 183170Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 193170Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 203170Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 213170Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 223170Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 233170Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 243170Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 253170Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 263170Sstever@eecs.umich.edu * this software without specific prior written permission. 273170Sstever@eecs.umich.edu * 283170Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293170Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303170Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313170Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323170Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333170Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343170Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353170Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363170Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373170Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383170Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393170Sstever@eecs.umich.edu * 403170Sstever@eecs.umich.edu * Authors: Steve Reinhardt 413170Sstever@eecs.umich.edu */ 423170Sstever@eecs.umich.edu 433170Sstever@eecs.umich.edu#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__ 443170Sstever@eecs.umich.edu#define __ARCH_ALPHA_LOCKED_MEM_HH__ 453170Sstever@eecs.umich.edu 463170Sstever@eecs.umich.edu/** 473170Sstever@eecs.umich.edu * @file 483170Sstever@eecs.umich.edu * 493170Sstever@eecs.umich.edu * ISA-specific helper functions for locked memory accesses. 504027Sstever@eecs.umich.edu * 514027Sstever@eecs.umich.edu * Note that these functions are not embedded in the ISA description 524027Sstever@eecs.umich.edu * because they operate on the *physical* address rather than the 534027Sstever@eecs.umich.edu * virtual address. In the current M5 design, the physical address is 544027Sstever@eecs.umich.edu * not accessible from the ISA description, only from the CPU model. 554027Sstever@eecs.umich.edu * Thus the CPU is responsible for calling back to the ISA (here) 564027Sstever@eecs.umich.edu * after the address translation has been performed to allow the ISA 574027Sstever@eecs.umich.edu * to do these manipulations based on the physical address. 583170Sstever@eecs.umich.edu */ 593170Sstever@eecs.umich.edu 606330Sgblack@eecs.umich.edu#include "arch/alpha/registers.hh" 6112334Sgabeblack@google.com#include "base/logging.hh" 629383SAli.Saidi@ARM.com#include "mem/packet.hh" 633170Sstever@eecs.umich.edu#include "mem/request.hh" 643170Sstever@eecs.umich.edu 655569Snate@binkert.orgnamespace AlphaISA { 663170Sstever@eecs.umich.edu 673170Sstever@eecs.umich.edutemplate <class XC> 683170Sstever@eecs.umich.eduinline void 699383SAli.Saidi@ARM.comhandleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) 709383SAli.Saidi@ARM.com{ 719383SAli.Saidi@ARM.com // If we see a snoop come into the CPU and we currently have an LLSC 729383SAli.Saidi@ARM.com // operation pending we need to clear the lock flag if it is to the same 739383SAli.Saidi@ARM.com // cache line. 749383SAli.Saidi@ARM.com 759383SAli.Saidi@ARM.com if (!xc->readMiscReg(MISCREG_LOCKFLAG)) 769383SAli.Saidi@ARM.com return; 779383SAli.Saidi@ARM.com 789383SAli.Saidi@ARM.com Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 7910574Sandreas.hansson@arm.com Addr snoop_addr = pkt->getAddr() & cacheBlockMask; 809383SAli.Saidi@ARM.com 819383SAli.Saidi@ARM.com if (locked_addr == snoop_addr) 829383SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKFLAG, false); 839383SAli.Saidi@ARM.com} 849383SAli.Saidi@ARM.com 859383SAli.Saidi@ARM.com 869383SAli.Saidi@ARM.comtemplate <class XC> 879383SAli.Saidi@ARM.cominline void 8812749Sgiacomo.travaglini@arm.comhandleLockedRead(XC *xc, const RequestPtr &req) 893170Sstever@eecs.umich.edu{ 907783SGiacomo.Gabrielli@arm.com xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); 917783SGiacomo.Gabrielli@arm.com xc->setMiscReg(MISCREG_LOCKFLAG, true); 923170Sstever@eecs.umich.edu} 933170Sstever@eecs.umich.edu 9410030SAli.Saidi@ARM.comtemplate <class XC> 9510030SAli.Saidi@ARM.cominline void 9610030SAli.Saidi@ARM.comhandleLockedSnoopHit(XC *xc) 9710030SAli.Saidi@ARM.com{ 9810030SAli.Saidi@ARM.com} 993170Sstever@eecs.umich.edu 1003170Sstever@eecs.umich.edutemplate <class XC> 1013170Sstever@eecs.umich.eduinline bool 10212749Sgiacomo.travaglini@arm.comhandleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) 1033170Sstever@eecs.umich.edu{ 1043170Sstever@eecs.umich.edu if (req->isUncacheable()) { 1053170Sstever@eecs.umich.edu // Funky Turbolaser mailbox access...don't update 1063170Sstever@eecs.umich.edu // result register (see stq_c in decoder.isa) 1074040Ssaidi@eecs.umich.edu req->setExtraData(2); 1083170Sstever@eecs.umich.edu } else { 1093170Sstever@eecs.umich.edu // standard store conditional 1107783SGiacomo.Gabrielli@arm.com bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); 1117783SGiacomo.Gabrielli@arm.com Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR); 1123170Sstever@eecs.umich.edu if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 1133170Sstever@eecs.umich.edu // Lock flag not set or addr mismatch in CPU; 1143170Sstever@eecs.umich.edu // don't even bother sending to memory system 1154040Ssaidi@eecs.umich.edu req->setExtraData(0); 1167783SGiacomo.Gabrielli@arm.com xc->setMiscReg(MISCREG_LOCKFLAG, false); 1173170Sstever@eecs.umich.edu // the rest of this code is not architectural; 1183170Sstever@eecs.umich.edu // it's just a debugging aid to help detect 1193170Sstever@eecs.umich.edu // livelock by warning on long sequences of failed 1203170Sstever@eecs.umich.edu // store conditionals 1213170Sstever@eecs.umich.edu int stCondFailures = xc->readStCondFailures(); 1223170Sstever@eecs.umich.edu stCondFailures++; 1233170Sstever@eecs.umich.edu xc->setStCondFailures(stCondFailures); 1243170Sstever@eecs.umich.edu if (stCondFailures % 100000 == 0) { 1255714Shsul@eecs.umich.edu warn("context %d: %d consecutive " 1263170Sstever@eecs.umich.edu "store conditional failures\n", 1275714Shsul@eecs.umich.edu xc->contextId(), stCondFailures); 1283170Sstever@eecs.umich.edu } 1293170Sstever@eecs.umich.edu 1303170Sstever@eecs.umich.edu // store conditional failed already, so don't issue it to mem 1313170Sstever@eecs.umich.edu return false; 1323170Sstever@eecs.umich.edu } 1333170Sstever@eecs.umich.edu } 1343170Sstever@eecs.umich.edu 1353170Sstever@eecs.umich.edu return true; 1363170Sstever@eecs.umich.edu} 1373170Sstever@eecs.umich.edu 13812218Snikos.nikoleris@arm.comtemplate <class XC> 13912218Snikos.nikoleris@arm.cominline void 14012218Snikos.nikoleris@arm.comglobalClearExclusive(XC *xc) 14112218Snikos.nikoleris@arm.com{ 14212218Snikos.nikoleris@arm.com xc->getCpuPtr()->wakeup(xc->threadId()); 14312218Snikos.nikoleris@arm.com} 14412218Snikos.nikoleris@arm.com 1453170Sstever@eecs.umich.edu} // namespace AlphaISA 1463170Sstever@eecs.umich.edu 1475569Snate@binkert.org#endif // __ARCH_ALPHA_LOCKED_MEM_HH__ 148