isa_traits.hh revision 6974
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Gabe Black 30 */ 31 32#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 33#define __ARCH_ALPHA_ISA_TRAITS_HH__ 34 35namespace LittleEndianGuest {} 36 37#include "arch/alpha/types.hh" 38#include "base/types.hh" 39#include "config/full_system.hh" 40 41class StaticInstPtr; 42 43namespace AlphaISA { 44 45using namespace LittleEndianGuest; 46 47StaticInstPtr decodeInst(ExtMachInst); 48 49// Alpha Does NOT have a delay slot 50#define ISA_HAS_DELAY_SLOT 0 51 52const Addr PageShift = 13; 53const Addr PageBytes = ULL(1) << PageShift; 54const Addr PageMask = ~(PageBytes - 1); 55const Addr PageOffset = PageBytes - 1; 56 57//////////////////////////////////////////////////////////////////////// 58// 59// Translation stuff 60// 61 62const Addr PteShift = 3; 63const Addr NPtePageShift = PageShift - PteShift; 64const Addr NPtePage = ULL(1) << NPtePageShift; 65const Addr PteMask = NPtePage - 1; 66 67// User Virtual 68const Addr USegBase = ULL(0x0); 69const Addr USegEnd = ULL(0x000003ffffffffff); 70 71// Kernel Direct Mapped 72const Addr K0SegBase = ULL(0xfffffc0000000000); 73const Addr K0SegEnd = ULL(0xfffffdffffffffff); 74 75// Kernel Virtual 76const Addr K1SegBase = ULL(0xfffffe0000000000); 77const Addr K1SegEnd = ULL(0xffffffffffffffff); 78 79// For loading... XXX This maybe could be USegEnd?? --ali 80const Addr LoadAddrMask = ULL(0xffffffffff); 81 82//////////////////////////////////////////////////////////////////////// 83// 84// Interrupt levels 85// 86enum InterruptLevels 87{ 88 INTLEVEL_SOFTWARE_MIN = 4, 89 INTLEVEL_SOFTWARE_MAX = 19, 90 91 INTLEVEL_EXTERNAL_MIN = 20, 92 INTLEVEL_EXTERNAL_MAX = 34, 93 94 INTLEVEL_IRQ0 = 20, 95 INTLEVEL_IRQ1 = 21, 96 INTINDEX_ETHERNET = 0, 97 INTINDEX_SCSI = 1, 98 INTLEVEL_IRQ2 = 22, 99 INTLEVEL_IRQ3 = 23, 100 101 INTLEVEL_SERIAL = 33, 102 103 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 104}; 105 106// EV5 modes 107enum mode_type 108{ 109 mode_kernel = 0, // kernel 110 mode_executive = 1, // executive (unused by unix) 111 mode_supervisor = 2, // supervisor (unused by unix) 112 mode_user = 3, // user mode 113 mode_number // number of modes 114}; 115 116// Constants Related to the number of registers 117 118enum { 119 LogVMPageSize = 13, // 8K bytes 120 VMPageSize = (1 << LogVMPageSize), 121 122 BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned 123 124 MachineBytes = 8, 125 WordBytes = 4, 126 HalfwordBytes = 2, 127 ByteBytes = 1, 128}; 129 130// return a no-op instruction... used for instruction fetch faults 131// Alpha UNOP (ldq_u r31,0(r0)) 132const ExtMachInst NoopMachInst = 0x2ffe0000; 133 134// Memory accesses cannot be unaligned 135const bool HasUnalignedMemAcc = false; 136 137} // namespace AlphaISA 138 139#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 140