isa_traits.hh revision 6327:f6148086f997 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Gabe Black
30 */
31
32#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
33#define __ARCH_ALPHA_ISA_TRAITS_HH__
34
35namespace LittleEndianGuest {}
36
37#include "arch/alpha/ipr.hh"
38#include "arch/alpha/max_inst_regs.hh"
39#include "arch/alpha/types.hh"
40#include "base/types.hh"
41#include "config/full_system.hh"
42
43class StaticInstPtr;
44
45namespace AlphaISA {
46
47using namespace LittleEndianGuest;
48using AlphaISAInst::MaxInstSrcRegs;
49using AlphaISAInst::MaxInstDestRegs;
50
51// These enumerate all the registers for dependence tracking.
52enum DependenceTags {
53    // 0..31 are the integer regs 0..31
54    // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
55    FP_Base_DepTag = 40,
56    Ctrl_Base_DepTag = 72
57};
58
59StaticInstPtr decodeInst(ExtMachInst);
60
61// Alpha Does NOT have a delay slot
62#define ISA_HAS_DELAY_SLOT 0
63
64const Addr PageShift = 13;
65const Addr PageBytes = ULL(1) << PageShift;
66const Addr PageMask = ~(PageBytes - 1);
67const Addr PageOffset = PageBytes - 1;
68
69////////////////////////////////////////////////////////////////////////
70//
71//  Translation stuff
72//
73
74const Addr PteShift = 3;
75const Addr NPtePageShift = PageShift - PteShift;
76const Addr NPtePage = ULL(1) << NPtePageShift;
77const Addr PteMask = NPtePage - 1;
78
79// User Virtual
80const Addr USegBase = ULL(0x0);
81const Addr USegEnd = ULL(0x000003ffffffffff);
82
83// Kernel Direct Mapped
84const Addr K0SegBase = ULL(0xfffffc0000000000);
85const Addr K0SegEnd = ULL(0xfffffdffffffffff);
86
87// Kernel Virtual
88const Addr K1SegBase = ULL(0xfffffe0000000000);
89const Addr K1SegEnd = ULL(0xffffffffffffffff);
90
91// For loading... XXX This maybe could be USegEnd?? --ali
92const Addr LoadAddrMask = ULL(0xffffffffff);
93
94////////////////////////////////////////////////////////////////////////
95//
96//  Interrupt levels
97//
98enum InterruptLevels
99{
100    INTLEVEL_SOFTWARE_MIN = 4,
101    INTLEVEL_SOFTWARE_MAX = 19,
102
103    INTLEVEL_EXTERNAL_MIN = 20,
104    INTLEVEL_EXTERNAL_MAX = 34,
105
106    INTLEVEL_IRQ0 = 20,
107    INTLEVEL_IRQ1 = 21,
108    INTINDEX_ETHERNET = 0,
109    INTINDEX_SCSI = 1,
110    INTLEVEL_IRQ2 = 22,
111    INTLEVEL_IRQ3 = 23,
112
113    INTLEVEL_SERIAL = 33,
114
115    NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
116};
117
118// EV5 modes
119enum mode_type
120{
121    mode_kernel = 0,        // kernel
122    mode_executive = 1,     // executive (unused by unix)
123    mode_supervisor = 2,    // supervisor (unused by unix)
124    mode_user = 3,          // user mode
125    mode_number             // number of modes
126};
127
128// Constants Related to the number of registers
129
130enum {
131    // semantically meaningful register indices
132    ZeroReg = 31,     // architecturally meaningful
133    // the rest of these depend on the ABI
134    StackPointerReg = 30,
135    GlobalPointerReg = 29,
136    ProcedureValueReg = 27,
137    ReturnAddressReg = 26,
138    ReturnValueReg = 0,
139    FramePointerReg = 15,
140
141    SyscallNumReg = 0,
142    FirstArgumentReg = 16,
143    SyscallPseudoReturnReg = 20,
144    SyscallSuccessReg = 19,
145
146    LogVMPageSize = 13,       // 8K bytes
147    VMPageSize = (1 << LogVMPageSize),
148
149    BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
150
151    MachineBytes = 8,
152    WordBytes = 4,
153    HalfwordBytes = 2,
154    ByteBytes = 1,
155};
156
157// return a no-op instruction... used for instruction fetch faults
158// Alpha UNOP (ldq_u r31,0(r0))
159const ExtMachInst NoopMachInst = 0x2ffe0000;
160
161} // namespace AlphaISA
162
163#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
164