isa_traits.hh revision 5543:3af77710f397 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Gabe Black
30 */
31
32#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
33#define __ARCH_ALPHA_ISA_TRAITS_HH__
34
35namespace LittleEndianGuest {}
36
37#include "arch/alpha/ipr.hh"
38#include "arch/alpha/max_inst_regs.hh"
39#include "arch/alpha/types.hh"
40#include "config/full_system.hh"
41#include "sim/host.hh"
42
43class StaticInstPtr;
44
45namespace AlphaISA
46{
47    using namespace LittleEndianGuest;
48    using AlphaISAInst::MaxInstSrcRegs;
49    using AlphaISAInst::MaxInstDestRegs;
50
51    // These enumerate all the registers for dependence tracking.
52    enum DependenceTags {
53        // 0..31 are the integer regs 0..31
54        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
55        FP_Base_DepTag = 40,
56        Ctrl_Base_DepTag = 72
57    };
58
59    StaticInstPtr decodeInst(ExtMachInst);
60
61    // Alpha Does NOT have a delay slot
62    #define ISA_HAS_DELAY_SLOT 0
63
64    const Addr PageShift = 13;
65    const Addr PageBytes = ULL(1) << PageShift;
66    const Addr PageMask = ~(PageBytes - 1);
67    const Addr PageOffset = PageBytes - 1;
68
69
70    ////////////////////////////////////////////////////////////////////////
71    //
72    //  Translation stuff
73    //
74
75    const Addr PteShift = 3;
76    const Addr NPtePageShift = PageShift - PteShift;
77    const Addr NPtePage = ULL(1) << NPtePageShift;
78    const Addr PteMask = NPtePage - 1;
79
80    // User Virtual
81    const Addr USegBase = ULL(0x0);
82    const Addr USegEnd = ULL(0x000003ffffffffff);
83
84    // Kernel Direct Mapped
85    const Addr K0SegBase = ULL(0xfffffc0000000000);
86    const Addr K0SegEnd = ULL(0xfffffdffffffffff);
87
88    // Kernel Virtual
89    const Addr K1SegBase = ULL(0xfffffe0000000000);
90    const Addr K1SegEnd = ULL(0xffffffffffffffff);
91
92    // For loading... XXX This maybe could be USegEnd?? --ali
93    const Addr LoadAddrMask = ULL(0xffffffffff);
94
95#if FULL_SYSTEM
96
97    ////////////////////////////////////////////////////////////////////////
98    //
99    //  Interrupt levels
100    //
101    enum InterruptLevels
102    {
103        INTLEVEL_SOFTWARE_MIN = 4,
104        INTLEVEL_SOFTWARE_MAX = 19,
105
106        INTLEVEL_EXTERNAL_MIN = 20,
107        INTLEVEL_EXTERNAL_MAX = 34,
108
109        INTLEVEL_IRQ0 = 20,
110        INTLEVEL_IRQ1 = 21,
111        INTINDEX_ETHERNET = 0,
112        INTINDEX_SCSI = 1,
113        INTLEVEL_IRQ2 = 22,
114        INTLEVEL_IRQ3 = 23,
115
116        INTLEVEL_SERIAL = 33,
117
118        NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
119    };
120
121#endif
122
123    // EV5 modes
124    enum mode_type
125    {
126        mode_kernel = 0,        // kernel
127        mode_executive = 1,     // executive (unused by unix)
128        mode_supervisor = 2,    // supervisor (unused by unix)
129        mode_user = 3,          // user mode
130        mode_number             // number of modes
131    };
132
133    // Constants Related to the number of registers
134
135    const int NumIntArchRegs = 32;
136    const int NumPALShadowRegs = 8;
137    const int NumFloatArchRegs = 32;
138    // @todo: Figure out what this number really should be.
139    const int NumMiscArchRegs = 77;
140
141    const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
142    const int NumFloatRegs = NumFloatArchRegs;
143    const int NumMiscRegs = NumMiscArchRegs;
144
145    const int TotalNumRegs = NumIntRegs + NumFloatRegs +
146        NumMiscRegs + NumInternalProcRegs;
147
148    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
149
150    // semantically meaningful register indices
151    const int ZeroReg = 31;     // architecturally meaningful
152    // the rest of these depend on the ABI
153    const int StackPointerReg = 30;
154    const int GlobalPointerReg = 29;
155    const int ProcedureValueReg = 27;
156    const int ReturnAddressReg = 26;
157    const int ReturnValueReg = 0;
158    const int FramePointerReg = 15;
159
160    const int ArgumentReg[] = {16, 17, 18, 19, 20, 21};
161    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
162
163    const int SyscallNumReg = ReturnValueReg;
164    const int SyscallPseudoReturnReg = ArgumentReg[4];
165    const int SyscallSuccessReg = 19;
166
167    const int LogVMPageSize = 13;       // 8K bytes
168    const int VMPageSize = (1 << LogVMPageSize);
169
170    const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
171
172    const int MachineBytes = 8;
173    const int WordBytes = 4;
174    const int HalfwordBytes = 2;
175    const int ByteBytes = 1;
176
177    // return a no-op instruction... used for instruction fetch faults
178    // Alpha UNOP (ldq_u r31,0(r0))
179    const ExtMachInst NoopMachInst = 0x2ffe0000;
180
181};
182
183#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
184