isa_traits.hh revision 2972 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Gabe Black
30 */
31
32#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
33#define __ARCH_ALPHA_ISA_TRAITS_HH__
34
35namespace LittleEndianGuest {}
36
37#include "arch/alpha/types.hh"
38#include "arch/alpha/isa_traits.hh"
39#include "config/full_system.hh"
40#include "sim/host.hh"
41
42class StaticInstPtr;
43
44#if FULL_SYSTEM
45#include "arch/alpha/isa_fullsys_traits.hh"
46#endif
47
48
49namespace AlphaISA
50{
51
52    using namespace LittleEndianGuest;
53
54    // These enumerate all the registers for dependence tracking.
55    enum DependenceTags {
56        // 0..31 are the integer regs 0..31
57        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
58        FP_Base_DepTag = 40,
59        Ctrl_Base_DepTag = 72,
60        Fpcr_DepTag = 72,		// floating point control register
61        Uniq_DepTag = 73,
62        Lock_Flag_DepTag = 74,
63        Lock_Addr_DepTag = 75,
64        IPR_Base_DepTag = 76
65    };
66
67    StaticInstPtr decodeInst(ExtMachInst);
68
69    const Addr PageShift = 13;
70    const Addr PageBytes = ULL(1) << PageShift;
71    const Addr PageMask = ~(PageBytes - 1);
72    const Addr PageOffset = PageBytes - 1;
73
74
75#if FULL_SYSTEM
76
77    ////////////////////////////////////////////////////////////////////////
78    //
79    //  Translation stuff
80    //
81
82   const Addr PteShift = 3;
83    const Addr NPtePageShift = PageShift - PteShift;
84    const Addr NPtePage = ULL(1) << NPtePageShift;
85    const Addr PteMask = NPtePage - 1;
86
87    // User Virtual
88    const Addr USegBase = ULL(0x0);
89    const Addr USegEnd = ULL(0x000003ffffffffff);
90
91    // Kernel Direct Mapped
92    const Addr K0SegBase = ULL(0xfffffc0000000000);
93    const Addr K0SegEnd = ULL(0xfffffdffffffffff);
94
95    // Kernel Virtual
96    const Addr K1SegBase = ULL(0xfffffe0000000000);
97    const Addr K1SegEnd = ULL(0xffffffffffffffff);
98
99    // For loading... XXX This maybe could be USegEnd?? --ali
100    const Addr LoadAddrMask = ULL(0xffffffffff);
101
102    ////////////////////////////////////////////////////////////////////////
103    //
104    //  Interrupt levels
105    //
106    enum InterruptLevels
107    {
108        INTLEVEL_SOFTWARE_MIN = 4,
109        INTLEVEL_SOFTWARE_MAX = 19,
110
111        INTLEVEL_EXTERNAL_MIN = 20,
112        INTLEVEL_EXTERNAL_MAX = 34,
113
114        INTLEVEL_IRQ0 = 20,
115        INTLEVEL_IRQ1 = 21,
116        INTINDEX_ETHERNET = 0,
117        INTINDEX_SCSI = 1,
118        INTLEVEL_IRQ2 = 22,
119        INTLEVEL_IRQ3 = 23,
120
121        INTLEVEL_SERIAL = 33,
122
123        NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
124    };
125
126
127    // EV5 modes
128    enum mode_type
129    {
130        mode_kernel = 0,		// kernel
131        mode_executive = 1,		// executive (unused by unix)
132        mode_supervisor = 2,	// supervisor (unused by unix)
133        mode_user = 3,		// user mode
134        mode_number			// number of modes
135    };
136
137#endif
138
139#if FULL_SYSTEM
140    ////////////////////////////////////////////////////////////////////////
141    //
142    //  Internal Processor Reigsters
143    //
144    enum md_ipr_names
145    {
146        IPR_ISR = 0x100,		// interrupt summary register
147        IPR_ITB_TAG = 0x101,	// ITLB tag register
148        IPR_ITB_PTE = 0x102,	// ITLB page table entry register
149        IPR_ITB_ASN = 0x103,	// ITLB address space register
150        IPR_ITB_PTE_TEMP = 0x104,	// ITLB page table entry temp register
151        IPR_ITB_IA = 0x105,		// ITLB invalidate all register
152        IPR_ITB_IAP = 0x106,	// ITLB invalidate all process register
153        IPR_ITB_IS = 0x107,		// ITLB invalidate select register
154        IPR_SIRR = 0x108,		// software interrupt request register
155        IPR_ASTRR = 0x109,		// asynchronous system trap request register
156        IPR_ASTER = 0x10a,		// asynchronous system trap enable register
157        IPR_EXC_ADDR = 0x10b,	// exception address register
158        IPR_EXC_SUM = 0x10c,	// exception summary register
159        IPR_EXC_MASK = 0x10d,	// exception mask register
160        IPR_PAL_BASE = 0x10e,	// PAL base address register
161        IPR_ICM = 0x10f,		// instruction current mode
162        IPR_IPLR = 0x110,		// interrupt priority level register
163        IPR_INTID = 0x111,		// interrupt ID register
164        IPR_IFAULT_VA_FORM = 0x112,	// formatted faulting virtual addr register
165        IPR_IVPTBR = 0x113,		// virtual page table base register
166        IPR_HWINT_CLR = 0x115,	// H/W interrupt clear register
167        IPR_SL_XMIT = 0x116,	// serial line transmit register
168        IPR_SL_RCV = 0x117,		// serial line receive register
169        IPR_ICSR = 0x118,		// instruction control and status register
170        IPR_IC_FLUSH = 0x119,	// instruction cache flush control
171        IPR_IC_PERR_STAT = 0x11a,	// inst cache parity error status register
172        IPR_PMCTR = 0x11c,		// performance counter register
173
174        // PAL temporary registers...
175        // register meanings gleaned from osfpal.s source code
176        IPR_PALtemp0 = 0x140,	// local scratch
177        IPR_PALtemp1 = 0x141,	// local scratch
178        IPR_PALtemp2 = 0x142,	// entUna
179        IPR_PALtemp3 = 0x143,	// CPU specific impure area pointer
180        IPR_PALtemp4 = 0x144,	// memory management temp
181        IPR_PALtemp5 = 0x145,	// memory management temp
182        IPR_PALtemp6 = 0x146,	// memory management temp
183        IPR_PALtemp7 = 0x147,	// entIF
184        IPR_PALtemp8 = 0x148,	// intmask
185        IPR_PALtemp9 = 0x149,	// entSys
186        IPR_PALtemp10 = 0x14a,	// ??
187        IPR_PALtemp11 = 0x14b,	// entInt
188        IPR_PALtemp12 = 0x14c,	// entArith
189        IPR_PALtemp13 = 0x14d,	// reserved for platform specific PAL
190        IPR_PALtemp14 = 0x14e,	// reserved for platform specific PAL
191        IPR_PALtemp15 = 0x14f,	// reserved for platform specific PAL
192        IPR_PALtemp16 = 0x150,	// scratch / whami<7:0> / mces<4:0>
193        IPR_PALtemp17 = 0x151,	// sysval
194        IPR_PALtemp18 = 0x152,	// usp
195        IPR_PALtemp19 = 0x153,	// ksp
196        IPR_PALtemp20 = 0x154,	// PTBR
197        IPR_PALtemp21 = 0x155,	// entMM
198        IPR_PALtemp22 = 0x156,	// kgp
199        IPR_PALtemp23 = 0x157,	// PCBB
200
201        IPR_DTB_ASN = 0x200,	// DTLB address space number register
202        IPR_DTB_CM = 0x201,		// DTLB current mode register
203        IPR_DTB_TAG = 0x202,	// DTLB tag register
204        IPR_DTB_PTE = 0x203,	// DTLB page table entry register
205        IPR_DTB_PTE_TEMP = 0x204,	// DTLB page table entry temporary register
206
207        IPR_MM_STAT = 0x205,	// data MMU fault status register
208        IPR_VA = 0x206,		// fault virtual address register
209        IPR_VA_FORM = 0x207,	// formatted virtual address register
210        IPR_MVPTBR = 0x208,		// MTU virtual page table base register
211        IPR_DTB_IAP = 0x209,	// DTLB invalidate all process register
212        IPR_DTB_IA = 0x20a,		// DTLB invalidate all register
213        IPR_DTB_IS = 0x20b,		// DTLB invalidate single register
214        IPR_ALT_MODE = 0x20c,	// alternate mode register
215        IPR_CC = 0x20d,		// cycle counter register
216        IPR_CC_CTL = 0x20e,		// cycle counter control register
217        IPR_MCSR = 0x20f,		// MTU control register
218
219        IPR_DC_FLUSH = 0x210,
220        IPR_DC_PERR_STAT = 0x212,	// Dcache parity error status register
221        IPR_DC_TEST_CTL = 0x213,	// Dcache test tag control register
222        IPR_DC_TEST_TAG = 0x214,	// Dcache test tag register
223        IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
224        IPR_DC_MODE = 0x216,	// Dcache mode register
225        IPR_MAF_MODE = 0x217,	// miss address file mode register
226
227        NumInternalProcRegs		// number of IPR registers
228    };
229#else
230    const int NumInternalProcRegs = 0;
231#endif
232
233    // Constants Related to the number of registers
234
235    const int NumIntArchRegs = 32;
236    const int NumPALShadowRegs = 8;
237    const int NumFloatArchRegs = 32;
238    // @todo: Figure out what this number really should be.
239    const int NumMiscArchRegs = 32;
240
241    const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
242    const int NumFloatRegs = NumFloatArchRegs;
243    const int NumMiscRegs = NumMiscArchRegs;
244
245    const int TotalNumRegs = NumIntRegs + NumFloatRegs +
246        NumMiscRegs + NumInternalProcRegs;
247
248    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
249
250    // Static instruction parameters
251    const int MaxInstSrcRegs = 3;
252    const int MaxInstDestRegs = 2;
253
254    // semantically meaningful register indices
255    const int ZeroReg = 31;	// architecturally meaningful
256    // the rest of these depend on the ABI
257    const int StackPointerReg = 30;
258    const int GlobalPointerReg = 29;
259    const int ProcedureValueReg = 27;
260    const int ReturnAddressReg = 26;
261    const int ReturnValueReg = 0;
262    const int FramePointerReg = 15;
263    const int ArgumentReg0 = 16;
264    const int ArgumentReg1 = 17;
265    const int ArgumentReg2 = 18;
266    const int ArgumentReg3 = 19;
267    const int ArgumentReg4 = 20;
268    const int ArgumentReg5 = 21;
269    const int SyscallNumReg = ReturnValueReg;
270    const int SyscallPseudoReturnReg = ArgumentReg4;
271    const int SyscallSuccessReg = 19;
272
273    const int LogVMPageSize = 13;	// 8K bytes
274    const int VMPageSize = (1 << LogVMPageSize);
275
276    const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
277
278    const int MachineBytes = 8;
279    const int WordBytes = 4;
280    const int HalfwordBytes = 2;
281    const int ByteBytes = 1;
282
283    // return a no-op instruction... used for instruction fetch faults
284    // Alpha UNOP (ldq_u r31,0(r0))
285    const ExtMachInst NoopMachInst = 0x2ffe0000;
286
287    // redirected register map, really only used for the full system case.
288    extern const int reg_redir[NumIntRegs];
289
290};
291
292#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
293