isa_traits.hh revision 2431 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
30#define __ARCH_ALPHA_ISA_TRAITS_HH__
31
32namespace LittleEndianGuest {}
33using namespace LittleEndianGuest;
34
35#include "arch/alpha/types.hh"
36#include "arch/alpha/constants.hh"
37#include "base/misc.hh"
38#include "config/full_system.hh"
39#include "sim/host.hh"
40#include "sim/faults.hh"
41
42class ExecContext;
43class FastCPU;
44class FullCPU;
45class Checkpoint;
46
47class StaticInst;
48class StaticInstPtr;
49
50#if !FULL_SYSTEM
51class SyscallReturn {
52        public:
53           template <class T>
54           SyscallReturn(T v, bool s)
55           {
56               retval = (uint64_t)v;
57               success = s;
58           }
59
60           template <class T>
61           SyscallReturn(T v)
62           {
63               success = (v >= 0);
64               retval = (uint64_t)v;
65           }
66
67           ~SyscallReturn() {}
68
69           SyscallReturn& operator=(const SyscallReturn& s) {
70               retval = s.retval;
71               success = s.success;
72               return *this;
73           }
74
75           bool successful() { return success; }
76           uint64_t value() { return retval; }
77
78
79       private:
80           uint64_t retval;
81           bool success;
82};
83
84#endif
85
86namespace AlphaISA
87{
88
89    typedef IntReg IntRegFile[NumIntRegs];
90
91    typedef union {
92        uint64_t q[NumFloatRegs];	// integer qword view
93        double d[NumFloatRegs];		// double-precision floating point view
94    } FloatRegFile;
95
96// redirected register map, really only used for the full system case.
97extern const int reg_redir[NumIntRegs];
98
99#if FULL_SYSTEM
100
101#include "arch/alpha/isa_fullsys_traits.hh"
102
103#endif
104    class MiscRegFile {
105      protected:
106        uint64_t	fpcr;		// floating point condition codes
107        uint64_t	uniq;		// process-unique register
108        bool		lock_flag;	// lock flag for LL/SC
109        Addr		lock_addr;	// lock address for LL/SC
110
111      public:
112        MiscReg readReg(int misc_reg);
113
114        //These functions should be removed once the simplescalar cpu model
115        //has been replaced.
116        int getInstAsid();
117        int getDataAsid();
118
119        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
120
121        Fault setReg(int misc_reg, const MiscReg &val);
122
123        Fault setRegWithEffect(int misc_reg, const MiscReg &val,
124                               ExecContext *xc);
125
126        void copyMiscRegs(ExecContext *xc);
127
128#if FULL_SYSTEM
129      protected:
130        typedef uint64_t InternalProcReg;
131
132        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
133
134      private:
135        InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc);
136
137        Fault setIpr(int idx, InternalProcReg val, ExecContext *xc);
138
139        void copyIprs(ExecContext *xc);
140#endif
141        friend class RegFile;
142    };
143
144    struct RegFile {
145        IntRegFile intRegFile;		// (signed) integer register file
146        FloatRegFile floatRegFile;	// floating point register file
147        MiscRegFile miscRegs;		// control register file
148        Addr pc;			// program counter
149        Addr npc;			// next-cycle program counter
150        Addr nnpc;
151
152#if FULL_SYSTEM
153        int intrflag;			// interrupt flag
154        inline int instAsid()
155        { return miscRegs.getInstAsid(); }
156        inline int dataAsid()
157        { return miscRegs.getDataAsid(); }
158#endif // FULL_SYSTEM
159
160        void serialize(std::ostream &os);
161        void unserialize(Checkpoint *cp, const std::string &section);
162    };
163
164    static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc);
165
166    StaticInstPtr decodeInst(ExtMachInst);
167
168    static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
169        panic("register classification not implemented");
170        return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
171    }
172
173    static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
174        panic("register classification not implemented");
175        return (reg >= 9 && reg <= 15);
176    }
177
178    static inline bool isCallerSaveFloatRegister(unsigned int reg) {
179        panic("register classification not implemented");
180        return false;
181    }
182
183    static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
184        panic("register classification not implemented");
185        return false;
186    }
187
188    static inline Addr alignAddress(const Addr &addr,
189                                         unsigned int nbytes) {
190        return (addr & ~(nbytes - 1));
191    }
192
193    // Instruction address compression hooks
194    static inline Addr realPCToFetchPC(const Addr &addr) {
195        return addr;
196    }
197
198    static inline Addr fetchPCToRealPC(const Addr &addr) {
199        return addr;
200    }
201
202    // the size of "fetched" instructions (not necessarily the size
203    // of real instructions for PISA)
204    static inline size_t fetchInstSize() {
205        return sizeof(MachInst);
206    }
207
208    static inline MachInst makeRegisterCopy(int dest, int src) {
209        panic("makeRegisterCopy not implemented");
210        return 0;
211    }
212
213    // Machine operations
214
215    void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
216                               int regnum);
217
218    void restoreMachineReg(RegFile &regs, const AnyReg &reg,
219                                  int regnum);
220
221#if 0
222    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
223                                     const RegFile &regs);
224
225    static void unserializeSpecialRegs(const IniFile *db,
226                                       const std::string &category,
227                                       ConfigNode *node,
228                                       RegFile &regs);
229#endif
230
231    /**
232     * Function to insure ISA semantics about 0 registers.
233     * @param xc The execution context.
234     */
235    template <class XC>
236    void zeroRegisters(XC *xc);
237
238#if !FULL_SYSTEM
239    static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
240    {
241        // check for error condition.  Alpha syscall convention is to
242        // indicate success/failure in reg a3 (r19) and put the
243        // return value itself in the standard return value reg (v0).
244        if (return_value.successful()) {
245            // no error
246            regs->intRegFile[SyscallSuccessReg] = 0;
247            regs->intRegFile[ReturnValueReg] = return_value.value();
248        } else {
249            // got an error, return details
250            regs->intRegFile[SyscallSuccessReg] = (IntReg) -1;
251            regs->intRegFile[ReturnValueReg] = -return_value.value();
252        }
253    }
254#endif
255};
256
257static inline AlphaISA::ExtMachInst
258AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) {
259#if FULL_SYSTEM
260    AlphaISA::ExtMachInst ext_inst = inst;
261    if (pc && 0x1)
262        return ext_inst|=(static_cast<AlphaISA::ExtMachInst>(pc & 0x1) << 32);
263    else
264        return ext_inst;
265#else
266    return AlphaISA::ExtMachInst(inst);
267#endif
268}
269
270#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
271