isa_traits.hh revision 2227 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
30#define __ARCH_ALPHA_ISA_TRAITS_HH__
31
32namespace LittleEndianGuest {}
33using namespace LittleEndianGuest;
34
35//#include "arch/alpha/faults.hh"
36#include "base/misc.hh"
37#include "config/full_system.hh"
38#include "sim/host.hh"
39#include "sim/faults.hh"
40
41class ExecContext;
42class FastCPU;
43class FullCPU;
44class Checkpoint;
45
46#define TARGET_ALPHA
47
48class StaticInst;
49class StaticInstPtr;
50
51namespace EV5 {
52int DTB_ASN_ASN(uint64_t reg);
53int ITB_ASN_ASN(uint64_t reg);
54}
55
56namespace AlphaISA
57{
58
59    typedef uint32_t MachInst;
60    typedef uint64_t ExtMachInst;
61//    typedef uint64_t Addr;
62    typedef uint8_t  RegIndex;
63
64    enum {
65        MemoryEnd = 0xffffffffffffffffULL,
66
67        NumIntArchRegs = 32,
68        NumPALShadowRegs = 8,
69        NumFloatArchRegs = 32,
70        // @todo: Figure out what this number really should be.
71        NumMiscArchRegs = 32,
72
73        MaxRegsOfAnyType = 32,
74        // Static instruction parameters
75        MaxInstSrcRegs = 3,
76        MaxInstDestRegs = 2,
77
78        // semantically meaningful register indices
79        ZeroReg = 31,	// architecturally meaningful
80        // the rest of these depend on the ABI
81        StackPointerReg = 30,
82        GlobalPointerReg = 29,
83        ProcedureValueReg = 27,
84        ReturnAddressReg = 26,
85        ReturnValueReg = 0,
86        FramePointerReg = 15,
87        ArgumentReg0 = 16,
88        ArgumentReg1 = 17,
89        ArgumentReg2 = 18,
90        ArgumentReg3 = 19,
91        ArgumentReg4 = 20,
92        ArgumentReg5 = 21,
93
94        LogVMPageSize = 13,	// 8K bytes
95        VMPageSize = (1 << LogVMPageSize),
96
97        BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
98
99        WordBytes = 4,
100        HalfwordBytes = 2,
101        ByteBytes = 1,
102        DepNA = 0,
103    };
104
105    enum {
106        NumIntRegs = NumIntArchRegs + NumPALShadowRegs,
107        NumFloatRegs = NumFloatArchRegs,
108        NumMiscRegs = NumMiscArchRegs
109    };
110
111    // These enumerate all the registers for dependence tracking.
112    enum DependenceTags {
113        // 0..31 are the integer regs 0..31
114        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
115        FP_Base_DepTag = 40,
116        Ctrl_Base_DepTag = 72,
117        Fpcr_DepTag = 72,		// floating point control register
118        Uniq_DepTag = 73,
119        Lock_Flag_DepTag = 74,
120        Lock_Addr_DepTag = 75,
121        IPR_Base_DepTag = 76
122    };
123
124    typedef uint64_t IntReg;
125    typedef IntReg IntRegFile[NumIntRegs];
126
127    // floating point register file entry type
128    typedef union {
129        uint64_t q;
130        double d;
131    } FloatReg;
132
133    typedef union {
134        uint64_t q[NumFloatRegs];	// integer qword view
135        double d[NumFloatRegs];		// double-precision floating point view
136    } FloatRegFile;
137
138extern const Addr PageShift;
139extern const Addr PageBytes;
140extern const Addr PageMask;
141extern const Addr PageOffset;
142
143// redirected register map, really only used for the full system case.
144extern const int reg_redir[NumIntRegs];
145
146#if FULL_SYSTEM
147
148    typedef uint64_t InternalProcReg;
149
150#include "arch/alpha/isa_fullsys_traits.hh"
151
152#else
153    enum {
154        NumInternalProcRegs = 0
155    };
156#endif
157
158    // control register file contents
159    typedef uint64_t MiscReg;
160    class MiscRegFile {
161      protected:
162        uint64_t	fpcr;		// floating point condition codes
163        uint64_t	uniq;		// process-unique register
164        bool		lock_flag;	// lock flag for LL/SC
165        Addr		lock_addr;	// lock address for LL/SC
166
167      public:
168        MiscReg readReg(int misc_reg);
169
170        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
171
172        Fault setReg(int misc_reg, const MiscReg &val);
173
174        Fault setRegWithEffect(int misc_reg, const MiscReg &val,
175                               ExecContext *xc);
176
177#if FULL_SYSTEM
178        void clearIprs();
179
180      protected:
181        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
182
183      private:
184        MiscReg readIpr(int idx, Fault &fault, ExecContext *xc);
185
186        Fault setIpr(int idx, uint64_t val, ExecContext *xc);
187#endif
188        friend class RegFile;
189    };
190
191    enum {
192        TotalNumRegs =
193        NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
194    };
195
196    enum {
197        TotalDataRegs = NumIntRegs + NumFloatRegs
198    };
199
200    typedef union {
201        IntReg  intreg;
202        FloatReg   fpreg;
203        MiscReg ctrlreg;
204    } AnyReg;
205
206    struct RegFile {
207        IntRegFile intRegFile;		// (signed) integer register file
208        FloatRegFile floatRegFile;	// floating point register file
209        MiscRegFile miscRegs;		// control register file
210        Addr pc;			// program counter
211        Addr npc;			// next-cycle program counter
212#if FULL_SYSTEM
213        int intrflag;			// interrupt flag
214        inline int instAsid()
215        { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
216        inline int dataAsid()
217        { return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); }
218#endif // FULL_SYSTEM
219
220        void serialize(std::ostream &os);
221        void unserialize(Checkpoint *cp, const std::string &section);
222    };
223
224    static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc);
225
226    StaticInstPtr decodeInst(ExtMachInst);
227
228    // return a no-op instruction... used for instruction fetch faults
229    extern const ExtMachInst NoopMachInst;
230
231    enum annotes {
232        ANNOTE_NONE = 0,
233        // An impossible number for instruction annotations
234        ITOUCH_ANNOTE = 0xffffffff,
235    };
236
237    static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
238        panic("register classification not implemented");
239        return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
240    }
241
242    static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
243        panic("register classification not implemented");
244        return (reg >= 9 && reg <= 15);
245    }
246
247    static inline bool isCallerSaveFloatRegister(unsigned int reg) {
248        panic("register classification not implemented");
249        return false;
250    }
251
252    static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
253        panic("register classification not implemented");
254        return false;
255    }
256
257    static inline Addr alignAddress(const Addr &addr,
258                                         unsigned int nbytes) {
259        return (addr & ~(nbytes - 1));
260    }
261
262    // Instruction address compression hooks
263    static inline Addr realPCToFetchPC(const Addr &addr) {
264        return addr;
265    }
266
267    static inline Addr fetchPCToRealPC(const Addr &addr) {
268        return addr;
269    }
270
271    // the size of "fetched" instructions (not necessarily the size
272    // of real instructions for PISA)
273    static inline size_t fetchInstSize() {
274        return sizeof(MachInst);
275    }
276
277    static inline MachInst makeRegisterCopy(int dest, int src) {
278        panic("makeRegisterCopy not implemented");
279        return 0;
280    }
281
282    // Machine operations
283
284    void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
285                               int regnum);
286
287    void restoreMachineReg(RegFile &regs, const AnyReg &reg,
288                                  int regnum);
289
290#if 0
291    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
292                                     const RegFile &regs);
293
294    static void unserializeSpecialRegs(const IniFile *db,
295                                       const std::string &category,
296                                       ConfigNode *node,
297                                       RegFile &regs);
298#endif
299
300    /**
301     * Function to insure ISA semantics about 0 registers.
302     * @param xc The execution context.
303     */
304    template <class XC>
305    void zeroRegisters(XC *xc);
306
307
308//typedef AlphaISA TheISA;
309
310//typedef TheISA::MachInst MachInst;
311//typedef TheISA::Addr Addr;
312//typedef TheISA::RegIndex RegIndex;
313//typedef TheISA::IntReg IntReg;
314//typedef TheISA::IntRegFile IntRegFile;
315//typedef TheISA::FloatReg FloatReg;
316//typedef TheISA::FloatRegFile FloatRegFile;
317//typedef TheISA::MiscReg MiscReg;
318//typedef TheISA::MiscRegFile MiscRegFile;
319//typedef TheISA::AnyReg AnyReg;
320//typedef TheISA::RegFile RegFile;
321
322//const int NumIntRegs   = TheISA::NumIntRegs;
323//const int NumFloatRegs = TheISA::NumFloatRegs;
324//const int NumMiscRegs  = TheISA::NumMiscRegs;
325//const int TotalNumRegs = TheISA::TotalNumRegs;
326//const int VMPageSize   = TheISA::VMPageSize;
327//const int LogVMPageSize   = TheISA::LogVMPageSize;
328//const int ZeroReg = TheISA::ZeroReg;
329//const int StackPointerReg = TheISA::StackPointerReg;
330//const int GlobalPointerReg = TheISA::GlobalPointerReg;
331//const int ReturnAddressReg = TheISA::ReturnAddressReg;
332//const int ReturnValueReg = TheISA::ReturnValueReg;
333//const int ArgumentReg0 = TheISA::ArgumentReg0;
334//const int ArgumentReg1 = TheISA::ArgumentReg1;
335//const int ArgumentReg2 = TheISA::ArgumentReg2;
336//const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
337const Addr MaxAddr = (Addr)-1;
338};
339
340#if !FULL_SYSTEM
341class SyscallReturn {
342        public:
343           template <class T>
344           SyscallReturn(T v, bool s)
345           {
346               retval = (uint64_t)v;
347               success = s;
348           }
349
350           template <class T>
351           SyscallReturn(T v)
352           {
353               success = (v >= 0);
354               retval = (uint64_t)v;
355           }
356
357           ~SyscallReturn() {}
358
359           SyscallReturn& operator=(const SyscallReturn& s) {
360               retval = s.retval;
361               success = s.success;
362               return *this;
363           }
364
365           bool successful() { return success; }
366           uint64_t value() { return retval; }
367
368
369       private:
370           uint64_t retval;
371           bool success;
372};
373
374#endif
375
376static inline AlphaISA::ExtMachInst
377AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) {
378#if FULL_SYSTEM
379    AlphaISA::ExtMachInst ext_inst = inst;
380    if (pc && 0x1)
381        return ext_inst|=(static_cast<AlphaISA::ExtMachInst>(pc & 0x1) << 32);
382    else
383        return ext_inst;
384#else
385    return AlphaISA::ExtMachInst(inst);
386#endif
387}
388
389#if FULL_SYSTEM
390//typedef TheISA::InternalProcReg InternalProcReg;
391//const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
392//const int NumInterruptLevels = TheISA::NumInterruptLevels;
393
394#include "arch/alpha/ev5.hh"
395#endif
396
397#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
398