isa_traits.hh revision 6227
12SN/A/* 21458SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Gabe Black 302SN/A */ 312SN/A 321147SN/A#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 331147SN/A#define __ARCH_ALPHA_ISA_TRAITS_HH__ 342SN/A 352037SN/Anamespace LittleEndianGuest {} 362037SN/A 373457Sgblack@eecs.umich.edu#include "arch/alpha/ipr.hh" 385228Sgblack@eecs.umich.edu#include "arch/alpha/max_inst_regs.hh" 392428SN/A#include "arch/alpha/types.hh" 406216Snate@binkert.org#include "base/types.hh" 411858SN/A#include "config/full_system.hh" 422SN/A 432107SN/Aclass StaticInstPtr; 442SN/A 455569Snate@binkert.orgnamespace AlphaISA { 462238SN/A 475569Snate@binkert.orgusing namespace LittleEndianGuest; 485569Snate@binkert.orgusing AlphaISAInst::MaxInstSrcRegs; 495569Snate@binkert.orgusing AlphaISAInst::MaxInstDestRegs; 502238SN/A 515569Snate@binkert.org// These enumerate all the registers for dependence tracking. 525569Snate@binkert.orgenum DependenceTags { 535569Snate@binkert.org // 0..31 are the integer regs 0..31 545569Snate@binkert.org // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 555569Snate@binkert.org FP_Base_DepTag = 40, 565569Snate@binkert.org Ctrl_Base_DepTag = 72 572264SN/A}; 582107SN/A 595569Snate@binkert.orgStaticInstPtr decodeInst(ExtMachInst); 605569Snate@binkert.org 615569Snate@binkert.org// Alpha Does NOT have a delay slot 625569Snate@binkert.org#define ISA_HAS_DELAY_SLOT 0 635569Snate@binkert.org 645569Snate@binkert.orgconst Addr PageShift = 13; 655569Snate@binkert.orgconst Addr PageBytes = ULL(1) << PageShift; 665569Snate@binkert.orgconst Addr PageMask = ~(PageBytes - 1); 675569Snate@binkert.orgconst Addr PageOffset = PageBytes - 1; 685569Snate@binkert.org 695569Snate@binkert.org//////////////////////////////////////////////////////////////////////// 705569Snate@binkert.org// 715569Snate@binkert.org// Translation stuff 725569Snate@binkert.org// 735569Snate@binkert.org 745569Snate@binkert.orgconst Addr PteShift = 3; 755569Snate@binkert.orgconst Addr NPtePageShift = PageShift - PteShift; 765569Snate@binkert.orgconst Addr NPtePage = ULL(1) << NPtePageShift; 775569Snate@binkert.orgconst Addr PteMask = NPtePage - 1; 785569Snate@binkert.org 795569Snate@binkert.org// User Virtual 805569Snate@binkert.orgconst Addr USegBase = ULL(0x0); 815569Snate@binkert.orgconst Addr USegEnd = ULL(0x000003ffffffffff); 825569Snate@binkert.org 835569Snate@binkert.org// Kernel Direct Mapped 845569Snate@binkert.orgconst Addr K0SegBase = ULL(0xfffffc0000000000); 855569Snate@binkert.orgconst Addr K0SegEnd = ULL(0xfffffdffffffffff); 865569Snate@binkert.org 875569Snate@binkert.org// Kernel Virtual 885569Snate@binkert.orgconst Addr K1SegBase = ULL(0xfffffe0000000000); 895569Snate@binkert.orgconst Addr K1SegEnd = ULL(0xffffffffffffffff); 905569Snate@binkert.org 915569Snate@binkert.org// For loading... XXX This maybe could be USegEnd?? --ali 925569Snate@binkert.orgconst Addr LoadAddrMask = ULL(0xffffffffff); 935569Snate@binkert.org 945569Snate@binkert.org//////////////////////////////////////////////////////////////////////// 955569Snate@binkert.org// 965569Snate@binkert.org// Interrupt levels 975569Snate@binkert.org// 985569Snate@binkert.orgenum InterruptLevels 995569Snate@binkert.org{ 1005569Snate@binkert.org INTLEVEL_SOFTWARE_MIN = 4, 1015569Snate@binkert.org INTLEVEL_SOFTWARE_MAX = 19, 1025569Snate@binkert.org 1035569Snate@binkert.org INTLEVEL_EXTERNAL_MIN = 20, 1045569Snate@binkert.org INTLEVEL_EXTERNAL_MAX = 34, 1055569Snate@binkert.org 1065569Snate@binkert.org INTLEVEL_IRQ0 = 20, 1075569Snate@binkert.org INTLEVEL_IRQ1 = 21, 1085569Snate@binkert.org INTINDEX_ETHERNET = 0, 1095569Snate@binkert.org INTINDEX_SCSI = 1, 1105569Snate@binkert.org INTLEVEL_IRQ2 = 22, 1115569Snate@binkert.org INTLEVEL_IRQ3 = 23, 1125569Snate@binkert.org 1135569Snate@binkert.org INTLEVEL_SERIAL = 33, 1145569Snate@binkert.org 1155569Snate@binkert.org NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 1165569Snate@binkert.org}; 1175569Snate@binkert.org 1185569Snate@binkert.org// EV5 modes 1195569Snate@binkert.orgenum mode_type 1205569Snate@binkert.org{ 1215569Snate@binkert.org mode_kernel = 0, // kernel 1225569Snate@binkert.org mode_executive = 1, // executive (unused by unix) 1235569Snate@binkert.org mode_supervisor = 2, // supervisor (unused by unix) 1245569Snate@binkert.org mode_user = 3, // user mode 1255569Snate@binkert.org mode_number // number of modes 1265569Snate@binkert.org}; 1275569Snate@binkert.org 1285569Snate@binkert.org// Constants Related to the number of registers 1295569Snate@binkert.org 1306227Snate@binkert.orgenum { 1316227Snate@binkert.org NumIntArchRegs = 32, 1326227Snate@binkert.org NumPALShadowRegs = 8, 1336227Snate@binkert.org NumFloatArchRegs = 32, 1346227Snate@binkert.org // @todo: Figure out what this number really should be. 1356227Snate@binkert.org NumMiscArchRegs = 77, 1365569Snate@binkert.org 1376227Snate@binkert.org NumIntRegs = NumIntArchRegs + NumPALShadowRegs, 1386227Snate@binkert.org NumFloatRegs = NumFloatArchRegs, 1396227Snate@binkert.org NumMiscRegs = NumMiscArchRegs, 1405569Snate@binkert.org 1416227Snate@binkert.org TotalNumRegs = 1426227Snate@binkert.org NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs, 1435569Snate@binkert.org 1446227Snate@binkert.org TotalDataRegs = NumIntRegs + NumFloatRegs, 1455569Snate@binkert.org 1466227Snate@binkert.org // semantically meaningful register indices 1476227Snate@binkert.org ZeroReg = 31, // architecturally meaningful 1486227Snate@binkert.org // the rest of these depend on the ABI 1496227Snate@binkert.org StackPointerReg = 30, 1506227Snate@binkert.org GlobalPointerReg = 29, 1516227Snate@binkert.org ProcedureValueReg = 27, 1526227Snate@binkert.org ReturnAddressReg = 26, 1536227Snate@binkert.org ReturnValueReg = 0, 1546227Snate@binkert.org FramePointerReg = 15, 1555569Snate@binkert.org 1566227Snate@binkert.org SyscallNumReg = 0, 1576227Snate@binkert.org FirstArgumentReg = 16, 1586227Snate@binkert.org SyscallPseudoReturnReg = 20, 1596227Snate@binkert.org SyscallSuccessReg = 19, 1605569Snate@binkert.org 1616227Snate@binkert.org LogVMPageSize = 13, // 8K bytes 1626227Snate@binkert.org VMPageSize = (1 << LogVMPageSize), 1635569Snate@binkert.org 1646227Snate@binkert.org BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned 1655569Snate@binkert.org 1666227Snate@binkert.org MachineBytes = 8, 1676227Snate@binkert.org WordBytes = 4, 1686227Snate@binkert.org HalfwordBytes = 2, 1696227Snate@binkert.org ByteBytes = 1, 1706227Snate@binkert.org}; 1715569Snate@binkert.org 1725569Snate@binkert.org// return a no-op instruction... used for instruction fetch faults 1735569Snate@binkert.org// Alpha UNOP (ldq_u r31,0(r0)) 1745569Snate@binkert.orgconst ExtMachInst NoopMachInst = 0x2ffe0000; 1755569Snate@binkert.org 1765569Snate@binkert.org} // namespace AlphaISA 1775569Snate@binkert.org 1781147SN/A#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 179