isa_traits.hh revision 5569
19651SAndreas.Sandberg@ARM.com/* 29651SAndreas.Sandberg@ARM.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 39651SAndreas.Sandberg@ARM.com * All rights reserved. 49651SAndreas.Sandberg@ARM.com * 59651SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 69651SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 79651SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 89651SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 99651SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 109651SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 119651SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 129651SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 139651SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 149651SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 159651SAndreas.Sandberg@ARM.com * 169651SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179651SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189651SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199651SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209651SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219651SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229651SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239651SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249651SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259651SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269651SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279651SAndreas.Sandberg@ARM.com * 289651SAndreas.Sandberg@ARM.com * Authors: Steve Reinhardt 299651SAndreas.Sandberg@ARM.com * Gabe Black 309651SAndreas.Sandberg@ARM.com */ 319651SAndreas.Sandberg@ARM.com 329651SAndreas.Sandberg@ARM.com#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 339651SAndreas.Sandberg@ARM.com#define __ARCH_ALPHA_ISA_TRAITS_HH__ 349651SAndreas.Sandberg@ARM.com 359651SAndreas.Sandberg@ARM.comnamespace LittleEndianGuest {} 369651SAndreas.Sandberg@ARM.com 379651SAndreas.Sandberg@ARM.com#include "arch/alpha/ipr.hh" 389651SAndreas.Sandberg@ARM.com#include "arch/alpha/max_inst_regs.hh" 399651SAndreas.Sandberg@ARM.com#include "arch/alpha/types.hh" 409651SAndreas.Sandberg@ARM.com#include "config/full_system.hh" 419651SAndreas.Sandberg@ARM.com#include "sim/host.hh" 429651SAndreas.Sandberg@ARM.com 439651SAndreas.Sandberg@ARM.comclass StaticInstPtr; 449651SAndreas.Sandberg@ARM.com 459651SAndreas.Sandberg@ARM.comnamespace AlphaISA { 469651SAndreas.Sandberg@ARM.com 479651SAndreas.Sandberg@ARM.comusing namespace LittleEndianGuest; 489651SAndreas.Sandberg@ARM.comusing AlphaISAInst::MaxInstSrcRegs; 499651SAndreas.Sandberg@ARM.comusing AlphaISAInst::MaxInstDestRegs; 509651SAndreas.Sandberg@ARM.com 519657Sandreas.sandberg@arm.com// These enumerate all the registers for dependence tracking. 529657Sandreas.sandberg@arm.comenum DependenceTags { 539657Sandreas.sandberg@arm.com // 0..31 are the integer regs 0..31 549883Sandreas@sandberg.pp.se // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 559883Sandreas@sandberg.pp.se FP_Base_DepTag = 40, 569883Sandreas@sandberg.pp.se Ctrl_Base_DepTag = 72 579657Sandreas.sandberg@arm.com}; 589651SAndreas.Sandberg@ARM.com 599651SAndreas.Sandberg@ARM.comStaticInstPtr decodeInst(ExtMachInst); 609651SAndreas.Sandberg@ARM.com 619651SAndreas.Sandberg@ARM.com// Alpha Does NOT have a delay slot 629651SAndreas.Sandberg@ARM.com#define ISA_HAS_DELAY_SLOT 0 639651SAndreas.Sandberg@ARM.com 649651SAndreas.Sandberg@ARM.comconst Addr PageShift = 13; 659651SAndreas.Sandberg@ARM.comconst Addr PageBytes = ULL(1) << PageShift; 669651SAndreas.Sandberg@ARM.comconst Addr PageMask = ~(PageBytes - 1); 679651SAndreas.Sandberg@ARM.comconst Addr PageOffset = PageBytes - 1; 68 69//////////////////////////////////////////////////////////////////////// 70// 71// Translation stuff 72// 73 74const Addr PteShift = 3; 75const Addr NPtePageShift = PageShift - PteShift; 76const Addr NPtePage = ULL(1) << NPtePageShift; 77const Addr PteMask = NPtePage - 1; 78 79// User Virtual 80const Addr USegBase = ULL(0x0); 81const Addr USegEnd = ULL(0x000003ffffffffff); 82 83// Kernel Direct Mapped 84const Addr K0SegBase = ULL(0xfffffc0000000000); 85const Addr K0SegEnd = ULL(0xfffffdffffffffff); 86 87// Kernel Virtual 88const Addr K1SegBase = ULL(0xfffffe0000000000); 89const Addr K1SegEnd = ULL(0xffffffffffffffff); 90 91// For loading... XXX This maybe could be USegEnd?? --ali 92const Addr LoadAddrMask = ULL(0xffffffffff); 93 94//////////////////////////////////////////////////////////////////////// 95// 96// Interrupt levels 97// 98enum InterruptLevels 99{ 100 INTLEVEL_SOFTWARE_MIN = 4, 101 INTLEVEL_SOFTWARE_MAX = 19, 102 103 INTLEVEL_EXTERNAL_MIN = 20, 104 INTLEVEL_EXTERNAL_MAX = 34, 105 106 INTLEVEL_IRQ0 = 20, 107 INTLEVEL_IRQ1 = 21, 108 INTINDEX_ETHERNET = 0, 109 INTINDEX_SCSI = 1, 110 INTLEVEL_IRQ2 = 22, 111 INTLEVEL_IRQ3 = 23, 112 113 INTLEVEL_SERIAL = 33, 114 115 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 116}; 117 118// EV5 modes 119enum mode_type 120{ 121 mode_kernel = 0, // kernel 122 mode_executive = 1, // executive (unused by unix) 123 mode_supervisor = 2, // supervisor (unused by unix) 124 mode_user = 3, // user mode 125 mode_number // number of modes 126}; 127 128// Constants Related to the number of registers 129 130const int NumIntArchRegs = 32; 131const int NumPALShadowRegs = 8; 132const int NumFloatArchRegs = 32; 133// @todo: Figure out what this number really should be. 134const int NumMiscArchRegs = 77; 135 136const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 137const int NumFloatRegs = NumFloatArchRegs; 138const int NumMiscRegs = NumMiscArchRegs; 139 140const int TotalNumRegs = 141 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs; 142 143const int TotalDataRegs = NumIntRegs + NumFloatRegs; 144 145// semantically meaningful register indices 146const int ZeroReg = 31; // architecturally meaningful 147// the rest of these depend on the ABI 148const int StackPointerReg = 30; 149const int GlobalPointerReg = 29; 150const int ProcedureValueReg = 27; 151const int ReturnAddressReg = 26; 152const int ReturnValueReg = 0; 153const int FramePointerReg = 15; 154 155const int ArgumentReg[] = {16, 17, 18, 19, 20, 21}; 156const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 157 158const int SyscallNumReg = ReturnValueReg; 159const int SyscallPseudoReturnReg = ArgumentReg[4]; 160const int SyscallSuccessReg = 19; 161 162const int LogVMPageSize = 13; // 8K bytes 163const int VMPageSize = (1 << LogVMPageSize); 164 165const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 166 167const int MachineBytes = 8; 168const int WordBytes = 4; 169const int HalfwordBytes = 2; 170const int ByteBytes = 1; 171 172// return a no-op instruction... used for instruction fetch faults 173// Alpha UNOP (ldq_u r31,0(r0)) 174const ExtMachInst NoopMachInst = 0x2ffe0000; 175 176} // namespace AlphaISA 177 178#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 179