isa_traits.hh revision 4997
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Gabe Black 30 */ 31 32#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 33#define __ARCH_ALPHA_ISA_TRAITS_HH__ 34 35namespace LittleEndianGuest {} 36 37#include "arch/alpha/ipr.hh" 38#include "arch/alpha/types.hh" 39#include "config/full_system.hh" 40#include "sim/host.hh" 41 42class StaticInstPtr; 43 44namespace AlphaISA 45{ 46 using namespace LittleEndianGuest; 47 48 // These enumerate all the registers for dependence tracking. 49 enum DependenceTags { 50 // 0..31 are the integer regs 0..31 51 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 52 FP_Base_DepTag = 40, 53 Ctrl_Base_DepTag = 72 54 }; 55 56 StaticInstPtr decodeInst(ExtMachInst); 57 58 // Alpha Does NOT have a delay slot 59 #define ISA_HAS_DELAY_SLOT 0 60 61 const Addr PageShift = 13; 62 const Addr PageBytes = ULL(1) << PageShift; 63 const Addr PageMask = ~(PageBytes - 1); 64 const Addr PageOffset = PageBytes - 1; 65 66 67 //////////////////////////////////////////////////////////////////////// 68 // 69 // Translation stuff 70 // 71 72 const Addr PteShift = 3; 73 const Addr NPtePageShift = PageShift - PteShift; 74 const Addr NPtePage = ULL(1) << NPtePageShift; 75 const Addr PteMask = NPtePage - 1; 76 77 // User Virtual 78 const Addr USegBase = ULL(0x0); 79 const Addr USegEnd = ULL(0x000003ffffffffff); 80 81 // Kernel Direct Mapped 82 const Addr K0SegBase = ULL(0xfffffc0000000000); 83 const Addr K0SegEnd = ULL(0xfffffdffffffffff); 84 85 // Kernel Virtual 86 const Addr K1SegBase = ULL(0xfffffe0000000000); 87 const Addr K1SegEnd = ULL(0xffffffffffffffff); 88 89 // For loading... XXX This maybe could be USegEnd?? --ali 90 const Addr LoadAddrMask = ULL(0xffffffffff); 91 92#if FULL_SYSTEM 93 94 //////////////////////////////////////////////////////////////////////// 95 // 96 // Interrupt levels 97 // 98 enum InterruptLevels 99 { 100 INTLEVEL_SOFTWARE_MIN = 4, 101 INTLEVEL_SOFTWARE_MAX = 19, 102 103 INTLEVEL_EXTERNAL_MIN = 20, 104 INTLEVEL_EXTERNAL_MAX = 34, 105 106 INTLEVEL_IRQ0 = 20, 107 INTLEVEL_IRQ1 = 21, 108 INTINDEX_ETHERNET = 0, 109 INTINDEX_SCSI = 1, 110 INTLEVEL_IRQ2 = 22, 111 INTLEVEL_IRQ3 = 23, 112 113 INTLEVEL_SERIAL = 33, 114 115 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 116 }; 117 118#endif 119 120 // EV5 modes 121 enum mode_type 122 { 123 mode_kernel = 0, // kernel 124 mode_executive = 1, // executive (unused by unix) 125 mode_supervisor = 2, // supervisor (unused by unix) 126 mode_user = 3, // user mode 127 mode_number // number of modes 128 }; 129 130 // Constants Related to the number of registers 131 132 const int NumIntArchRegs = 32; 133 const int NumPALShadowRegs = 8; 134 const int NumFloatArchRegs = 32; 135 // @todo: Figure out what this number really should be. 136 const int NumMiscArchRegs = 77; 137 138 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 139 const int NumFloatRegs = NumFloatArchRegs; 140 const int NumMiscRegs = NumMiscArchRegs; 141 142 const int TotalNumRegs = NumIntRegs + NumFloatRegs + 143 NumMiscRegs + NumInternalProcRegs; 144 145 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 146 147 // Static instruction parameters 148 const int MaxInstSrcRegs = 3; 149 const int MaxInstDestRegs = 2; 150 151 // semantically meaningful register indices 152 const int ZeroReg = 31; // architecturally meaningful 153 // the rest of these depend on the ABI 154 const int StackPointerReg = 30; 155 const int GlobalPointerReg = 29; 156 const int ProcedureValueReg = 27; 157 const int ReturnAddressReg = 26; 158 const int ReturnValueReg = 0; 159 const int FramePointerReg = 15; 160 161 const int ArgumentReg[] = {16, 17, 18, 19, 20, 21}; 162 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 163 164 const int SyscallNumReg = ReturnValueReg; 165 const int SyscallPseudoReturnReg = ArgumentReg[4]; 166 const int SyscallSuccessReg = 19; 167 168 const int LogVMPageSize = 13; // 8K bytes 169 const int VMPageSize = (1 << LogVMPageSize); 170 171 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 172 173 const int MachineBytes = 8; 174 const int WordBytes = 4; 175 const int HalfwordBytes = 2; 176 const int ByteBytes = 1; 177 178 // return a no-op instruction... used for instruction fetch faults 179 // Alpha UNOP (ldq_u r31,0(r0)) 180 const ExtMachInst NoopMachInst = 0x2ffe0000; 181 182}; 183 184#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 185