isa_traits.hh revision 3454
12SN/A/*
21458SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292665Ssaidi@eecs.umich.edu *          Gabe Black
302SN/A */
312SN/A
321147SN/A#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
331147SN/A#define __ARCH_ALPHA_ISA_TRAITS_HH__
342SN/A
352037SN/Anamespace LittleEndianGuest {}
362037SN/A
372428SN/A#include "arch/alpha/types.hh"
381858SN/A#include "config/full_system.hh"
3956SN/A#include "sim/host.hh"
402SN/A
412107SN/Aclass StaticInstPtr;
422SN/A
432972Sgblack@eecs.umich.edunamespace AlphaISA
442972Sgblack@eecs.umich.edu{
452972Sgblack@eecs.umich.edu    using namespace LittleEndianGuest;
462238SN/A
472972Sgblack@eecs.umich.edu    // These enumerate all the registers for dependence tracking.
482972Sgblack@eecs.umich.edu    enum DependenceTags {
492972Sgblack@eecs.umich.edu        // 0..31 are the integer regs 0..31
502972Sgblack@eecs.umich.edu        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
512972Sgblack@eecs.umich.edu        FP_Base_DepTag = 40,
522972Sgblack@eecs.umich.edu        Ctrl_Base_DepTag = 72,
532972Sgblack@eecs.umich.edu        Fpcr_DepTag = 72,		// floating point control register
542972Sgblack@eecs.umich.edu        Uniq_DepTag = 73,
552972Sgblack@eecs.umich.edu        Lock_Flag_DepTag = 74,
562972Sgblack@eecs.umich.edu        Lock_Addr_DepTag = 75,
573454Sgblack@eecs.umich.edu        Intr_Flag_DepTag = 76,
583454Sgblack@eecs.umich.edu        IPR_Base_DepTag = 77
592972Sgblack@eecs.umich.edu    };
602238SN/A
612972Sgblack@eecs.umich.edu    StaticInstPtr decodeInst(ExtMachInst);
622238SN/A
633093Sksewell@umich.edu    // Alpha Does NOT have a delay slot
643093Sksewell@umich.edu    #define ISA_HAS_DELAY_SLOT 0
653093Sksewell@umich.edu
662972Sgblack@eecs.umich.edu    const Addr PageShift = 13;
672972Sgblack@eecs.umich.edu    const Addr PageBytes = ULL(1) << PageShift;
682972Sgblack@eecs.umich.edu    const Addr PageMask = ~(PageBytes - 1);
692972Sgblack@eecs.umich.edu    const Addr PageOffset = PageBytes - 1;
702972Sgblack@eecs.umich.edu
712972Sgblack@eecs.umich.edu#if FULL_SYSTEM
722972Sgblack@eecs.umich.edu
732972Sgblack@eecs.umich.edu    ////////////////////////////////////////////////////////////////////////
742972Sgblack@eecs.umich.edu    //
752972Sgblack@eecs.umich.edu    //  Translation stuff
762972Sgblack@eecs.umich.edu    //
772972Sgblack@eecs.umich.edu
782972Sgblack@eecs.umich.edu   const Addr PteShift = 3;
792972Sgblack@eecs.umich.edu    const Addr NPtePageShift = PageShift - PteShift;
802972Sgblack@eecs.umich.edu    const Addr NPtePage = ULL(1) << NPtePageShift;
812972Sgblack@eecs.umich.edu    const Addr PteMask = NPtePage - 1;
822972Sgblack@eecs.umich.edu
832972Sgblack@eecs.umich.edu    // User Virtual
842972Sgblack@eecs.umich.edu    const Addr USegBase = ULL(0x0);
852972Sgblack@eecs.umich.edu    const Addr USegEnd = ULL(0x000003ffffffffff);
862972Sgblack@eecs.umich.edu
872972Sgblack@eecs.umich.edu    // Kernel Direct Mapped
882972Sgblack@eecs.umich.edu    const Addr K0SegBase = ULL(0xfffffc0000000000);
892972Sgblack@eecs.umich.edu    const Addr K0SegEnd = ULL(0xfffffdffffffffff);
902972Sgblack@eecs.umich.edu
912972Sgblack@eecs.umich.edu    // Kernel Virtual
922972Sgblack@eecs.umich.edu    const Addr K1SegBase = ULL(0xfffffe0000000000);
932972Sgblack@eecs.umich.edu    const Addr K1SegEnd = ULL(0xffffffffffffffff);
942972Sgblack@eecs.umich.edu
952972Sgblack@eecs.umich.edu    // For loading... XXX This maybe could be USegEnd?? --ali
962972Sgblack@eecs.umich.edu    const Addr LoadAddrMask = ULL(0xffffffffff);
972972Sgblack@eecs.umich.edu
982972Sgblack@eecs.umich.edu    ////////////////////////////////////////////////////////////////////////
992972Sgblack@eecs.umich.edu    //
1002972Sgblack@eecs.umich.edu    //  Interrupt levels
1012972Sgblack@eecs.umich.edu    //
1022972Sgblack@eecs.umich.edu    enum InterruptLevels
1032972Sgblack@eecs.umich.edu    {
1042972Sgblack@eecs.umich.edu        INTLEVEL_SOFTWARE_MIN = 4,
1052972Sgblack@eecs.umich.edu        INTLEVEL_SOFTWARE_MAX = 19,
1062972Sgblack@eecs.umich.edu
1072972Sgblack@eecs.umich.edu        INTLEVEL_EXTERNAL_MIN = 20,
1082972Sgblack@eecs.umich.edu        INTLEVEL_EXTERNAL_MAX = 34,
1092972Sgblack@eecs.umich.edu
1102972Sgblack@eecs.umich.edu        INTLEVEL_IRQ0 = 20,
1112972Sgblack@eecs.umich.edu        INTLEVEL_IRQ1 = 21,
1122972Sgblack@eecs.umich.edu        INTINDEX_ETHERNET = 0,
1132972Sgblack@eecs.umich.edu        INTINDEX_SCSI = 1,
1142972Sgblack@eecs.umich.edu        INTLEVEL_IRQ2 = 22,
1152972Sgblack@eecs.umich.edu        INTLEVEL_IRQ3 = 23,
1162972Sgblack@eecs.umich.edu
1172972Sgblack@eecs.umich.edu        INTLEVEL_SERIAL = 33,
1182972Sgblack@eecs.umich.edu
1192972Sgblack@eecs.umich.edu        NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
1202972Sgblack@eecs.umich.edu    };
1212972Sgblack@eecs.umich.edu
1222972Sgblack@eecs.umich.edu
1232972Sgblack@eecs.umich.edu    // EV5 modes
1242972Sgblack@eecs.umich.edu    enum mode_type
1252972Sgblack@eecs.umich.edu    {
1262972Sgblack@eecs.umich.edu        mode_kernel = 0,		// kernel
1272972Sgblack@eecs.umich.edu        mode_executive = 1,		// executive (unused by unix)
1282972Sgblack@eecs.umich.edu        mode_supervisor = 2,	// supervisor (unused by unix)
1292972Sgblack@eecs.umich.edu        mode_user = 3,		// user mode
1302972Sgblack@eecs.umich.edu        mode_number			// number of modes
1312972Sgblack@eecs.umich.edu    };
1322238SN/A
1332238SN/A#endif
1342238SN/A
1352512SN/A#if FULL_SYSTEM
1362972Sgblack@eecs.umich.edu    ////////////////////////////////////////////////////////////////////////
1372972Sgblack@eecs.umich.edu    //
1382972Sgblack@eecs.umich.edu    //  Internal Processor Reigsters
1392972Sgblack@eecs.umich.edu    //
1402972Sgblack@eecs.umich.edu    enum md_ipr_names
1412972Sgblack@eecs.umich.edu    {
1422972Sgblack@eecs.umich.edu        IPR_ISR = 0x100,		// interrupt summary register
1432972Sgblack@eecs.umich.edu        IPR_ITB_TAG = 0x101,	// ITLB tag register
1442972Sgblack@eecs.umich.edu        IPR_ITB_PTE = 0x102,	// ITLB page table entry register
1452972Sgblack@eecs.umich.edu        IPR_ITB_ASN = 0x103,	// ITLB address space register
1462972Sgblack@eecs.umich.edu        IPR_ITB_PTE_TEMP = 0x104,	// ITLB page table entry temp register
1472972Sgblack@eecs.umich.edu        IPR_ITB_IA = 0x105,		// ITLB invalidate all register
1482972Sgblack@eecs.umich.edu        IPR_ITB_IAP = 0x106,	// ITLB invalidate all process register
1492972Sgblack@eecs.umich.edu        IPR_ITB_IS = 0x107,		// ITLB invalidate select register
1502972Sgblack@eecs.umich.edu        IPR_SIRR = 0x108,		// software interrupt request register
1512972Sgblack@eecs.umich.edu        IPR_ASTRR = 0x109,		// asynchronous system trap request register
1522972Sgblack@eecs.umich.edu        IPR_ASTER = 0x10a,		// asynchronous system trap enable register
1532972Sgblack@eecs.umich.edu        IPR_EXC_ADDR = 0x10b,	// exception address register
1542972Sgblack@eecs.umich.edu        IPR_EXC_SUM = 0x10c,	// exception summary register
1552972Sgblack@eecs.umich.edu        IPR_EXC_MASK = 0x10d,	// exception mask register
1562972Sgblack@eecs.umich.edu        IPR_PAL_BASE = 0x10e,	// PAL base address register
1572972Sgblack@eecs.umich.edu        IPR_ICM = 0x10f,		// instruction current mode
1582972Sgblack@eecs.umich.edu        IPR_IPLR = 0x110,		// interrupt priority level register
1592972Sgblack@eecs.umich.edu        IPR_INTID = 0x111,		// interrupt ID register
1602972Sgblack@eecs.umich.edu        IPR_IFAULT_VA_FORM = 0x112,	// formatted faulting virtual addr register
1612972Sgblack@eecs.umich.edu        IPR_IVPTBR = 0x113,		// virtual page table base register
1622972Sgblack@eecs.umich.edu        IPR_HWINT_CLR = 0x115,	// H/W interrupt clear register
1632972Sgblack@eecs.umich.edu        IPR_SL_XMIT = 0x116,	// serial line transmit register
1642972Sgblack@eecs.umich.edu        IPR_SL_RCV = 0x117,		// serial line receive register
1652972Sgblack@eecs.umich.edu        IPR_ICSR = 0x118,		// instruction control and status register
1662972Sgblack@eecs.umich.edu        IPR_IC_FLUSH = 0x119,	// instruction cache flush control
1672972Sgblack@eecs.umich.edu        IPR_IC_PERR_STAT = 0x11a,	// inst cache parity error status register
1682972Sgblack@eecs.umich.edu        IPR_PMCTR = 0x11c,		// performance counter register
1692972Sgblack@eecs.umich.edu
1702972Sgblack@eecs.umich.edu        // PAL temporary registers...
1712972Sgblack@eecs.umich.edu        // register meanings gleaned from osfpal.s source code
1722972Sgblack@eecs.umich.edu        IPR_PALtemp0 = 0x140,	// local scratch
1732972Sgblack@eecs.umich.edu        IPR_PALtemp1 = 0x141,	// local scratch
1742972Sgblack@eecs.umich.edu        IPR_PALtemp2 = 0x142,	// entUna
1752972Sgblack@eecs.umich.edu        IPR_PALtemp3 = 0x143,	// CPU specific impure area pointer
1762972Sgblack@eecs.umich.edu        IPR_PALtemp4 = 0x144,	// memory management temp
1772972Sgblack@eecs.umich.edu        IPR_PALtemp5 = 0x145,	// memory management temp
1782972Sgblack@eecs.umich.edu        IPR_PALtemp6 = 0x146,	// memory management temp
1792972Sgblack@eecs.umich.edu        IPR_PALtemp7 = 0x147,	// entIF
1802972Sgblack@eecs.umich.edu        IPR_PALtemp8 = 0x148,	// intmask
1812972Sgblack@eecs.umich.edu        IPR_PALtemp9 = 0x149,	// entSys
1822972Sgblack@eecs.umich.edu        IPR_PALtemp10 = 0x14a,	// ??
1832972Sgblack@eecs.umich.edu        IPR_PALtemp11 = 0x14b,	// entInt
1842972Sgblack@eecs.umich.edu        IPR_PALtemp12 = 0x14c,	// entArith
1852972Sgblack@eecs.umich.edu        IPR_PALtemp13 = 0x14d,	// reserved for platform specific PAL
1862972Sgblack@eecs.umich.edu        IPR_PALtemp14 = 0x14e,	// reserved for platform specific PAL
1872972Sgblack@eecs.umich.edu        IPR_PALtemp15 = 0x14f,	// reserved for platform specific PAL
1882972Sgblack@eecs.umich.edu        IPR_PALtemp16 = 0x150,	// scratch / whami<7:0> / mces<4:0>
1892972Sgblack@eecs.umich.edu        IPR_PALtemp17 = 0x151,	// sysval
1902972Sgblack@eecs.umich.edu        IPR_PALtemp18 = 0x152,	// usp
1912972Sgblack@eecs.umich.edu        IPR_PALtemp19 = 0x153,	// ksp
1922972Sgblack@eecs.umich.edu        IPR_PALtemp20 = 0x154,	// PTBR
1932972Sgblack@eecs.umich.edu        IPR_PALtemp21 = 0x155,	// entMM
1942972Sgblack@eecs.umich.edu        IPR_PALtemp22 = 0x156,	// kgp
1952972Sgblack@eecs.umich.edu        IPR_PALtemp23 = 0x157,	// PCBB
1962972Sgblack@eecs.umich.edu
1972972Sgblack@eecs.umich.edu        IPR_DTB_ASN = 0x200,	// DTLB address space number register
1982972Sgblack@eecs.umich.edu        IPR_DTB_CM = 0x201,		// DTLB current mode register
1992972Sgblack@eecs.umich.edu        IPR_DTB_TAG = 0x202,	// DTLB tag register
2002972Sgblack@eecs.umich.edu        IPR_DTB_PTE = 0x203,	// DTLB page table entry register
2012972Sgblack@eecs.umich.edu        IPR_DTB_PTE_TEMP = 0x204,	// DTLB page table entry temporary register
2022972Sgblack@eecs.umich.edu
2032972Sgblack@eecs.umich.edu        IPR_MM_STAT = 0x205,	// data MMU fault status register
2042972Sgblack@eecs.umich.edu        IPR_VA = 0x206,		// fault virtual address register
2052972Sgblack@eecs.umich.edu        IPR_VA_FORM = 0x207,	// formatted virtual address register
2062972Sgblack@eecs.umich.edu        IPR_MVPTBR = 0x208,		// MTU virtual page table base register
2072972Sgblack@eecs.umich.edu        IPR_DTB_IAP = 0x209,	// DTLB invalidate all process register
2082972Sgblack@eecs.umich.edu        IPR_DTB_IA = 0x20a,		// DTLB invalidate all register
2092972Sgblack@eecs.umich.edu        IPR_DTB_IS = 0x20b,		// DTLB invalidate single register
2102972Sgblack@eecs.umich.edu        IPR_ALT_MODE = 0x20c,	// alternate mode register
2112972Sgblack@eecs.umich.edu        IPR_CC = 0x20d,		// cycle counter register
2122972Sgblack@eecs.umich.edu        IPR_CC_CTL = 0x20e,		// cycle counter control register
2132972Sgblack@eecs.umich.edu        IPR_MCSR = 0x20f,		// MTU control register
2142972Sgblack@eecs.umich.edu
2152972Sgblack@eecs.umich.edu        IPR_DC_FLUSH = 0x210,
2162972Sgblack@eecs.umich.edu        IPR_DC_PERR_STAT = 0x212,	// Dcache parity error status register
2172972Sgblack@eecs.umich.edu        IPR_DC_TEST_CTL = 0x213,	// Dcache test tag control register
2182972Sgblack@eecs.umich.edu        IPR_DC_TEST_TAG = 0x214,	// Dcache test tag register
2192972Sgblack@eecs.umich.edu        IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
2202972Sgblack@eecs.umich.edu        IPR_DC_MODE = 0x216,	// Dcache mode register
2212972Sgblack@eecs.umich.edu        IPR_MAF_MODE = 0x217,	// miss address file mode register
2222972Sgblack@eecs.umich.edu
2232972Sgblack@eecs.umich.edu        NumInternalProcRegs		// number of IPR registers
2242972Sgblack@eecs.umich.edu    };
2252972Sgblack@eecs.umich.edu#else
2262972Sgblack@eecs.umich.edu    const int NumInternalProcRegs = 0;
2272512SN/A#endif
2282512SN/A
2292972Sgblack@eecs.umich.edu    // Constants Related to the number of registers
2302512SN/A
2312972Sgblack@eecs.umich.edu    const int NumIntArchRegs = 32;
2322972Sgblack@eecs.umich.edu    const int NumPALShadowRegs = 8;
2332972Sgblack@eecs.umich.edu    const int NumFloatArchRegs = 32;
2342972Sgblack@eecs.umich.edu    // @todo: Figure out what this number really should be.
2352972Sgblack@eecs.umich.edu    const int NumMiscArchRegs = 32;
2362SN/A
2372972Sgblack@eecs.umich.edu    const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
2382972Sgblack@eecs.umich.edu    const int NumFloatRegs = NumFloatArchRegs;
2392972Sgblack@eecs.umich.edu    const int NumMiscRegs = NumMiscArchRegs;
2402449SN/A
2412972Sgblack@eecs.umich.edu    const int TotalNumRegs = NumIntRegs + NumFloatRegs +
2422972Sgblack@eecs.umich.edu        NumMiscRegs + NumInternalProcRegs;
2432227SN/A
2442972Sgblack@eecs.umich.edu    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
2452SN/A
2462972Sgblack@eecs.umich.edu    // Static instruction parameters
2472972Sgblack@eecs.umich.edu    const int MaxInstSrcRegs = 3;
2482972Sgblack@eecs.umich.edu    const int MaxInstDestRegs = 2;
2492972Sgblack@eecs.umich.edu
2502972Sgblack@eecs.umich.edu    // semantically meaningful register indices
2512972Sgblack@eecs.umich.edu    const int ZeroReg = 31;	// architecturally meaningful
2522972Sgblack@eecs.umich.edu    // the rest of these depend on the ABI
2532972Sgblack@eecs.umich.edu    const int StackPointerReg = 30;
2542972Sgblack@eecs.umich.edu    const int GlobalPointerReg = 29;
2552972Sgblack@eecs.umich.edu    const int ProcedureValueReg = 27;
2562972Sgblack@eecs.umich.edu    const int ReturnAddressReg = 26;
2572972Sgblack@eecs.umich.edu    const int ReturnValueReg = 0;
2582972Sgblack@eecs.umich.edu    const int FramePointerReg = 15;
2592972Sgblack@eecs.umich.edu    const int ArgumentReg0 = 16;
2602972Sgblack@eecs.umich.edu    const int ArgumentReg1 = 17;
2612972Sgblack@eecs.umich.edu    const int ArgumentReg2 = 18;
2622972Sgblack@eecs.umich.edu    const int ArgumentReg3 = 19;
2632972Sgblack@eecs.umich.edu    const int ArgumentReg4 = 20;
2642972Sgblack@eecs.umich.edu    const int ArgumentReg5 = 21;
2652972Sgblack@eecs.umich.edu    const int SyscallNumReg = ReturnValueReg;
2662972Sgblack@eecs.umich.edu    const int SyscallPseudoReturnReg = ArgumentReg4;
2672972Sgblack@eecs.umich.edu    const int SyscallSuccessReg = 19;
2682972Sgblack@eecs.umich.edu
2692972Sgblack@eecs.umich.edu    const int LogVMPageSize = 13;	// 8K bytes
2702972Sgblack@eecs.umich.edu    const int VMPageSize = (1 << LogVMPageSize);
2712972Sgblack@eecs.umich.edu
2722972Sgblack@eecs.umich.edu    const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
2732972Sgblack@eecs.umich.edu
2742972Sgblack@eecs.umich.edu    const int MachineBytes = 8;
2752972Sgblack@eecs.umich.edu    const int WordBytes = 4;
2762972Sgblack@eecs.umich.edu    const int HalfwordBytes = 2;
2772972Sgblack@eecs.umich.edu    const int ByteBytes = 1;
2782972Sgblack@eecs.umich.edu
2792972Sgblack@eecs.umich.edu    // return a no-op instruction... used for instruction fetch faults
2802972Sgblack@eecs.umich.edu    // Alpha UNOP (ldq_u r31,0(r0))
2812972Sgblack@eecs.umich.edu    const ExtMachInst NoopMachInst = 0x2ffe0000;
2822972Sgblack@eecs.umich.edu
2832972Sgblack@eecs.umich.edu    // redirected register map, really only used for the full system case.
2842972Sgblack@eecs.umich.edu    extern const int reg_redir[NumIntRegs];
2852972Sgblack@eecs.umich.edu
2862264SN/A};
2872107SN/A
2881147SN/A#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
289